/* Generated by Yosys 0.51 (git sha1 c4b5190229616f7ebf8197f43990b4429de3e420, g++ 14.2.1 -fPIC -O3) */

(* top =  1  *)
(* src = "/home/runner/workspace/hardware/ti60_f225.py:56" *)
(* generator = "Amaranth" *)
module church_ti60f225(clk, push_button, uart_tx, dbg_nia, dbg_fault, dbg_fault_valid, dbg_boot_complete, led0, led1, led2, led3, uart_rx);
  reg \$auto$verilog_backend.cc:2355:dump_module$41  = 0;
  wire \$1 ;
  wire \$10 ;
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  wire \$199 ;
  wire \$2 ;
  wire \$20 ;
  wire [16:0] \$200 ;
  wire [16:0] \$201 ;
  wire \$202 ;
  reg [31:0] \$203 ;
  reg \$204 ;
  reg [2:0] \$205 ;
  reg [2:0] \$206 ;
  reg [2:0] \$207 ;
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  wire \$21 ;
  reg [31:0] \$210 ;
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  reg \$212 ;
  reg [7:0] \$213 ;
  reg \$214 ;
  wire [2:0] \$215 ;
  reg [24:0] \$216 ;
  reg \$217 ;
  reg \$218 ;
  reg [7:0] \$219 ;
  wire \$22 ;
  reg [24:0] \$220 ;
  reg \$221 ;
  reg [23:0] \$222 ;
  reg [2:0] \$223 ;
  reg [3:0] \$224 ;
  reg \$225 ;
  reg [27:0] \$226 ;
  reg [5:0] \$227 ;
  reg [4:0] \$228 ;
  reg \$229 ;
  wire \$23 ;
  reg \$230 ;
  reg [4:0] \$231 ;
  reg [1:0] \$232 ;
  reg \$233 ;
  reg [2:0] \$234 ;
  reg \$235 ;
  reg [7:0] \$236 ;
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  reg [31:0] \$238 ;
  reg [31:0] \$239 ;
  wire \$24 ;
  reg [3:0] \$240 ;
  reg \$241 ;
  reg [1:0] \$242 ;
  reg [1:0] \$243 ;
  reg [15:0] \$244 ;
  reg [15:0] \$245 ;
  reg [15:0] \$246 ;
  reg [15:0] \$247 ;
  reg [31:0] \$248 ;
  reg [7:0] \$249 ;
  wire \$25 ;
  reg \$250 ;
  reg [7:0] \$251 ;
  reg [7:0] \$252 ;
  reg [7:0] \$253 ;
  reg [7:0] \$254 ;
  reg [2:0] \$255 ;
  reg [15:0] \$256 ;
  reg [15:0] \$257 ;
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  reg [31:0] \$259 ;
  wire \$26 ;
  wire \$27 ;
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  wire \$3 ;
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  wire \$4 ;
  wire \$40 ;
  wire \$41 ;
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  wire \$48 ;
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  wire \$5 ;
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  wire \$51 ;
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  wire \$6 ;
  wire \$60 ;
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  wire \$7 ;
  wire \$70 ;
  wire \$71 ;
  reg [7:0] \$72 ;
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  wire \$96 ;
  wire \$97 ;
  wire \$98 ;
  wire \$99 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:257" *)
  reg _dmem_rd_valid_r = 1'h0;
  (* src = "/home/runner/workspace/hardware/boot_rom.py:669" *)
  wire [9:0] addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:181" *)
  reg alarm_armed = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:180" *)
  reg [31:0] alarm_cmp = 32'd0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:182" *)
  reg alarm_fired = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:119" *)
  wire any_clist_access;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:118" *)
  wire any_ns_access;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:479" *)
  reg [7:0] banner_byte;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:446" *)
  reg banner_ever_sent = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:478" *)
  reg [4:0] banner_idx = 5'h00;
  (* src = "/home/runner/workspace/hardware/core.py:78" *)
  wire boot_complete;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:464" *)
  reg [3:0] boot_delay = 4'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:510" *)
  reg [7:0] boot_reason = 8'h00;
  (* src = "/home/runner/workspace/hardware/core.py:76" *)
  reg boot_start;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:465" *)
  reg boot_triggered = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:354" *)
  reg [24:0] btn_hold_ctr = 25'h0000000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:355" *)
  reg btn_hold_done = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:349" *)
  wire btn_press;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:342" *)
  reg btn_prev = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:341" *)
  reg [2:0] btn_sync = 3'h0;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:93" *)
  wire busy;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:92" *)
  reg [7:0] byte_data;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:492" *)
  reg [7:0] callhome_byte;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:491" *)
  reg [4:0] callhome_idx = 5'h00;
  (* src = "/home/runner/workspace/hardware/core.py:70" *)
  wire [31:0] clist_addr;
  (* src = "/home/runner/workspace/hardware/core.py:72" *)
  wire [31:0] clist_rd_data;
  (* src = "/home/runner/workspace/hardware/core.py:72" *)
  wire \clist_rd_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:72" *)
  wire \clist_rd_data.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:72" *)
  wire [8:0] \clist_rd_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:72" *)
  wire [1:0] \clist_rd_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:72" *)
  wire [2:0] \clist_rd_data.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:72" *)
  wire [15:0] \clist_rd_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:71" *)
  wire clist_rd_en;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [31:0] clist_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire \clist_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire \clist_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [8:0] \clist_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [1:0] \clist_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [2:0] \clist_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [15:0] \clist_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:74" *)
  wire clist_wr_en;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:308" *)
  reg [31:0] cpu_wr_data;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:309" *)
  reg cpu_wr_en;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:21" *)
  wire [15:0] crc;
  (* src = "/home/runner/workspace/hardware/boot_rom.py:670" *)
  wire [31:0] data;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:89" *)
  reg [31:0] \data$120 ;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:20" *)
  wire [7:0] \data$123 ;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:20" *)
  reg [7:0] data_in;
  (* src = "/home/runner/workspace/hardware/core.py:78" *)
  output dbg_boot_complete;
  wire dbg_boot_complete;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:51" *)
  output [3:0] dbg_fault;
  wire [3:0] dbg_fault;
  (* src = "/home/runner/workspace/hardware/core.py:85" *)
  output dbg_fault_valid;
  wire dbg_fault_valid;
  (* src = "/home/runner/workspace/hardware/core.py:99" *)
  output [31:0] dbg_nia;
  wire [31:0] dbg_nia;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [5:0] debug_fsm_state = 6'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:422" *)
  reg [23:0] demo_ctr = 24'h000000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:424" *)
  wire demo_led0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:424" *)
  wire demo_led1;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:424" *)
  wire demo_led2;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:424" *)
  wire demo_led3;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:423" *)
  reg [2:0] demo_phase = 3'h0;
  (* src = "/home/runner/workspace/hardware/core.py:57" *)
  wire [31:0] dmem_addr;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:240" *)
  wire [13:0] dmem_rd__addr;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:241" *)
  wire [31:0] dmem_rd__data;
  (* src = "/home/runner/workspace/hardware/core.py:59" *)
  wire [31:0] dmem_rd_data;
  (* src = "/home/runner/workspace/hardware/core.py:58" *)
  wire dmem_rd_en;
  (* src = "/home/runner/workspace/hardware/core.py:60" *)
  wire dmem_rd_valid;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:401" *)
  reg [13:0] dmem_wr__addr;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:402" *)
  reg [31:0] dmem_wr__data;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:400" *)
  reg dmem_wr__en;
  (* src = "/home/runner/workspace/hardware/core.py:61" *)
  wire [31:0] dmem_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:62" *)
  wire dmem_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:84" *)
  wire [4:0] fault;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:507" *)
  reg [7:0] fault_byte;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:263" *)
  reg fault_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:506" *)
  reg [1:0] fault_msg_idx = 2'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:512" *)
  reg [31:0] fault_nia = 32'd0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:513" *)
  reg [1:0] fault_nia_idx = 2'h0;
  (* src = "/home/runner/workspace/hardware/core.py:85" *)
  wire fault_valid;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:745" *)
  reg [31:0] fault_word;
  (* src = "/home/runner/workspace/hardware/core.py:97" *)
  reg [31:0] free_run_nia;
  (* src = "/home/runner/workspace/hardware/core.py:96" *)
  reg free_run_start;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:379" *)
  reg [7:0] fsm_byte_data;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:378" *)
  reg fsm_send_byte;
  (* src = "/home/runner/workspace/hardware/core.py:80" *)
  wire gc_start;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:497" *)
  reg [7:0] halt_byte;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:496" *)
  reg [2:0] halt_idx = 3'h0;
  (* src = "/home/runner/workspace/hardware/core.py:86" *)
  wire halt_valid;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:261" *)
  reg halted = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:401" *)
  reg heartbeat_blink = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:400" *)
  reg [24:0] heartbeat_ctr = 25'h0000000;
  (* src = "/home/runner/workspace/hardware/core.py:53" *)
  wire [31:0] imem_addr;
  (* src = "/home/runner/workspace/hardware/core.py:54" *)
  wire [31:0] imem_data;
  (* src = "/home/runner/workspace/hardware/core.py:55" *)
  wire imem_valid;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:163" *)
  wire is_mmio;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:215" *)
  wire is_mmio_read;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:192" *)
  wire is_mmio_write;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:511" *)
  reg [7:0] last_fault_code = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:48" *)
  output led0;
  wire led0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:48" *)
  output led1;
  wire led1;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:48" *)
  output led2;
  wire led2;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:48" *)
  output led3;
  wire led3;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:116" *)
  reg [13:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:138" *)
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  reg [2:0] mmio_led0 = 3'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  reg [2:0] mmio_led1 = 3'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  reg [2:0] mmio_led2 = 3'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  reg [2:0] mmio_led3 = 3'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  reg [2:0] mmio_led4 = 3'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:218" *)
  reg [31:0] mmio_rd_data;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:165" *)
  wire [3:0] mmio_reg_sel;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:173" *)
  reg [7:0] mmio_rx_data = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:175" *)
  reg mmio_rx_read;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:174" *)
  reg mmio_rx_valid = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:377" *)
  reg [7:0] mmio_uart_byte_reg = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:376" *)
  reg mmio_uart_pending = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:171" *)
  reg [7:0] mmio_uart_tx_data;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:170" *)
  reg mmio_uart_tx_wr;
  (* src = "/home/runner/workspace/hardware/core.py:99" *)
  wire [31:0] nia;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:333" *)
  wire nia_changed;
  (* src = "/home/runner/workspace/hardware/core.py:64" *)
  wire [31:0] ns_addr;
  (* src = "/home/runner/workspace/hardware/core.py:66" *)
  wire [95:0] ns_rd_data;
  (* src = "/home/runner/workspace/hardware/core.py:65" *)
  wire ns_rd_en;
  (* src = "/home/runner/workspace/hardware/core.py:67" *)
  wire [95:0] ns_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:68" *)
  wire ns_wr_en;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  reg [7:0] pl_ack0 = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  reg [7:0] pl_ack1 = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  reg [7:0] pl_ack2 = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  reg [7:0] pl_ack3 = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:284" *)
  reg [2:0] pl_ack_idx = 3'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:275" *)
  reg pl_active = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:276" *)
  reg [15:0] pl_addr = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:278" *)
  reg [15:0] pl_count = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:282" *)
  reg pl_crc_fail = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:281" *)
  reg [7:0] pl_crc_hi_buf = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:280" *)
  reg [15:0] pl_cur_addr = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:277" *)
  reg [15:0] pl_total_count = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:279" *)
  reg [31:0] pl_word = 32'd0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:273" *)
  reg [13:0] pl_wr_addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:274" *)
  reg [31:0] pl_wr_data;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:272" *)
  reg pl_wr_en;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:331" *)
  reg [31:0] prev_nia = 32'd0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:46" *)
  input push_button;
  wire push_button;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:304" *)
  reg [15:0] rb_addr = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:305" *)
  reg [15:0] rb_count = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:128" *)
  reg [15:0] rb_cur_addr = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:127" *)
  reg rb_rd_en;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:306" *)
  reg [31:0] rb_word = 32'd0;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:18" *)
  reg reset;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:19" *)
  wire rx;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:90" *)
  reg send;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:91" *)
  reg send_byte;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:523" *)
  reg [27:0] startup_ctr = 28'h0000000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:502" *)
  reg [7:0] step_byte;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:336" *)
  wire step_complete;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:516" *)
  reg [3:0] step_fault = 4'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:517" *)
  reg step_had_fault = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:501" *)
  reg [1:0] step_idx = 2'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:515" *)
  reg [31:0] step_nia = 32'd0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:262" *)
  reg stepping = 1'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:178" *)
  reg [31:0] timer_hi = 32'd0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:177" *)
  reg [31:0] timer_lo = 32'd0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:179" *)
  reg [31:0] tod_epoch = 32'd0;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:94" *)
  wire tx;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:19" *)
  input uart_rx;
  wire uart_rx;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:94" *)
  output uart_tx;
  wire uart_tx;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:21" *)
  wire valid;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:19" *)
  reg \valid$131 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:111" *)
  reg [31:0] dmem [16383:0];
  initial begin
    dmem[0] = 32'd64768;
    dmem[1] = 32'd63;
    dmem[2] = 32'd3738492655;
    dmem[3] = 32'd805306368;
    dmem[4] = 32'd256;
    dmem[5] = 32'd63;
    dmem[6] = 32'd3735740143;
    dmem[7] = 32'd805306368;
    dmem[8] = 32'd0;
    dmem[9] = 32'd0;
    dmem[10] = 32'd3735928559;
    dmem[11] = 32'd0;
    dmem[12] = 32'd0;
    dmem[13] = 32'd0;
    dmem[14] = 32'd3735928559;
    dmem[15] = 32'd0;
    dmem[16] = 32'd1020;
    dmem[17] = 32'd63;
    dmem[18] = 32'd3735789807;
    dmem[19] = 32'd1207959552;
    dmem[20] = 32'd1280;
    dmem[21] = 32'd63;
    dmem[22] = 32'd3735609071;
    dmem[23] = 32'd1207959552;
    dmem[24] = 32'd1536;
    dmem[25] = 32'd63;
    dmem[26] = 32'd3735641839;
    dmem[27] = 32'd1207959552;
    dmem[28] = 32'd1792;
    dmem[29] = 32'd63;
    dmem[30] = 32'd3735674607;
    dmem[31] = 32'd1207959552;
    dmem[32] = 32'd2048;
    dmem[33] = 32'd63;
    dmem[34] = 32'd3735969519;
    dmem[35] = 32'd1207959552;
    dmem[36] = 32'd2304;
    dmem[37] = 32'd63;
    dmem[38] = 32'd3736002287;
    dmem[39] = 32'd1207959552;
    dmem[40] = 32'd2560;
    dmem[41] = 32'd63;
    dmem[42] = 32'd3736035055;
    dmem[43] = 32'd1207959552;
    dmem[44] = 32'd1073741844;
    dmem[45] = 32'd2;
    dmem[46] = 32'd3735942351;
    dmem[47] = 32'd805306368;
    dmem[48] = 32'd1073741824;
    dmem[49] = 32'd4;
    dmem[50] = 32'd3735895759;
    dmem[51] = 32'd805306368;
    dmem[52] = 32'd1073741864;
    dmem[53] = 32'd0;
    dmem[54] = 32'd3735923407;
    dmem[55] = 32'd268435456;
    dmem[56] = 32'd1073741868;
    dmem[57] = 32'd4;
    dmem[58] = 32'd3735890127;
    dmem[59] = 32'd805306368;
    dmem[60] = 32'd3840;
    dmem[61] = 32'd63;
    dmem[62] = 32'd3735936751;
    dmem[63] = 32'd1207959552;
    dmem[64] = 32'd2044;
    dmem[65] = 32'd255;
    dmem[66] = 32'd3736183023;
    dmem[67] = 32'd1207959552;
    dmem[68] = 32'd4352;
    dmem[69] = 32'd63;
    dmem[70] = 32'd3735215855;
    dmem[71] = 32'd805306368;
    dmem[72] = 32'd4608;
    dmem[73] = 32'd63;
    dmem[74] = 32'd3735248623;
    dmem[75] = 32'd268435456;
    dmem[76] = 32'd4294967052;
    dmem[77] = 32'd0;
    dmem[78] = 32'd559036560;
    dmem[79] = 32'd671088640;
    dmem[80] = 32'd4294967053;
    dmem[81] = 32'd0;
    dmem[82] = 32'd559036432;
    dmem[83] = 32'd671088640;
    dmem[84] = 32'd4294967068;
    dmem[85] = 32'd0;
    dmem[86] = 32'd559034512;
    dmem[87] = 32'd671088640;
    dmem[88] = 32'd4294967069;
    dmem[89] = 32'd0;
    dmem[90] = 32'd0;
    dmem[91] = 32'd0;
    dmem[92] = 32'd0;
    dmem[93] = 32'd0;
    dmem[94] = 32'd0;
    dmem[95] = 32'd0;
    dmem[96] = 32'd0;
    dmem[97] = 32'd0;
    dmem[98] = 32'd0;
    dmem[99] = 32'd0;
    dmem[100] = 32'd0;
    dmem[101] = 32'd0;
    dmem[102] = 32'd0;
    dmem[103] = 32'd0;
    dmem[104] = 32'd0;
    dmem[105] = 32'd0;
    dmem[106] = 32'd0;
    dmem[107] = 32'd0;
    dmem[108] = 32'd0;
    dmem[109] = 32'd0;
    dmem[110] = 32'd0;
    dmem[111] = 32'd0;
    dmem[112] = 32'd0;
    dmem[113] = 32'd0;
    dmem[114] = 32'd0;
    dmem[115] = 32'd0;
    dmem[116] = 32'd0;
    dmem[117] = 32'd0;
    dmem[118] = 32'd0;
    dmem[119] = 32'd0;
    dmem[120] = 32'd0;
    dmem[121] = 32'd0;
    dmem[122] = 32'd0;
    dmem[123] = 32'd0;
    dmem[124] = 32'd0;
    dmem[125] = 32'd1241513988;
    dmem[126] = 32'd0;
    dmem[127] = 32'd0;
    dmem[128] = 32'd0;
    dmem[129] = 32'd0;
    dmem[130] = 32'd0;
    dmem[131] = 32'd0;
    dmem[132] = 32'd0;
    dmem[133] = 32'd0;
    dmem[134] = 32'd0;
    dmem[135] = 32'd0;
    dmem[136] = 32'd0;
    dmem[137] = 32'd0;
    dmem[138] = 32'd0;
    dmem[139] = 32'd0;
    dmem[140] = 32'd0;
    dmem[141] = 32'd0;
    dmem[142] = 32'd0;
    dmem[143] = 32'd0;
    dmem[144] = 32'd0;
    dmem[145] = 32'd0;
    dmem[146] = 32'd0;
    dmem[147] = 32'd0;
    dmem[148] = 32'd0;
    dmem[149] = 32'd0;
    dmem[150] = 32'd0;
    dmem[151] = 32'd0;
    dmem[152] = 32'd0;
    dmem[153] = 32'd0;
    dmem[154] = 32'd0;
    dmem[155] = 32'd0;
    dmem[156] = 32'd0;
    dmem[157] = 32'd0;
    dmem[158] = 32'd0;
    dmem[159] = 32'd0;
    dmem[160] = 32'd0;
    dmem[161] = 32'd0;
    dmem[162] = 32'd0;
    dmem[163] = 32'd0;
    dmem[164] = 32'd0;
    dmem[165] = 32'd0;
    dmem[166] = 32'd0;
    dmem[167] = 32'd0;
    dmem[168] = 32'd0;
    dmem[169] = 32'd0;
    dmem[170] = 32'd0;
    dmem[171] = 32'd0;
    dmem[172] = 32'd0;
    dmem[173] = 32'd0;
    dmem[174] = 32'd0;
    dmem[175] = 32'd0;
    dmem[176] = 32'd0;
    dmem[177] = 32'd0;
    dmem[178] = 32'd0;
    dmem[179] = 32'd0;
    dmem[180] = 32'd0;
    dmem[181] = 32'd0;
    dmem[182] = 32'd0;
    dmem[183] = 32'd0;
    dmem[184] = 32'd0;
    dmem[185] = 32'd0;
    dmem[186] = 32'd0;
    dmem[187] = 32'd0;
    dmem[188] = 32'd0;
    dmem[189] = 32'd0;
    dmem[190] = 32'd0;
    dmem[191] = 32'd0;
    dmem[192] = 32'd0;
    dmem[193] = 32'd0;
    dmem[194] = 32'd0;
    dmem[195] = 32'd0;
    dmem[196] = 32'd0;
    dmem[197] = 32'd0;
    dmem[198] = 32'd0;
    dmem[199] = 32'd0;
    dmem[200] = 32'd0;
    dmem[201] = 32'd0;
    dmem[202] = 32'd0;
    dmem[203] = 32'd0;
    dmem[204] = 32'd0;
    dmem[205] = 32'd0;
    dmem[206] = 32'd0;
    dmem[207] = 32'd0;
    dmem[208] = 32'd0;
    dmem[209] = 32'd0;
    dmem[210] = 32'd0;
    dmem[211] = 32'd0;
    dmem[212] = 32'd0;
    dmem[213] = 32'd0;
    dmem[214] = 32'd0;
    dmem[215] = 32'd0;
    dmem[216] = 32'd0;
    dmem[217] = 32'd0;
    dmem[218] = 32'd0;
    dmem[219] = 32'd0;
    dmem[220] = 32'd0;
    dmem[221] = 32'd0;
    dmem[222] = 32'd0;
    dmem[223] = 32'd0;
    dmem[224] = 32'd0;
    dmem[225] = 32'd0;
    dmem[226] = 32'd0;
    dmem[227] = 32'd0;
    dmem[228] = 32'd0;
    dmem[229] = 32'd0;
    dmem[230] = 32'd0;
    dmem[231] = 32'd0;
    dmem[232] = 32'd0;
    dmem[233] = 32'd0;
    dmem[234] = 32'd0;
    dmem[235] = 32'd0;
    dmem[236] = 32'd0;
    dmem[237] = 32'd0;
    dmem[238] = 32'd0;
    dmem[239] = 32'd0;
    dmem[240] = 32'd0;
    dmem[241] = 32'd0;
    dmem[242] = 32'd0;
    dmem[243] = 32'd0;
    dmem[244] = 32'd0;
    dmem[245] = 32'd0;
    dmem[246] = 32'd0;
    dmem[247] = 32'd0;
    dmem[248] = 32'd0;
    dmem[249] = 32'd0;
    dmem[250] = 32'd0;
    dmem[251] = 32'd0;
    dmem[252] = 32'd0;
    dmem[253] = 32'd0;
    dmem[254] = 32'd0;
    dmem[255] = 32'd4160766976;
    dmem[256] = 32'd1375731715;
    dmem[257] = 32'd1107296260;
    dmem[258] = 32'd0;
    dmem[259] = 32'd1241513986;
    dmem[260] = 32'd0;
    dmem[261] = 32'd1241513989;
    dmem[262] = 32'd1241513990;
    dmem[263] = 32'd1241513991;
    dmem[264] = 32'd2986344460;
    dmem[265] = 32'd2986344459;
    dmem[266] = 32'd2449473549;
    dmem[267] = 32'd2986344462;
    dmem[268] = 32'd1241514000;
    dmem[269] = 32'd301989906;
    dmem[270] = 32'd0;
    dmem[271] = 32'd0;
    dmem[272] = 32'd0;
    dmem[273] = 32'd0;
    dmem[274] = 32'd0;
    dmem[275] = 32'd0;
    dmem[276] = 32'd0;
    dmem[277] = 32'd0;
    dmem[278] = 32'd0;
    dmem[279] = 32'd0;
    dmem[280] = 32'd0;
    dmem[281] = 32'd0;
    dmem[282] = 32'd0;
    dmem[283] = 32'd0;
    dmem[284] = 32'd0;
    dmem[285] = 32'd0;
    dmem[286] = 32'd0;
    dmem[287] = 32'd0;
    dmem[288] = 32'd0;
    dmem[289] = 32'd0;
    dmem[290] = 32'd0;
    dmem[291] = 32'd0;
    dmem[292] = 32'd0;
    dmem[293] = 32'd0;
    dmem[294] = 32'd0;
    dmem[295] = 32'd0;
    dmem[296] = 32'd0;
    dmem[297] = 32'd0;
    dmem[298] = 32'd0;
    dmem[299] = 32'd0;
    dmem[300] = 32'd0;
    dmem[301] = 32'd0;
    dmem[302] = 32'd0;
    dmem[303] = 32'd0;
    dmem[304] = 32'd0;
    dmem[305] = 32'd0;
    dmem[306] = 32'd0;
    dmem[307] = 32'd0;
    dmem[308] = 32'd0;
    dmem[309] = 32'd0;
    dmem[310] = 32'd0;
    dmem[311] = 32'd0;
    dmem[312] = 32'd0;
    dmem[313] = 32'd0;
    dmem[314] = 32'd0;
    dmem[315] = 32'd0;
    dmem[316] = 32'd0;
    dmem[317] = 32'd0;
    dmem[318] = 32'd0;
    dmem[319] = 32'd0;
    dmem[320] = 32'd0;
    dmem[321] = 32'd0;
    dmem[322] = 32'd0;
    dmem[323] = 32'd0;
    dmem[324] = 32'd0;
    dmem[325] = 32'd0;
    dmem[326] = 32'd0;
    dmem[327] = 32'd0;
    dmem[328] = 32'd0;
    dmem[329] = 32'd0;
    dmem[330] = 32'd0;
    dmem[331] = 32'd0;
    dmem[332] = 32'd0;
    dmem[333] = 32'd0;
    dmem[334] = 32'd0;
    dmem[335] = 32'd0;
    dmem[336] = 32'd0;
    dmem[337] = 32'd0;
    dmem[338] = 32'd0;
    dmem[339] = 32'd0;
    dmem[340] = 32'd0;
    dmem[341] = 32'd0;
    dmem[342] = 32'd0;
    dmem[343] = 32'd0;
    dmem[344] = 32'd0;
    dmem[345] = 32'd0;
    dmem[346] = 32'd0;
    dmem[347] = 32'd0;
    dmem[348] = 32'd0;
    dmem[349] = 32'd0;
    dmem[350] = 32'd0;
    dmem[351] = 32'd0;
    dmem[352] = 32'd0;
    dmem[353] = 32'd0;
    dmem[354] = 32'd0;
    dmem[355] = 32'd0;
    dmem[356] = 32'd0;
    dmem[357] = 32'd0;
    dmem[358] = 32'd0;
    dmem[359] = 32'd0;
    dmem[360] = 32'd0;
    dmem[361] = 32'd0;
    dmem[362] = 32'd0;
    dmem[363] = 32'd0;
    dmem[364] = 32'd0;
    dmem[365] = 32'd0;
    dmem[366] = 32'd0;
    dmem[367] = 32'd0;
    dmem[368] = 32'd0;
    dmem[369] = 32'd0;
    dmem[370] = 32'd0;
    dmem[371] = 32'd0;
    dmem[372] = 32'd0;
    dmem[373] = 32'd0;
    dmem[374] = 32'd0;
    dmem[375] = 32'd0;
    dmem[376] = 32'd0;
    dmem[377] = 32'd0;
    dmem[378] = 32'd0;
    dmem[379] = 32'd0;
    dmem[380] = 32'd0;
    dmem[381] = 32'd0;
    dmem[382] = 32'd0;
    dmem[383] = 32'd0;
    dmem[384] = 32'd0;
    dmem[385] = 32'd0;
    dmem[386] = 32'd0;
    dmem[387] = 32'd0;
    dmem[388] = 32'd0;
    dmem[389] = 32'd0;
    dmem[390] = 32'd0;
    dmem[391] = 32'd0;
    dmem[392] = 32'd0;
    dmem[393] = 32'd0;
    dmem[394] = 32'd0;
    dmem[395] = 32'd0;
    dmem[396] = 32'd0;
    dmem[397] = 32'd0;
    dmem[398] = 32'd0;
    dmem[399] = 32'd0;
    dmem[400] = 32'd0;
    dmem[401] = 32'd0;
    dmem[402] = 32'd0;
    dmem[403] = 32'd0;
    dmem[404] = 32'd0;
    dmem[405] = 32'd0;
    dmem[406] = 32'd0;
    dmem[407] = 32'd0;
    dmem[408] = 32'd0;
    dmem[409] = 32'd0;
    dmem[410] = 32'd0;
    dmem[411] = 32'd0;
    dmem[412] = 32'd0;
    dmem[413] = 32'd0;
    dmem[414] = 32'd0;
    dmem[415] = 32'd0;
    dmem[416] = 32'd0;
    dmem[417] = 32'd0;
    dmem[418] = 32'd0;
    dmem[419] = 32'd0;
    dmem[420] = 32'd0;
    dmem[421] = 32'd0;
    dmem[422] = 32'd0;
    dmem[423] = 32'd0;
    dmem[424] = 32'd0;
    dmem[425] = 32'd0;
    dmem[426] = 32'd0;
    dmem[427] = 32'd0;
    dmem[428] = 32'd0;
    dmem[429] = 32'd0;
    dmem[430] = 32'd0;
    dmem[431] = 32'd0;
    dmem[432] = 32'd0;
    dmem[433] = 32'd0;
    dmem[434] = 32'd0;
    dmem[435] = 32'd0;
    dmem[436] = 32'd0;
    dmem[437] = 32'd0;
    dmem[438] = 32'd0;
    dmem[439] = 32'd0;
    dmem[440] = 32'd0;
    dmem[441] = 32'd0;
    dmem[442] = 32'd0;
    dmem[443] = 32'd0;
    dmem[444] = 32'd0;
    dmem[445] = 32'd0;
    dmem[446] = 32'd0;
    dmem[447] = 32'd0;
    dmem[448] = 32'd0;
    dmem[449] = 32'd0;
    dmem[450] = 32'd0;
    dmem[451] = 32'd0;
    dmem[452] = 32'd0;
    dmem[453] = 32'd0;
    dmem[454] = 32'd0;
    dmem[455] = 32'd0;
    dmem[456] = 32'd0;
    dmem[457] = 32'd0;
    dmem[458] = 32'd0;
    dmem[459] = 32'd0;
    dmem[460] = 32'd0;
    dmem[461] = 32'd0;
    dmem[462] = 32'd0;
    dmem[463] = 32'd0;
    dmem[464] = 32'd0;
    dmem[465] = 32'd0;
    dmem[466] = 32'd0;
    dmem[467] = 32'd0;
    dmem[468] = 32'd0;
    dmem[469] = 32'd0;
    dmem[470] = 32'd0;
    dmem[471] = 32'd0;
    dmem[472] = 32'd0;
    dmem[473] = 32'd0;
    dmem[474] = 32'd0;
    dmem[475] = 32'd0;
    dmem[476] = 32'd0;
    dmem[477] = 32'd0;
    dmem[478] = 32'd0;
    dmem[479] = 32'd0;
    dmem[480] = 32'd0;
    dmem[481] = 32'd0;
    dmem[482] = 32'd0;
    dmem[483] = 32'd0;
    dmem[484] = 32'd0;
    dmem[485] = 32'd0;
    dmem[486] = 32'd0;
    dmem[487] = 32'd0;
    dmem[488] = 32'd0;
    dmem[489] = 32'd0;
    dmem[490] = 32'd0;
    dmem[491] = 32'd0;
    dmem[492] = 32'd0;
    dmem[493] = 32'd0;
    dmem[494] = 32'd0;
    dmem[495] = 32'd0;
    dmem[496] = 32'd0;
    dmem[497] = 32'd0;
    dmem[498] = 32'd0;
    dmem[499] = 32'd0;
    dmem[500] = 32'd0;
    dmem[501] = 32'd0;
    dmem[502] = 32'd0;
    dmem[503] = 32'd0;
    dmem[504] = 32'd0;
    dmem[505] = 32'd0;
    dmem[506] = 32'd0;
    dmem[507] = 32'd0;
    dmem[508] = 32'd0;
    dmem[509] = 32'd0;
    dmem[510] = 32'd0;
    dmem[511] = 32'd4177699840;
    dmem[512] = 32'd0;
    dmem[513] = 32'd0;
    dmem[514] = 32'd0;
    dmem[515] = 32'd0;
    dmem[516] = 32'd0;
    dmem[517] = 32'd0;
    dmem[518] = 32'd0;
    dmem[519] = 32'd0;
    dmem[520] = 32'd0;
    dmem[521] = 32'd0;
    dmem[522] = 32'd0;
    dmem[523] = 32'd0;
    dmem[524] = 32'd0;
    dmem[525] = 32'd0;
    dmem[526] = 32'd0;
    dmem[527] = 32'd0;
    dmem[528] = 32'd0;
    dmem[529] = 32'd0;
    dmem[530] = 32'd0;
    dmem[531] = 32'd0;
    dmem[532] = 32'd0;
    dmem[533] = 32'd0;
    dmem[534] = 32'd0;
    dmem[535] = 32'd0;
    dmem[536] = 32'd0;
    dmem[537] = 32'd0;
    dmem[538] = 32'd0;
    dmem[539] = 32'd0;
    dmem[540] = 32'd0;
    dmem[541] = 32'd0;
    dmem[542] = 32'd0;
    dmem[543] = 32'd0;
    dmem[544] = 32'd0;
    dmem[545] = 32'd0;
    dmem[546] = 32'd0;
    dmem[547] = 32'd0;
    dmem[548] = 32'd0;
    dmem[549] = 32'd0;
    dmem[550] = 32'd0;
    dmem[551] = 32'd0;
    dmem[552] = 32'd0;
    dmem[553] = 32'd0;
    dmem[554] = 32'd0;
    dmem[555] = 32'd0;
    dmem[556] = 32'd0;
    dmem[557] = 32'd0;
    dmem[558] = 32'd0;
    dmem[559] = 32'd0;
    dmem[560] = 32'd0;
    dmem[561] = 32'd0;
    dmem[562] = 32'd0;
    dmem[563] = 32'd0;
    dmem[564] = 32'd0;
    dmem[565] = 32'd0;
    dmem[566] = 32'd0;
    dmem[567] = 32'd0;
    dmem[568] = 32'd0;
    dmem[569] = 32'd0;
    dmem[570] = 32'd0;
    dmem[571] = 32'd0;
    dmem[572] = 32'd0;
    dmem[573] = 32'd0;
    dmem[574] = 32'd0;
    dmem[575] = 32'd0;
    dmem[576] = 32'd0;
    dmem[577] = 32'd0;
    dmem[578] = 32'd0;
    dmem[579] = 32'd0;
    dmem[580] = 32'd0;
    dmem[581] = 32'd0;
    dmem[582] = 32'd0;
    dmem[583] = 32'd0;
    dmem[584] = 32'd0;
    dmem[585] = 32'd0;
    dmem[586] = 32'd0;
    dmem[587] = 32'd0;
    dmem[588] = 32'd0;
    dmem[589] = 32'd0;
    dmem[590] = 32'd0;
    dmem[591] = 32'd0;
    dmem[592] = 32'd0;
    dmem[593] = 32'd0;
    dmem[594] = 32'd0;
    dmem[595] = 32'd0;
    dmem[596] = 32'd0;
    dmem[597] = 32'd0;
    dmem[598] = 32'd0;
    dmem[599] = 32'd0;
    dmem[600] = 32'd0;
    dmem[601] = 32'd0;
    dmem[602] = 32'd0;
    dmem[603] = 32'd0;
    dmem[604] = 32'd0;
    dmem[605] = 32'd0;
    dmem[606] = 32'd0;
    dmem[607] = 32'd0;
    dmem[608] = 32'd0;
    dmem[609] = 32'd0;
    dmem[610] = 32'd0;
    dmem[611] = 32'd0;
    dmem[612] = 32'd0;
    dmem[613] = 32'd0;
    dmem[614] = 32'd0;
    dmem[615] = 32'd0;
    dmem[616] = 32'd0;
    dmem[617] = 32'd0;
    dmem[618] = 32'd0;
    dmem[619] = 32'd0;
    dmem[620] = 32'd0;
    dmem[621] = 32'd0;
    dmem[622] = 32'd0;
    dmem[623] = 32'd0;
    dmem[624] = 32'd0;
    dmem[625] = 32'd0;
    dmem[626] = 32'd0;
    dmem[627] = 32'd0;
    dmem[628] = 32'd0;
    dmem[629] = 32'd0;
    dmem[630] = 32'd0;
    dmem[631] = 32'd0;
    dmem[632] = 32'd0;
    dmem[633] = 32'd0;
    dmem[634] = 32'd0;
    dmem[635] = 32'd0;
    dmem[636] = 32'd0;
    dmem[637] = 32'd0;
    dmem[638] = 32'd0;
    dmem[639] = 32'd0;
    dmem[640] = 32'd0;
    dmem[641] = 32'd0;
    dmem[642] = 32'd0;
    dmem[643] = 32'd0;
    dmem[644] = 32'd0;
    dmem[645] = 32'd0;
    dmem[646] = 32'd0;
    dmem[647] = 32'd0;
    dmem[648] = 32'd0;
    dmem[649] = 32'd0;
    dmem[650] = 32'd0;
    dmem[651] = 32'd0;
    dmem[652] = 32'd0;
    dmem[653] = 32'd0;
    dmem[654] = 32'd0;
    dmem[655] = 32'd0;
    dmem[656] = 32'd0;
    dmem[657] = 32'd0;
    dmem[658] = 32'd0;
    dmem[659] = 32'd0;
    dmem[660] = 32'd0;
    dmem[661] = 32'd0;
    dmem[662] = 32'd0;
    dmem[663] = 32'd0;
    dmem[664] = 32'd0;
    dmem[665] = 32'd0;
    dmem[666] = 32'd0;
    dmem[667] = 32'd0;
    dmem[668] = 32'd0;
    dmem[669] = 32'd0;
    dmem[670] = 32'd0;
    dmem[671] = 32'd0;
    dmem[672] = 32'd0;
    dmem[673] = 32'd0;
    dmem[674] = 32'd0;
    dmem[675] = 32'd0;
    dmem[676] = 32'd0;
    dmem[677] = 32'd0;
    dmem[678] = 32'd0;
    dmem[679] = 32'd0;
    dmem[680] = 32'd0;
    dmem[681] = 32'd0;
    dmem[682] = 32'd0;
    dmem[683] = 32'd0;
    dmem[684] = 32'd0;
    dmem[685] = 32'd0;
    dmem[686] = 32'd0;
    dmem[687] = 32'd0;
    dmem[688] = 32'd0;
    dmem[689] = 32'd0;
    dmem[690] = 32'd0;
    dmem[691] = 32'd0;
    dmem[692] = 32'd0;
    dmem[693] = 32'd0;
    dmem[694] = 32'd0;
    dmem[695] = 32'd0;
    dmem[696] = 32'd0;
    dmem[697] = 32'd0;
    dmem[698] = 32'd0;
    dmem[699] = 32'd0;
    dmem[700] = 32'd0;
    dmem[701] = 32'd0;
    dmem[702] = 32'd0;
    dmem[703] = 32'd0;
    dmem[704] = 32'd0;
    dmem[705] = 32'd0;
    dmem[706] = 32'd0;
    dmem[707] = 32'd0;
    dmem[708] = 32'd0;
    dmem[709] = 32'd0;
    dmem[710] = 32'd0;
    dmem[711] = 32'd0;
    dmem[712] = 32'd0;
    dmem[713] = 32'd0;
    dmem[714] = 32'd0;
    dmem[715] = 32'd0;
    dmem[716] = 32'd0;
    dmem[717] = 32'd0;
    dmem[718] = 32'd0;
    dmem[719] = 32'd0;
    dmem[720] = 32'd0;
    dmem[721] = 32'd0;
    dmem[722] = 32'd0;
    dmem[723] = 32'd0;
    dmem[724] = 32'd0;
    dmem[725] = 32'd0;
    dmem[726] = 32'd0;
    dmem[727] = 32'd0;
    dmem[728] = 32'd0;
    dmem[729] = 32'd0;
    dmem[730] = 32'd0;
    dmem[731] = 32'd0;
    dmem[732] = 32'd0;
    dmem[733] = 32'd0;
    dmem[734] = 32'd0;
    dmem[735] = 32'd0;
    dmem[736] = 32'd0;
    dmem[737] = 32'd0;
    dmem[738] = 32'd0;
    dmem[739] = 32'd0;
    dmem[740] = 32'd0;
    dmem[741] = 32'd0;
    dmem[742] = 32'd0;
    dmem[743] = 32'd0;
    dmem[744] = 32'd0;
    dmem[745] = 32'd0;
    dmem[746] = 32'd0;
    dmem[747] = 32'd0;
    dmem[748] = 32'd0;
    dmem[749] = 32'd0;
    dmem[750] = 32'd0;
    dmem[751] = 32'd0;
    dmem[752] = 32'd0;
    dmem[753] = 32'd0;
    dmem[754] = 32'd0;
    dmem[755] = 32'd0;
    dmem[756] = 32'd0;
    dmem[757] = 32'd0;
    dmem[758] = 32'd0;
    dmem[759] = 32'd0;
    dmem[760] = 32'd0;
    dmem[761] = 32'd0;
    dmem[762] = 32'd0;
    dmem[763] = 32'd0;
    dmem[764] = 32'd0;
    dmem[765] = 32'd0;
    dmem[766] = 32'd0;
    dmem[767] = 32'd0;
    dmem[768] = 32'd0;
    dmem[769] = 32'd0;
    dmem[770] = 32'd0;
    dmem[771] = 32'd0;
    dmem[772] = 32'd0;
    dmem[773] = 32'd0;
    dmem[774] = 32'd0;
    dmem[775] = 32'd0;
    dmem[776] = 32'd0;
    dmem[777] = 32'd0;
    dmem[778] = 32'd0;
    dmem[779] = 32'd0;
    dmem[780] = 32'd0;
    dmem[781] = 32'd0;
    dmem[782] = 32'd0;
    dmem[783] = 32'd0;
    dmem[784] = 32'd0;
    dmem[785] = 32'd0;
    dmem[786] = 32'd0;
    dmem[787] = 32'd0;
    dmem[788] = 32'd0;
    dmem[789] = 32'd0;
    dmem[790] = 32'd0;
    dmem[791] = 32'd0;
    dmem[792] = 32'd0;
    dmem[793] = 32'd0;
    dmem[794] = 32'd0;
    dmem[795] = 32'd0;
    dmem[796] = 32'd0;
    dmem[797] = 32'd0;
    dmem[798] = 32'd0;
    dmem[799] = 32'd0;
    dmem[800] = 32'd0;
    dmem[801] = 32'd0;
    dmem[802] = 32'd0;
    dmem[803] = 32'd0;
    dmem[804] = 32'd0;
    dmem[805] = 32'd0;
    dmem[806] = 32'd0;
    dmem[807] = 32'd0;
    dmem[808] = 32'd0;
    dmem[809] = 32'd0;
    dmem[810] = 32'd0;
    dmem[811] = 32'd0;
    dmem[812] = 32'd0;
    dmem[813] = 32'd0;
    dmem[814] = 32'd0;
    dmem[815] = 32'd0;
    dmem[816] = 32'd0;
    dmem[817] = 32'd0;
    dmem[818] = 32'd0;
    dmem[819] = 32'd0;
    dmem[820] = 32'd0;
    dmem[821] = 32'd0;
    dmem[822] = 32'd0;
    dmem[823] = 32'd0;
    dmem[824] = 32'd0;
    dmem[825] = 32'd0;
    dmem[826] = 32'd0;
    dmem[827] = 32'd0;
    dmem[828] = 32'd0;
    dmem[829] = 32'd0;
    dmem[830] = 32'd0;
    dmem[831] = 32'd0;
    dmem[832] = 32'd0;
    dmem[833] = 32'd0;
    dmem[834] = 32'd0;
    dmem[835] = 32'd0;
    dmem[836] = 32'd0;
    dmem[837] = 32'd0;
    dmem[838] = 32'd0;
    dmem[839] = 32'd0;
    dmem[840] = 32'd0;
    dmem[841] = 32'd0;
    dmem[842] = 32'd0;
    dmem[843] = 32'd0;
    dmem[844] = 32'd0;
    dmem[845] = 32'd0;
    dmem[846] = 32'd0;
    dmem[847] = 32'd0;
    dmem[848] = 32'd0;
    dmem[849] = 32'd0;
    dmem[850] = 32'd0;
    dmem[851] = 32'd0;
    dmem[852] = 32'd0;
    dmem[853] = 32'd0;
    dmem[854] = 32'd0;
    dmem[855] = 32'd0;
    dmem[856] = 32'd0;
    dmem[857] = 32'd0;
    dmem[858] = 32'd0;
    dmem[859] = 32'd0;
    dmem[860] = 32'd0;
    dmem[861] = 32'd0;
    dmem[862] = 32'd0;
    dmem[863] = 32'd0;
    dmem[864] = 32'd0;
    dmem[865] = 32'd0;
    dmem[866] = 32'd0;
    dmem[867] = 32'd0;
    dmem[868] = 32'd0;
    dmem[869] = 32'd0;
    dmem[870] = 32'd0;
    dmem[871] = 32'd0;
    dmem[872] = 32'd0;
    dmem[873] = 32'd0;
    dmem[874] = 32'd0;
    dmem[875] = 32'd0;
    dmem[876] = 32'd0;
    dmem[877] = 32'd0;
    dmem[878] = 32'd0;
    dmem[879] = 32'd0;
    dmem[880] = 32'd0;
    dmem[881] = 32'd0;
    dmem[882] = 32'd0;
    dmem[883] = 32'd0;
    dmem[884] = 32'd0;
    dmem[885] = 32'd0;
    dmem[886] = 32'd0;
    dmem[887] = 32'd0;
    dmem[888] = 32'd0;
    dmem[889] = 32'd0;
    dmem[890] = 32'd0;
    dmem[891] = 32'd0;
    dmem[892] = 32'd0;
    dmem[893] = 32'd0;
    dmem[894] = 32'd0;
    dmem[895] = 32'd0;
    dmem[896] = 32'd0;
    dmem[897] = 32'd0;
    dmem[898] = 32'd0;
    dmem[899] = 32'd0;
    dmem[900] = 32'd0;
    dmem[901] = 32'd0;
    dmem[902] = 32'd0;
    dmem[903] = 32'd0;
    dmem[904] = 32'd0;
    dmem[905] = 32'd0;
    dmem[906] = 32'd0;
    dmem[907] = 32'd0;
    dmem[908] = 32'd0;
    dmem[909] = 32'd0;
    dmem[910] = 32'd0;
    dmem[911] = 32'd0;
    dmem[912] = 32'd0;
    dmem[913] = 32'd0;
    dmem[914] = 32'd0;
    dmem[915] = 32'd0;
    dmem[916] = 32'd0;
    dmem[917] = 32'd0;
    dmem[918] = 32'd0;
    dmem[919] = 32'd0;
    dmem[920] = 32'd0;
    dmem[921] = 32'd0;
    dmem[922] = 32'd0;
    dmem[923] = 32'd0;
    dmem[924] = 32'd0;
    dmem[925] = 32'd0;
    dmem[926] = 32'd0;
    dmem[927] = 32'd0;
    dmem[928] = 32'd0;
    dmem[929] = 32'd0;
    dmem[930] = 32'd0;
    dmem[931] = 32'd0;
    dmem[932] = 32'd0;
    dmem[933] = 32'd0;
    dmem[934] = 32'd0;
    dmem[935] = 32'd0;
    dmem[936] = 32'd0;
    dmem[937] = 32'd0;
    dmem[938] = 32'd0;
    dmem[939] = 32'd0;
    dmem[940] = 32'd0;
    dmem[941] = 32'd0;
    dmem[942] = 32'd0;
    dmem[943] = 32'd0;
    dmem[944] = 32'd0;
    dmem[945] = 32'd0;
    dmem[946] = 32'd0;
    dmem[947] = 32'd0;
    dmem[948] = 32'd0;
    dmem[949] = 32'd0;
    dmem[950] = 32'd0;
    dmem[951] = 32'd0;
    dmem[952] = 32'd0;
    dmem[953] = 32'd0;
    dmem[954] = 32'd0;
    dmem[955] = 32'd0;
    dmem[956] = 32'd0;
    dmem[957] = 32'd0;
    dmem[958] = 32'd0;
    dmem[959] = 32'd0;
    dmem[960] = 32'd0;
    dmem[961] = 32'd0;
    dmem[962] = 32'd0;
    dmem[963] = 32'd0;
    dmem[964] = 32'd0;
    dmem[965] = 32'd0;
    dmem[966] = 32'd0;
    dmem[967] = 32'd0;
    dmem[968] = 32'd0;
    dmem[969] = 32'd0;
    dmem[970] = 32'd0;
    dmem[971] = 32'd0;
    dmem[972] = 32'd0;
    dmem[973] = 32'd0;
    dmem[974] = 32'd0;
    dmem[975] = 32'd0;
    dmem[976] = 32'd0;
    dmem[977] = 32'd0;
    dmem[978] = 32'd0;
    dmem[979] = 32'd0;
    dmem[980] = 32'd0;
    dmem[981] = 32'd0;
    dmem[982] = 32'd0;
    dmem[983] = 32'd0;
    dmem[984] = 32'd0;
    dmem[985] = 32'd0;
    dmem[986] = 32'd0;
    dmem[987] = 32'd0;
    dmem[988] = 32'd0;
    dmem[989] = 32'd0;
    dmem[990] = 32'd0;
    dmem[991] = 32'd0;
    dmem[992] = 32'd0;
    dmem[993] = 32'd0;
    dmem[994] = 32'd0;
    dmem[995] = 32'd0;
    dmem[996] = 32'd0;
    dmem[997] = 32'd0;
    dmem[998] = 32'd0;
    dmem[999] = 32'd0;
    dmem[1000] = 32'd0;
    dmem[1001] = 32'd0;
    dmem[1002] = 32'd0;
    dmem[1003] = 32'd0;
    dmem[1004] = 32'd0;
    dmem[1005] = 32'd0;
    dmem[1006] = 32'd0;
    dmem[1007] = 32'd0;
    dmem[1008] = 32'd0;
    dmem[1009] = 32'd0;
    dmem[1010] = 32'd0;
    dmem[1011] = 32'd0;
    dmem[1012] = 32'd0;
    dmem[1013] = 32'd0;
    dmem[1014] = 32'd0;
    dmem[1015] = 32'd0;
    dmem[1016] = 32'd0;
    dmem[1017] = 32'd0;
    dmem[1018] = 32'd0;
    dmem[1019] = 32'd0;
    dmem[1020] = 32'd0;
    dmem[1021] = 32'd0;
    dmem[1022] = 32'd0;
    dmem[1023] = 32'd0;
    dmem[1024] = 32'd0;
    dmem[1025] = 32'd0;
    dmem[1026] = 32'd0;
    dmem[1027] = 32'd0;
    dmem[1028] = 32'd0;
    dmem[1029] = 32'd0;
    dmem[1030] = 32'd0;
    dmem[1031] = 32'd0;
    dmem[1032] = 32'd0;
    dmem[1033] = 32'd0;
    dmem[1034] = 32'd0;
    dmem[1035] = 32'd0;
    dmem[1036] = 32'd0;
    dmem[1037] = 32'd0;
    dmem[1038] = 32'd0;
    dmem[1039] = 32'd0;
    dmem[1040] = 32'd0;
    dmem[1041] = 32'd0;
    dmem[1042] = 32'd0;
    dmem[1043] = 32'd0;
    dmem[1044] = 32'd0;
    dmem[1045] = 32'd0;
    dmem[1046] = 32'd0;
    dmem[1047] = 32'd0;
    dmem[1048] = 32'd0;
    dmem[1049] = 32'd0;
    dmem[1050] = 32'd0;
    dmem[1051] = 32'd0;
    dmem[1052] = 32'd0;
    dmem[1053] = 32'd0;
    dmem[1054] = 32'd0;
    dmem[1055] = 32'd0;
    dmem[1056] = 32'd0;
    dmem[1057] = 32'd0;
    dmem[1058] = 32'd0;
    dmem[1059] = 32'd0;
    dmem[1060] = 32'd0;
    dmem[1061] = 32'd0;
    dmem[1062] = 32'd0;
    dmem[1063] = 32'd0;
    dmem[1064] = 32'd0;
    dmem[1065] = 32'd0;
    dmem[1066] = 32'd0;
    dmem[1067] = 32'd0;
    dmem[1068] = 32'd0;
    dmem[1069] = 32'd0;
    dmem[1070] = 32'd0;
    dmem[1071] = 32'd0;
    dmem[1072] = 32'd0;
    dmem[1073] = 32'd0;
    dmem[1074] = 32'd0;
    dmem[1075] = 32'd0;
    dmem[1076] = 32'd0;
    dmem[1077] = 32'd0;
    dmem[1078] = 32'd0;
    dmem[1079] = 32'd0;
    dmem[1080] = 32'd0;
    dmem[1081] = 32'd0;
    dmem[1082] = 32'd0;
    dmem[1083] = 32'd0;
    dmem[1084] = 32'd0;
    dmem[1085] = 32'd0;
    dmem[1086] = 32'd0;
    dmem[1087] = 32'd0;
    dmem[1088] = 32'd0;
    dmem[1089] = 32'd0;
    dmem[1090] = 32'd0;
    dmem[1091] = 32'd0;
    dmem[1092] = 32'd0;
    dmem[1093] = 32'd0;
    dmem[1094] = 32'd0;
    dmem[1095] = 32'd0;
    dmem[1096] = 32'd0;
    dmem[1097] = 32'd0;
    dmem[1098] = 32'd0;
    dmem[1099] = 32'd0;
    dmem[1100] = 32'd0;
    dmem[1101] = 32'd0;
    dmem[1102] = 32'd0;
    dmem[1103] = 32'd0;
    dmem[1104] = 32'd0;
    dmem[1105] = 32'd0;
    dmem[1106] = 32'd0;
    dmem[1107] = 32'd0;
    dmem[1108] = 32'd0;
    dmem[1109] = 32'd0;
    dmem[1110] = 32'd0;
    dmem[1111] = 32'd0;
    dmem[1112] = 32'd0;
    dmem[1113] = 32'd0;
    dmem[1114] = 32'd0;
    dmem[1115] = 32'd0;
    dmem[1116] = 32'd0;
    dmem[1117] = 32'd0;
    dmem[1118] = 32'd0;
    dmem[1119] = 32'd0;
    dmem[1120] = 32'd0;
    dmem[1121] = 32'd0;
    dmem[1122] = 32'd0;
    dmem[1123] = 32'd0;
    dmem[1124] = 32'd0;
    dmem[1125] = 32'd0;
    dmem[1126] = 32'd0;
    dmem[1127] = 32'd0;
    dmem[1128] = 32'd0;
    dmem[1129] = 32'd0;
    dmem[1130] = 32'd0;
    dmem[1131] = 32'd0;
    dmem[1132] = 32'd0;
    dmem[1133] = 32'd0;
    dmem[1134] = 32'd0;
    dmem[1135] = 32'd0;
    dmem[1136] = 32'd0;
    dmem[1137] = 32'd0;
    dmem[1138] = 32'd0;
    dmem[1139] = 32'd0;
    dmem[1140] = 32'd0;
    dmem[1141] = 32'd0;
    dmem[1142] = 32'd0;
    dmem[1143] = 32'd0;
    dmem[1144] = 32'd0;
    dmem[1145] = 32'd0;
    dmem[1146] = 32'd0;
    dmem[1147] = 32'd0;
    dmem[1148] = 32'd0;
    dmem[1149] = 32'd0;
    dmem[1150] = 32'd0;
    dmem[1151] = 32'd0;
    dmem[1152] = 32'd0;
    dmem[1153] = 32'd0;
    dmem[1154] = 32'd0;
    dmem[1155] = 32'd0;
    dmem[1156] = 32'd0;
    dmem[1157] = 32'd0;
    dmem[1158] = 32'd0;
    dmem[1159] = 32'd0;
    dmem[1160] = 32'd0;
    dmem[1161] = 32'd0;
    dmem[1162] = 32'd0;
    dmem[1163] = 32'd0;
    dmem[1164] = 32'd0;
    dmem[1165] = 32'd0;
    dmem[1166] = 32'd0;
    dmem[1167] = 32'd0;
    dmem[1168] = 32'd0;
    dmem[1169] = 32'd0;
    dmem[1170] = 32'd0;
    dmem[1171] = 32'd0;
    dmem[1172] = 32'd0;
    dmem[1173] = 32'd0;
    dmem[1174] = 32'd0;
    dmem[1175] = 32'd0;
    dmem[1176] = 32'd0;
    dmem[1177] = 32'd0;
    dmem[1178] = 32'd0;
    dmem[1179] = 32'd0;
    dmem[1180] = 32'd0;
    dmem[1181] = 32'd0;
    dmem[1182] = 32'd0;
    dmem[1183] = 32'd0;
    dmem[1184] = 32'd0;
    dmem[1185] = 32'd0;
    dmem[1186] = 32'd0;
    dmem[1187] = 32'd0;
    dmem[1188] = 32'd0;
    dmem[1189] = 32'd0;
    dmem[1190] = 32'd0;
    dmem[1191] = 32'd0;
    dmem[1192] = 32'd0;
    dmem[1193] = 32'd0;
    dmem[1194] = 32'd0;
    dmem[1195] = 32'd0;
    dmem[1196] = 32'd0;
    dmem[1197] = 32'd0;
    dmem[1198] = 32'd0;
    dmem[1199] = 32'd0;
    dmem[1200] = 32'd0;
    dmem[1201] = 32'd0;
    dmem[1202] = 32'd0;
    dmem[1203] = 32'd0;
    dmem[1204] = 32'd0;
    dmem[1205] = 32'd0;
    dmem[1206] = 32'd0;
    dmem[1207] = 32'd0;
    dmem[1208] = 32'd0;
    dmem[1209] = 32'd0;
    dmem[1210] = 32'd0;
    dmem[1211] = 32'd0;
    dmem[1212] = 32'd0;
    dmem[1213] = 32'd0;
    dmem[1214] = 32'd0;
    dmem[1215] = 32'd0;
    dmem[1216] = 32'd0;
    dmem[1217] = 32'd0;
    dmem[1218] = 32'd0;
    dmem[1219] = 32'd0;
    dmem[1220] = 32'd0;
    dmem[1221] = 32'd0;
    dmem[1222] = 32'd0;
    dmem[1223] = 32'd0;
    dmem[1224] = 32'd0;
    dmem[1225] = 32'd0;
    dmem[1226] = 32'd0;
    dmem[1227] = 32'd0;
    dmem[1228] = 32'd0;
    dmem[1229] = 32'd0;
    dmem[1230] = 32'd0;
    dmem[1231] = 32'd0;
    dmem[1232] = 32'd0;
    dmem[1233] = 32'd0;
    dmem[1234] = 32'd0;
    dmem[1235] = 32'd0;
    dmem[1236] = 32'd0;
    dmem[1237] = 32'd0;
    dmem[1238] = 32'd0;
    dmem[1239] = 32'd0;
    dmem[1240] = 32'd0;
    dmem[1241] = 32'd0;
    dmem[1242] = 32'd0;
    dmem[1243] = 32'd0;
    dmem[1244] = 32'd0;
    dmem[1245] = 32'd0;
    dmem[1246] = 32'd0;
    dmem[1247] = 32'd0;
    dmem[1248] = 32'd0;
    dmem[1249] = 32'd0;
    dmem[1250] = 32'd0;
    dmem[1251] = 32'd0;
    dmem[1252] = 32'd0;
    dmem[1253] = 32'd0;
    dmem[1254] = 32'd0;
    dmem[1255] = 32'd0;
    dmem[1256] = 32'd0;
    dmem[1257] = 32'd0;
    dmem[1258] = 32'd0;
    dmem[1259] = 32'd0;
    dmem[1260] = 32'd0;
    dmem[1261] = 32'd0;
    dmem[1262] = 32'd0;
    dmem[1263] = 32'd0;
    dmem[1264] = 32'd0;
    dmem[1265] = 32'd0;
    dmem[1266] = 32'd0;
    dmem[1267] = 32'd0;
    dmem[1268] = 32'd0;
    dmem[1269] = 32'd0;
    dmem[1270] = 32'd0;
    dmem[1271] = 32'd0;
    dmem[1272] = 32'd0;
    dmem[1273] = 32'd0;
    dmem[1274] = 32'd0;
    dmem[1275] = 32'd0;
    dmem[1276] = 32'd0;
    dmem[1277] = 32'd0;
    dmem[1278] = 32'd0;
    dmem[1279] = 32'd0;
    dmem[1280] = 32'd0;
    dmem[1281] = 32'd0;
    dmem[1282] = 32'd0;
    dmem[1283] = 32'd0;
    dmem[1284] = 32'd0;
    dmem[1285] = 32'd0;
    dmem[1286] = 32'd0;
    dmem[1287] = 32'd0;
    dmem[1288] = 32'd0;
    dmem[1289] = 32'd0;
    dmem[1290] = 32'd0;
    dmem[1291] = 32'd0;
    dmem[1292] = 32'd0;
    dmem[1293] = 32'd0;
    dmem[1294] = 32'd0;
    dmem[1295] = 32'd0;
    dmem[1296] = 32'd0;
    dmem[1297] = 32'd0;
    dmem[1298] = 32'd0;
    dmem[1299] = 32'd0;
    dmem[1300] = 32'd0;
    dmem[1301] = 32'd0;
    dmem[1302] = 32'd0;
    dmem[1303] = 32'd0;
    dmem[1304] = 32'd0;
    dmem[1305] = 32'd0;
    dmem[1306] = 32'd0;
    dmem[1307] = 32'd0;
    dmem[1308] = 32'd0;
    dmem[1309] = 32'd0;
    dmem[1310] = 32'd0;
    dmem[1311] = 32'd0;
    dmem[1312] = 32'd0;
    dmem[1313] = 32'd0;
    dmem[1314] = 32'd0;
    dmem[1315] = 32'd0;
    dmem[1316] = 32'd0;
    dmem[1317] = 32'd0;
    dmem[1318] = 32'd0;
    dmem[1319] = 32'd0;
    dmem[1320] = 32'd0;
    dmem[1321] = 32'd0;
    dmem[1322] = 32'd0;
    dmem[1323] = 32'd0;
    dmem[1324] = 32'd0;
    dmem[1325] = 32'd0;
    dmem[1326] = 32'd0;
    dmem[1327] = 32'd0;
    dmem[1328] = 32'd0;
    dmem[1329] = 32'd0;
    dmem[1330] = 32'd0;
    dmem[1331] = 32'd0;
    dmem[1332] = 32'd0;
    dmem[1333] = 32'd0;
    dmem[1334] = 32'd0;
    dmem[1335] = 32'd0;
    dmem[1336] = 32'd0;
    dmem[1337] = 32'd0;
    dmem[1338] = 32'd0;
    dmem[1339] = 32'd0;
    dmem[1340] = 32'd0;
    dmem[1341] = 32'd0;
    dmem[1342] = 32'd0;
    dmem[1343] = 32'd0;
    dmem[1344] = 32'd0;
    dmem[1345] = 32'd0;
    dmem[1346] = 32'd0;
    dmem[1347] = 32'd0;
    dmem[1348] = 32'd0;
    dmem[1349] = 32'd0;
    dmem[1350] = 32'd0;
    dmem[1351] = 32'd0;
    dmem[1352] = 32'd0;
    dmem[1353] = 32'd0;
    dmem[1354] = 32'd0;
    dmem[1355] = 32'd0;
    dmem[1356] = 32'd0;
    dmem[1357] = 32'd0;
    dmem[1358] = 32'd0;
    dmem[1359] = 32'd0;
    dmem[1360] = 32'd0;
    dmem[1361] = 32'd0;
    dmem[1362] = 32'd0;
    dmem[1363] = 32'd0;
    dmem[1364] = 32'd0;
    dmem[1365] = 32'd0;
    dmem[1366] = 32'd0;
    dmem[1367] = 32'd0;
    dmem[1368] = 32'd0;
    dmem[1369] = 32'd0;
    dmem[1370] = 32'd0;
    dmem[1371] = 32'd0;
    dmem[1372] = 32'd0;
    dmem[1373] = 32'd0;
    dmem[1374] = 32'd0;
    dmem[1375] = 32'd0;
    dmem[1376] = 32'd0;
    dmem[1377] = 32'd0;
    dmem[1378] = 32'd0;
    dmem[1379] = 32'd0;
    dmem[1380] = 32'd0;
    dmem[1381] = 32'd0;
    dmem[1382] = 32'd0;
    dmem[1383] = 32'd0;
    dmem[1384] = 32'd0;
    dmem[1385] = 32'd0;
    dmem[1386] = 32'd0;
    dmem[1387] = 32'd0;
    dmem[1388] = 32'd0;
    dmem[1389] = 32'd0;
    dmem[1390] = 32'd0;
    dmem[1391] = 32'd0;
    dmem[1392] = 32'd0;
    dmem[1393] = 32'd0;
    dmem[1394] = 32'd0;
    dmem[1395] = 32'd0;
    dmem[1396] = 32'd0;
    dmem[1397] = 32'd0;
    dmem[1398] = 32'd0;
    dmem[1399] = 32'd0;
    dmem[1400] = 32'd0;
    dmem[1401] = 32'd0;
    dmem[1402] = 32'd0;
    dmem[1403] = 32'd0;
    dmem[1404] = 32'd0;
    dmem[1405] = 32'd0;
    dmem[1406] = 32'd0;
    dmem[1407] = 32'd0;
    dmem[1408] = 32'd0;
    dmem[1409] = 32'd0;
    dmem[1410] = 32'd0;
    dmem[1411] = 32'd0;
    dmem[1412] = 32'd0;
    dmem[1413] = 32'd0;
    dmem[1414] = 32'd0;
    dmem[1415] = 32'd0;
    dmem[1416] = 32'd0;
    dmem[1417] = 32'd0;
    dmem[1418] = 32'd0;
    dmem[1419] = 32'd0;
    dmem[1420] = 32'd0;
    dmem[1421] = 32'd0;
    dmem[1422] = 32'd0;
    dmem[1423] = 32'd0;
    dmem[1424] = 32'd0;
    dmem[1425] = 32'd0;
    dmem[1426] = 32'd0;
    dmem[1427] = 32'd0;
    dmem[1428] = 32'd0;
    dmem[1429] = 32'd0;
    dmem[1430] = 32'd0;
    dmem[1431] = 32'd0;
    dmem[1432] = 32'd0;
    dmem[1433] = 32'd0;
    dmem[1434] = 32'd0;
    dmem[1435] = 32'd0;
    dmem[1436] = 32'd0;
    dmem[1437] = 32'd0;
    dmem[1438] = 32'd0;
    dmem[1439] = 32'd0;
    dmem[1440] = 32'd0;
    dmem[1441] = 32'd0;
    dmem[1442] = 32'd0;
    dmem[1443] = 32'd0;
    dmem[1444] = 32'd0;
    dmem[1445] = 32'd0;
    dmem[1446] = 32'd0;
    dmem[1447] = 32'd0;
    dmem[1448] = 32'd0;
    dmem[1449] = 32'd0;
    dmem[1450] = 32'd0;
    dmem[1451] = 32'd0;
    dmem[1452] = 32'd0;
    dmem[1453] = 32'd0;
    dmem[1454] = 32'd0;
    dmem[1455] = 32'd0;
    dmem[1456] = 32'd0;
    dmem[1457] = 32'd0;
    dmem[1458] = 32'd0;
    dmem[1459] = 32'd0;
    dmem[1460] = 32'd0;
    dmem[1461] = 32'd0;
    dmem[1462] = 32'd0;
    dmem[1463] = 32'd0;
    dmem[1464] = 32'd0;
    dmem[1465] = 32'd0;
    dmem[1466] = 32'd0;
    dmem[1467] = 32'd0;
    dmem[1468] = 32'd0;
    dmem[1469] = 32'd0;
    dmem[1470] = 32'd0;
    dmem[1471] = 32'd0;
    dmem[1472] = 32'd0;
    dmem[1473] = 32'd0;
    dmem[1474] = 32'd0;
    dmem[1475] = 32'd0;
    dmem[1476] = 32'd0;
    dmem[1477] = 32'd0;
    dmem[1478] = 32'd0;
    dmem[1479] = 32'd0;
    dmem[1480] = 32'd0;
    dmem[1481] = 32'd0;
    dmem[1482] = 32'd0;
    dmem[1483] = 32'd0;
    dmem[1484] = 32'd0;
    dmem[1485] = 32'd0;
    dmem[1486] = 32'd0;
    dmem[1487] = 32'd0;
    dmem[1488] = 32'd0;
    dmem[1489] = 32'd0;
    dmem[1490] = 32'd0;
    dmem[1491] = 32'd0;
    dmem[1492] = 32'd0;
    dmem[1493] = 32'd0;
    dmem[1494] = 32'd0;
    dmem[1495] = 32'd0;
    dmem[1496] = 32'd0;
    dmem[1497] = 32'd0;
    dmem[1498] = 32'd0;
    dmem[1499] = 32'd0;
    dmem[1500] = 32'd0;
    dmem[1501] = 32'd0;
    dmem[1502] = 32'd0;
    dmem[1503] = 32'd0;
    dmem[1504] = 32'd0;
    dmem[1505] = 32'd0;
    dmem[1506] = 32'd0;
    dmem[1507] = 32'd0;
    dmem[1508] = 32'd0;
    dmem[1509] = 32'd0;
    dmem[1510] = 32'd0;
    dmem[1511] = 32'd0;
    dmem[1512] = 32'd0;
    dmem[1513] = 32'd0;
    dmem[1514] = 32'd0;
    dmem[1515] = 32'd0;
    dmem[1516] = 32'd0;
    dmem[1517] = 32'd0;
    dmem[1518] = 32'd0;
    dmem[1519] = 32'd0;
    dmem[1520] = 32'd0;
    dmem[1521] = 32'd0;
    dmem[1522] = 32'd0;
    dmem[1523] = 32'd0;
    dmem[1524] = 32'd0;
    dmem[1525] = 32'd0;
    dmem[1526] = 32'd0;
    dmem[1527] = 32'd0;
    dmem[1528] = 32'd0;
    dmem[1529] = 32'd0;
    dmem[1530] = 32'd0;
    dmem[1531] = 32'd0;
    dmem[1532] = 32'd0;
    dmem[1533] = 32'd0;
    dmem[1534] = 32'd0;
    dmem[1535] = 32'd0;
    dmem[1536] = 32'd0;
    dmem[1537] = 32'd0;
    dmem[1538] = 32'd0;
    dmem[1539] = 32'd0;
    dmem[1540] = 32'd0;
    dmem[1541] = 32'd0;
    dmem[1542] = 32'd0;
    dmem[1543] = 32'd0;
    dmem[1544] = 32'd0;
    dmem[1545] = 32'd0;
    dmem[1546] = 32'd0;
    dmem[1547] = 32'd0;
    dmem[1548] = 32'd0;
    dmem[1549] = 32'd0;
    dmem[1550] = 32'd0;
    dmem[1551] = 32'd0;
    dmem[1552] = 32'd0;
    dmem[1553] = 32'd0;
    dmem[1554] = 32'd0;
    dmem[1555] = 32'd0;
    dmem[1556] = 32'd0;
    dmem[1557] = 32'd0;
    dmem[1558] = 32'd0;
    dmem[1559] = 32'd0;
    dmem[1560] = 32'd0;
    dmem[1561] = 32'd0;
    dmem[1562] = 32'd0;
    dmem[1563] = 32'd0;
    dmem[1564] = 32'd0;
    dmem[1565] = 32'd0;
    dmem[1566] = 32'd0;
    dmem[1567] = 32'd0;
    dmem[1568] = 32'd0;
    dmem[1569] = 32'd0;
    dmem[1570] = 32'd0;
    dmem[1571] = 32'd0;
    dmem[1572] = 32'd0;
    dmem[1573] = 32'd0;
    dmem[1574] = 32'd0;
    dmem[1575] = 32'd0;
    dmem[1576] = 32'd0;
    dmem[1577] = 32'd0;
    dmem[1578] = 32'd0;
    dmem[1579] = 32'd0;
    dmem[1580] = 32'd0;
    dmem[1581] = 32'd0;
    dmem[1582] = 32'd0;
    dmem[1583] = 32'd0;
    dmem[1584] = 32'd0;
    dmem[1585] = 32'd0;
    dmem[1586] = 32'd0;
    dmem[1587] = 32'd0;
    dmem[1588] = 32'd0;
    dmem[1589] = 32'd0;
    dmem[1590] = 32'd0;
    dmem[1591] = 32'd0;
    dmem[1592] = 32'd0;
    dmem[1593] = 32'd0;
    dmem[1594] = 32'd0;
    dmem[1595] = 32'd0;
    dmem[1596] = 32'd0;
    dmem[1597] = 32'd0;
    dmem[1598] = 32'd0;
    dmem[1599] = 32'd0;
    dmem[1600] = 32'd0;
    dmem[1601] = 32'd0;
    dmem[1602] = 32'd0;
    dmem[1603] = 32'd0;
    dmem[1604] = 32'd0;
    dmem[1605] = 32'd0;
    dmem[1606] = 32'd0;
    dmem[1607] = 32'd0;
    dmem[1608] = 32'd0;
    dmem[1609] = 32'd0;
    dmem[1610] = 32'd0;
    dmem[1611] = 32'd0;
    dmem[1612] = 32'd0;
    dmem[1613] = 32'd0;
    dmem[1614] = 32'd0;
    dmem[1615] = 32'd0;
    dmem[1616] = 32'd0;
    dmem[1617] = 32'd0;
    dmem[1618] = 32'd0;
    dmem[1619] = 32'd0;
    dmem[1620] = 32'd0;
    dmem[1621] = 32'd0;
    dmem[1622] = 32'd0;
    dmem[1623] = 32'd0;
    dmem[1624] = 32'd0;
    dmem[1625] = 32'd0;
    dmem[1626] = 32'd0;
    dmem[1627] = 32'd0;
    dmem[1628] = 32'd0;
    dmem[1629] = 32'd0;
    dmem[1630] = 32'd0;
    dmem[1631] = 32'd0;
    dmem[1632] = 32'd0;
    dmem[1633] = 32'd0;
    dmem[1634] = 32'd0;
    dmem[1635] = 32'd0;
    dmem[1636] = 32'd0;
    dmem[1637] = 32'd0;
    dmem[1638] = 32'd0;
    dmem[1639] = 32'd0;
    dmem[1640] = 32'd0;
    dmem[1641] = 32'd0;
    dmem[1642] = 32'd0;
    dmem[1643] = 32'd0;
    dmem[1644] = 32'd0;
    dmem[1645] = 32'd0;
    dmem[1646] = 32'd0;
    dmem[1647] = 32'd0;
    dmem[1648] = 32'd0;
    dmem[1649] = 32'd0;
    dmem[1650] = 32'd0;
    dmem[1651] = 32'd0;
    dmem[1652] = 32'd0;
    dmem[1653] = 32'd0;
    dmem[1654] = 32'd0;
    dmem[1655] = 32'd0;
    dmem[1656] = 32'd0;
    dmem[1657] = 32'd0;
    dmem[1658] = 32'd0;
    dmem[1659] = 32'd0;
    dmem[1660] = 32'd0;
    dmem[1661] = 32'd0;
    dmem[1662] = 32'd0;
    dmem[1663] = 32'd0;
    dmem[1664] = 32'd0;
    dmem[1665] = 32'd0;
    dmem[1666] = 32'd0;
    dmem[1667] = 32'd0;
    dmem[1668] = 32'd0;
    dmem[1669] = 32'd0;
    dmem[1670] = 32'd0;
    dmem[1671] = 32'd0;
    dmem[1672] = 32'd0;
    dmem[1673] = 32'd0;
    dmem[1674] = 32'd0;
    dmem[1675] = 32'd0;
    dmem[1676] = 32'd0;
    dmem[1677] = 32'd0;
    dmem[1678] = 32'd0;
    dmem[1679] = 32'd0;
    dmem[1680] = 32'd0;
    dmem[1681] = 32'd0;
    dmem[1682] = 32'd0;
    dmem[1683] = 32'd0;
    dmem[1684] = 32'd0;
    dmem[1685] = 32'd0;
    dmem[1686] = 32'd0;
    dmem[1687] = 32'd0;
    dmem[1688] = 32'd0;
    dmem[1689] = 32'd0;
    dmem[1690] = 32'd0;
    dmem[1691] = 32'd0;
    dmem[1692] = 32'd0;
    dmem[1693] = 32'd0;
    dmem[1694] = 32'd0;
    dmem[1695] = 32'd0;
    dmem[1696] = 32'd0;
    dmem[1697] = 32'd0;
    dmem[1698] = 32'd0;
    dmem[1699] = 32'd0;
    dmem[1700] = 32'd0;
    dmem[1701] = 32'd0;
    dmem[1702] = 32'd0;
    dmem[1703] = 32'd0;
    dmem[1704] = 32'd0;
    dmem[1705] = 32'd0;
    dmem[1706] = 32'd0;
    dmem[1707] = 32'd0;
    dmem[1708] = 32'd0;
    dmem[1709] = 32'd0;
    dmem[1710] = 32'd0;
    dmem[1711] = 32'd0;
    dmem[1712] = 32'd0;
    dmem[1713] = 32'd0;
    dmem[1714] = 32'd0;
    dmem[1715] = 32'd0;
    dmem[1716] = 32'd0;
    dmem[1717] = 32'd0;
    dmem[1718] = 32'd0;
    dmem[1719] = 32'd0;
    dmem[1720] = 32'd0;
    dmem[1721] = 32'd0;
    dmem[1722] = 32'd0;
    dmem[1723] = 32'd0;
    dmem[1724] = 32'd0;
    dmem[1725] = 32'd0;
    dmem[1726] = 32'd0;
    dmem[1727] = 32'd0;
    dmem[1728] = 32'd0;
    dmem[1729] = 32'd0;
    dmem[1730] = 32'd0;
    dmem[1731] = 32'd0;
    dmem[1732] = 32'd0;
    dmem[1733] = 32'd0;
    dmem[1734] = 32'd0;
    dmem[1735] = 32'd0;
    dmem[1736] = 32'd0;
    dmem[1737] = 32'd0;
    dmem[1738] = 32'd0;
    dmem[1739] = 32'd0;
    dmem[1740] = 32'd0;
    dmem[1741] = 32'd0;
    dmem[1742] = 32'd0;
    dmem[1743] = 32'd0;
    dmem[1744] = 32'd0;
    dmem[1745] = 32'd0;
    dmem[1746] = 32'd0;
    dmem[1747] = 32'd0;
    dmem[1748] = 32'd0;
    dmem[1749] = 32'd0;
    dmem[1750] = 32'd0;
    dmem[1751] = 32'd0;
    dmem[1752] = 32'd0;
    dmem[1753] = 32'd0;
    dmem[1754] = 32'd0;
    dmem[1755] = 32'd0;
    dmem[1756] = 32'd0;
    dmem[1757] = 32'd0;
    dmem[1758] = 32'd0;
    dmem[1759] = 32'd0;
    dmem[1760] = 32'd0;
    dmem[1761] = 32'd0;
    dmem[1762] = 32'd0;
    dmem[1763] = 32'd0;
    dmem[1764] = 32'd0;
    dmem[1765] = 32'd0;
    dmem[1766] = 32'd0;
    dmem[1767] = 32'd0;
    dmem[1768] = 32'd0;
    dmem[1769] = 32'd0;
    dmem[1770] = 32'd0;
    dmem[1771] = 32'd0;
    dmem[1772] = 32'd0;
    dmem[1773] = 32'd0;
    dmem[1774] = 32'd0;
    dmem[1775] = 32'd0;
    dmem[1776] = 32'd0;
    dmem[1777] = 32'd0;
    dmem[1778] = 32'd0;
    dmem[1779] = 32'd0;
    dmem[1780] = 32'd0;
    dmem[1781] = 32'd0;
    dmem[1782] = 32'd0;
    dmem[1783] = 32'd0;
    dmem[1784] = 32'd0;
    dmem[1785] = 32'd0;
    dmem[1786] = 32'd0;
    dmem[1787] = 32'd0;
    dmem[1788] = 32'd0;
    dmem[1789] = 32'd0;
    dmem[1790] = 32'd0;
    dmem[1791] = 32'd0;
    dmem[1792] = 32'd0;
    dmem[1793] = 32'd0;
    dmem[1794] = 32'd0;
    dmem[1795] = 32'd0;
    dmem[1796] = 32'd0;
    dmem[1797] = 32'd0;
    dmem[1798] = 32'd0;
    dmem[1799] = 32'd0;
    dmem[1800] = 32'd0;
    dmem[1801] = 32'd0;
    dmem[1802] = 32'd0;
    dmem[1803] = 32'd0;
    dmem[1804] = 32'd0;
    dmem[1805] = 32'd0;
    dmem[1806] = 32'd0;
    dmem[1807] = 32'd0;
    dmem[1808] = 32'd0;
    dmem[1809] = 32'd0;
    dmem[1810] = 32'd0;
    dmem[1811] = 32'd0;
    dmem[1812] = 32'd0;
    dmem[1813] = 32'd0;
    dmem[1814] = 32'd0;
    dmem[1815] = 32'd0;
    dmem[1816] = 32'd0;
    dmem[1817] = 32'd0;
    dmem[1818] = 32'd0;
    dmem[1819] = 32'd0;
    dmem[1820] = 32'd0;
    dmem[1821] = 32'd0;
    dmem[1822] = 32'd0;
    dmem[1823] = 32'd0;
    dmem[1824] = 32'd0;
    dmem[1825] = 32'd0;
    dmem[1826] = 32'd0;
    dmem[1827] = 32'd0;
    dmem[1828] = 32'd0;
    dmem[1829] = 32'd0;
    dmem[1830] = 32'd0;
    dmem[1831] = 32'd0;
    dmem[1832] = 32'd0;
    dmem[1833] = 32'd0;
    dmem[1834] = 32'd0;
    dmem[1835] = 32'd0;
    dmem[1836] = 32'd0;
    dmem[1837] = 32'd0;
    dmem[1838] = 32'd0;
    dmem[1839] = 32'd0;
    dmem[1840] = 32'd0;
    dmem[1841] = 32'd0;
    dmem[1842] = 32'd0;
    dmem[1843] = 32'd0;
    dmem[1844] = 32'd0;
    dmem[1845] = 32'd0;
    dmem[1846] = 32'd0;
    dmem[1847] = 32'd0;
    dmem[1848] = 32'd0;
    dmem[1849] = 32'd0;
    dmem[1850] = 32'd0;
    dmem[1851] = 32'd0;
    dmem[1852] = 32'd0;
    dmem[1853] = 32'd0;
    dmem[1854] = 32'd0;
    dmem[1855] = 32'd0;
    dmem[1856] = 32'd0;
    dmem[1857] = 32'd0;
    dmem[1858] = 32'd0;
    dmem[1859] = 32'd0;
    dmem[1860] = 32'd0;
    dmem[1861] = 32'd0;
    dmem[1862] = 32'd0;
    dmem[1863] = 32'd0;
    dmem[1864] = 32'd0;
    dmem[1865] = 32'd0;
    dmem[1866] = 32'd0;
    dmem[1867] = 32'd0;
    dmem[1868] = 32'd0;
    dmem[1869] = 32'd0;
    dmem[1870] = 32'd0;
    dmem[1871] = 32'd0;
    dmem[1872] = 32'd0;
    dmem[1873] = 32'd0;
    dmem[1874] = 32'd0;
    dmem[1875] = 32'd0;
    dmem[1876] = 32'd0;
    dmem[1877] = 32'd0;
    dmem[1878] = 32'd0;
    dmem[1879] = 32'd0;
    dmem[1880] = 32'd0;
    dmem[1881] = 32'd0;
    dmem[1882] = 32'd0;
    dmem[1883] = 32'd0;
    dmem[1884] = 32'd0;
    dmem[1885] = 32'd0;
    dmem[1886] = 32'd0;
    dmem[1887] = 32'd0;
    dmem[1888] = 32'd0;
    dmem[1889] = 32'd0;
    dmem[1890] = 32'd0;
    dmem[1891] = 32'd0;
    dmem[1892] = 32'd0;
    dmem[1893] = 32'd0;
    dmem[1894] = 32'd0;
    dmem[1895] = 32'd0;
    dmem[1896] = 32'd0;
    dmem[1897] = 32'd0;
    dmem[1898] = 32'd0;
    dmem[1899] = 32'd0;
    dmem[1900] = 32'd0;
    dmem[1901] = 32'd0;
    dmem[1902] = 32'd0;
    dmem[1903] = 32'd0;
    dmem[1904] = 32'd0;
    dmem[1905] = 32'd0;
    dmem[1906] = 32'd0;
    dmem[1907] = 32'd0;
    dmem[1908] = 32'd0;
    dmem[1909] = 32'd0;
    dmem[1910] = 32'd0;
    dmem[1911] = 32'd0;
    dmem[1912] = 32'd0;
    dmem[1913] = 32'd0;
    dmem[1914] = 32'd0;
    dmem[1915] = 32'd0;
    dmem[1916] = 32'd0;
    dmem[1917] = 32'd0;
    dmem[1918] = 32'd0;
    dmem[1919] = 32'd0;
    dmem[1920] = 32'd0;
    dmem[1921] = 32'd0;
    dmem[1922] = 32'd0;
    dmem[1923] = 32'd0;
    dmem[1924] = 32'd0;
    dmem[1925] = 32'd0;
    dmem[1926] = 32'd0;
    dmem[1927] = 32'd0;
    dmem[1928] = 32'd0;
    dmem[1929] = 32'd0;
    dmem[1930] = 32'd0;
    dmem[1931] = 32'd0;
    dmem[1932] = 32'd0;
    dmem[1933] = 32'd0;
    dmem[1934] = 32'd0;
    dmem[1935] = 32'd0;
    dmem[1936] = 32'd0;
    dmem[1937] = 32'd0;
    dmem[1938] = 32'd0;
    dmem[1939] = 32'd0;
    dmem[1940] = 32'd0;
    dmem[1941] = 32'd0;
    dmem[1942] = 32'd0;
    dmem[1943] = 32'd0;
    dmem[1944] = 32'd0;
    dmem[1945] = 32'd0;
    dmem[1946] = 32'd0;
    dmem[1947] = 32'd0;
    dmem[1948] = 32'd0;
    dmem[1949] = 32'd0;
    dmem[1950] = 32'd0;
    dmem[1951] = 32'd0;
    dmem[1952] = 32'd0;
    dmem[1953] = 32'd0;
    dmem[1954] = 32'd0;
    dmem[1955] = 32'd0;
    dmem[1956] = 32'd0;
    dmem[1957] = 32'd0;
    dmem[1958] = 32'd0;
    dmem[1959] = 32'd0;
    dmem[1960] = 32'd0;
    dmem[1961] = 32'd0;
    dmem[1962] = 32'd0;
    dmem[1963] = 32'd0;
    dmem[1964] = 32'd0;
    dmem[1965] = 32'd0;
    dmem[1966] = 32'd0;
    dmem[1967] = 32'd0;
    dmem[1968] = 32'd0;
    dmem[1969] = 32'd0;
    dmem[1970] = 32'd0;
    dmem[1971] = 32'd0;
    dmem[1972] = 32'd0;
    dmem[1973] = 32'd0;
    dmem[1974] = 32'd0;
    dmem[1975] = 32'd0;
    dmem[1976] = 32'd0;
    dmem[1977] = 32'd0;
    dmem[1978] = 32'd0;
    dmem[1979] = 32'd0;
    dmem[1980] = 32'd0;
    dmem[1981] = 32'd0;
    dmem[1982] = 32'd0;
    dmem[1983] = 32'd0;
    dmem[1984] = 32'd0;
    dmem[1985] = 32'd0;
    dmem[1986] = 32'd0;
    dmem[1987] = 32'd0;
    dmem[1988] = 32'd0;
    dmem[1989] = 32'd0;
    dmem[1990] = 32'd0;
    dmem[1991] = 32'd0;
    dmem[1992] = 32'd0;
    dmem[1993] = 32'd0;
    dmem[1994] = 32'd0;
    dmem[1995] = 32'd0;
    dmem[1996] = 32'd0;
    dmem[1997] = 32'd0;
    dmem[1998] = 32'd0;
    dmem[1999] = 32'd0;
    dmem[2000] = 32'd0;
    dmem[2001] = 32'd0;
    dmem[2002] = 32'd0;
    dmem[2003] = 32'd0;
    dmem[2004] = 32'd0;
    dmem[2005] = 32'd0;
    dmem[2006] = 32'd0;
    dmem[2007] = 32'd0;
    dmem[2008] = 32'd0;
    dmem[2009] = 32'd0;
    dmem[2010] = 32'd0;
    dmem[2011] = 32'd0;
    dmem[2012] = 32'd0;
    dmem[2013] = 32'd0;
    dmem[2014] = 32'd0;
    dmem[2015] = 32'd0;
    dmem[2016] = 32'd0;
    dmem[2017] = 32'd0;
    dmem[2018] = 32'd0;
    dmem[2019] = 32'd0;
    dmem[2020] = 32'd0;
    dmem[2021] = 32'd0;
    dmem[2022] = 32'd0;
    dmem[2023] = 32'd0;
    dmem[2024] = 32'd0;
    dmem[2025] = 32'd0;
    dmem[2026] = 32'd0;
    dmem[2027] = 32'd0;
    dmem[2028] = 32'd0;
    dmem[2029] = 32'd0;
    dmem[2030] = 32'd0;
    dmem[2031] = 32'd0;
    dmem[2032] = 32'd0;
    dmem[2033] = 32'd0;
    dmem[2034] = 32'd0;
    dmem[2035] = 32'd0;
    dmem[2036] = 32'd0;
    dmem[2037] = 32'd0;
    dmem[2038] = 32'd0;
    dmem[2039] = 32'd0;
    dmem[2040] = 32'd0;
    dmem[2041] = 32'd0;
    dmem[2042] = 32'd0;
    dmem[2043] = 32'd0;
    dmem[2044] = 32'd0;
    dmem[2045] = 32'd0;
    dmem[2046] = 32'd0;
    dmem[2047] = 32'd0;
    dmem[2048] = 32'd0;
    dmem[2049] = 32'd0;
    dmem[2050] = 32'd0;
    dmem[2051] = 32'd0;
    dmem[2052] = 32'd0;
    dmem[2053] = 32'd0;
    dmem[2054] = 32'd0;
    dmem[2055] = 32'd0;
    dmem[2056] = 32'd0;
    dmem[2057] = 32'd0;
    dmem[2058] = 32'd0;
    dmem[2059] = 32'd0;
    dmem[2060] = 32'd0;
    dmem[2061] = 32'd0;
    dmem[2062] = 32'd0;
    dmem[2063] = 32'd0;
    dmem[2064] = 32'd0;
    dmem[2065] = 32'd0;
    dmem[2066] = 32'd0;
    dmem[2067] = 32'd0;
    dmem[2068] = 32'd0;
    dmem[2069] = 32'd0;
    dmem[2070] = 32'd0;
    dmem[2071] = 32'd0;
    dmem[2072] = 32'd0;
    dmem[2073] = 32'd0;
    dmem[2074] = 32'd0;
    dmem[2075] = 32'd0;
    dmem[2076] = 32'd0;
    dmem[2077] = 32'd0;
    dmem[2078] = 32'd0;
    dmem[2079] = 32'd0;
    dmem[2080] = 32'd0;
    dmem[2081] = 32'd0;
    dmem[2082] = 32'd0;
    dmem[2083] = 32'd0;
    dmem[2084] = 32'd0;
    dmem[2085] = 32'd0;
    dmem[2086] = 32'd0;
    dmem[2087] = 32'd0;
    dmem[2088] = 32'd0;
    dmem[2089] = 32'd0;
    dmem[2090] = 32'd0;
    dmem[2091] = 32'd0;
    dmem[2092] = 32'd0;
    dmem[2093] = 32'd0;
    dmem[2094] = 32'd0;
    dmem[2095] = 32'd0;
    dmem[2096] = 32'd0;
    dmem[2097] = 32'd0;
    dmem[2098] = 32'd0;
    dmem[2099] = 32'd0;
    dmem[2100] = 32'd0;
    dmem[2101] = 32'd0;
    dmem[2102] = 32'd0;
    dmem[2103] = 32'd0;
    dmem[2104] = 32'd0;
    dmem[2105] = 32'd0;
    dmem[2106] = 32'd0;
    dmem[2107] = 32'd0;
    dmem[2108] = 32'd0;
    dmem[2109] = 32'd0;
    dmem[2110] = 32'd0;
    dmem[2111] = 32'd0;
    dmem[2112] = 32'd0;
    dmem[2113] = 32'd0;
    dmem[2114] = 32'd0;
    dmem[2115] = 32'd0;
    dmem[2116] = 32'd0;
    dmem[2117] = 32'd0;
    dmem[2118] = 32'd0;
    dmem[2119] = 32'd0;
    dmem[2120] = 32'd0;
    dmem[2121] = 32'd0;
    dmem[2122] = 32'd0;
    dmem[2123] = 32'd0;
    dmem[2124] = 32'd0;
    dmem[2125] = 32'd0;
    dmem[2126] = 32'd0;
    dmem[2127] = 32'd0;
    dmem[2128] = 32'd0;
    dmem[2129] = 32'd0;
    dmem[2130] = 32'd0;
    dmem[2131] = 32'd0;
    dmem[2132] = 32'd0;
    dmem[2133] = 32'd0;
    dmem[2134] = 32'd0;
    dmem[2135] = 32'd0;
    dmem[2136] = 32'd0;
    dmem[2137] = 32'd0;
    dmem[2138] = 32'd0;
    dmem[2139] = 32'd0;
    dmem[2140] = 32'd0;
    dmem[2141] = 32'd0;
    dmem[2142] = 32'd0;
    dmem[2143] = 32'd0;
    dmem[2144] = 32'd0;
    dmem[2145] = 32'd0;
    dmem[2146] = 32'd0;
    dmem[2147] = 32'd0;
    dmem[2148] = 32'd0;
    dmem[2149] = 32'd0;
    dmem[2150] = 32'd0;
    dmem[2151] = 32'd0;
    dmem[2152] = 32'd0;
    dmem[2153] = 32'd0;
    dmem[2154] = 32'd0;
    dmem[2155] = 32'd0;
    dmem[2156] = 32'd0;
    dmem[2157] = 32'd0;
    dmem[2158] = 32'd0;
    dmem[2159] = 32'd0;
    dmem[2160] = 32'd0;
    dmem[2161] = 32'd0;
    dmem[2162] = 32'd0;
    dmem[2163] = 32'd0;
    dmem[2164] = 32'd0;
    dmem[2165] = 32'd0;
    dmem[2166] = 32'd0;
    dmem[2167] = 32'd0;
    dmem[2168] = 32'd0;
    dmem[2169] = 32'd0;
    dmem[2170] = 32'd0;
    dmem[2171] = 32'd0;
    dmem[2172] = 32'd0;
    dmem[2173] = 32'd0;
    dmem[2174] = 32'd0;
    dmem[2175] = 32'd0;
    dmem[2176] = 32'd0;
    dmem[2177] = 32'd0;
    dmem[2178] = 32'd0;
    dmem[2179] = 32'd0;
    dmem[2180] = 32'd0;
    dmem[2181] = 32'd0;
    dmem[2182] = 32'd0;
    dmem[2183] = 32'd0;
    dmem[2184] = 32'd0;
    dmem[2185] = 32'd0;
    dmem[2186] = 32'd0;
    dmem[2187] = 32'd0;
    dmem[2188] = 32'd0;
    dmem[2189] = 32'd0;
    dmem[2190] = 32'd0;
    dmem[2191] = 32'd0;
    dmem[2192] = 32'd0;
    dmem[2193] = 32'd0;
    dmem[2194] = 32'd0;
    dmem[2195] = 32'd0;
    dmem[2196] = 32'd0;
    dmem[2197] = 32'd0;
    dmem[2198] = 32'd0;
    dmem[2199] = 32'd0;
    dmem[2200] = 32'd0;
    dmem[2201] = 32'd0;
    dmem[2202] = 32'd0;
    dmem[2203] = 32'd0;
    dmem[2204] = 32'd0;
    dmem[2205] = 32'd0;
    dmem[2206] = 32'd0;
    dmem[2207] = 32'd0;
    dmem[2208] = 32'd0;
    dmem[2209] = 32'd0;
    dmem[2210] = 32'd0;
    dmem[2211] = 32'd0;
    dmem[2212] = 32'd0;
    dmem[2213] = 32'd0;
    dmem[2214] = 32'd0;
    dmem[2215] = 32'd0;
    dmem[2216] = 32'd0;
    dmem[2217] = 32'd0;
    dmem[2218] = 32'd0;
    dmem[2219] = 32'd0;
    dmem[2220] = 32'd0;
    dmem[2221] = 32'd0;
    dmem[2222] = 32'd0;
    dmem[2223] = 32'd0;
    dmem[2224] = 32'd0;
    dmem[2225] = 32'd0;
    dmem[2226] = 32'd0;
    dmem[2227] = 32'd0;
    dmem[2228] = 32'd0;
    dmem[2229] = 32'd0;
    dmem[2230] = 32'd0;
    dmem[2231] = 32'd0;
    dmem[2232] = 32'd0;
    dmem[2233] = 32'd0;
    dmem[2234] = 32'd0;
    dmem[2235] = 32'd0;
    dmem[2236] = 32'd0;
    dmem[2237] = 32'd0;
    dmem[2238] = 32'd0;
    dmem[2239] = 32'd0;
    dmem[2240] = 32'd0;
    dmem[2241] = 32'd0;
    dmem[2242] = 32'd0;
    dmem[2243] = 32'd0;
    dmem[2244] = 32'd0;
    dmem[2245] = 32'd0;
    dmem[2246] = 32'd0;
    dmem[2247] = 32'd0;
    dmem[2248] = 32'd0;
    dmem[2249] = 32'd0;
    dmem[2250] = 32'd0;
    dmem[2251] = 32'd0;
    dmem[2252] = 32'd0;
    dmem[2253] = 32'd0;
    dmem[2254] = 32'd0;
    dmem[2255] = 32'd0;
    dmem[2256] = 32'd0;
    dmem[2257] = 32'd0;
    dmem[2258] = 32'd0;
    dmem[2259] = 32'd0;
    dmem[2260] = 32'd0;
    dmem[2261] = 32'd0;
    dmem[2262] = 32'd0;
    dmem[2263] = 32'd0;
    dmem[2264] = 32'd0;
    dmem[2265] = 32'd0;
    dmem[2266] = 32'd0;
    dmem[2267] = 32'd0;
    dmem[2268] = 32'd0;
    dmem[2269] = 32'd0;
    dmem[2270] = 32'd0;
    dmem[2271] = 32'd0;
    dmem[2272] = 32'd0;
    dmem[2273] = 32'd0;
    dmem[2274] = 32'd0;
    dmem[2275] = 32'd0;
    dmem[2276] = 32'd0;
    dmem[2277] = 32'd0;
    dmem[2278] = 32'd0;
    dmem[2279] = 32'd0;
    dmem[2280] = 32'd0;
    dmem[2281] = 32'd0;
    dmem[2282] = 32'd0;
    dmem[2283] = 32'd0;
    dmem[2284] = 32'd0;
    dmem[2285] = 32'd0;
    dmem[2286] = 32'd0;
    dmem[2287] = 32'd0;
    dmem[2288] = 32'd0;
    dmem[2289] = 32'd0;
    dmem[2290] = 32'd0;
    dmem[2291] = 32'd0;
    dmem[2292] = 32'd0;
    dmem[2293] = 32'd0;
    dmem[2294] = 32'd0;
    dmem[2295] = 32'd0;
    dmem[2296] = 32'd0;
    dmem[2297] = 32'd0;
    dmem[2298] = 32'd0;
    dmem[2299] = 32'd0;
    dmem[2300] = 32'd0;
    dmem[2301] = 32'd0;
    dmem[2302] = 32'd0;
    dmem[2303] = 32'd0;
    dmem[2304] = 32'd0;
    dmem[2305] = 32'd0;
    dmem[2306] = 32'd0;
    dmem[2307] = 32'd0;
    dmem[2308] = 32'd0;
    dmem[2309] = 32'd0;
    dmem[2310] = 32'd0;
    dmem[2311] = 32'd0;
    dmem[2312] = 32'd0;
    dmem[2313] = 32'd0;
    dmem[2314] = 32'd0;
    dmem[2315] = 32'd0;
    dmem[2316] = 32'd0;
    dmem[2317] = 32'd0;
    dmem[2318] = 32'd0;
    dmem[2319] = 32'd0;
    dmem[2320] = 32'd0;
    dmem[2321] = 32'd0;
    dmem[2322] = 32'd0;
    dmem[2323] = 32'd0;
    dmem[2324] = 32'd0;
    dmem[2325] = 32'd0;
    dmem[2326] = 32'd0;
    dmem[2327] = 32'd0;
    dmem[2328] = 32'd0;
    dmem[2329] = 32'd0;
    dmem[2330] = 32'd0;
    dmem[2331] = 32'd0;
    dmem[2332] = 32'd0;
    dmem[2333] = 32'd0;
    dmem[2334] = 32'd0;
    dmem[2335] = 32'd0;
    dmem[2336] = 32'd0;
    dmem[2337] = 32'd0;
    dmem[2338] = 32'd0;
    dmem[2339] = 32'd0;
    dmem[2340] = 32'd0;
    dmem[2341] = 32'd0;
    dmem[2342] = 32'd0;
    dmem[2343] = 32'd0;
    dmem[2344] = 32'd0;
    dmem[2345] = 32'd0;
    dmem[2346] = 32'd0;
    dmem[2347] = 32'd0;
    dmem[2348] = 32'd0;
    dmem[2349] = 32'd0;
    dmem[2350] = 32'd0;
    dmem[2351] = 32'd0;
    dmem[2352] = 32'd0;
    dmem[2353] = 32'd0;
    dmem[2354] = 32'd0;
    dmem[2355] = 32'd0;
    dmem[2356] = 32'd0;
    dmem[2357] = 32'd0;
    dmem[2358] = 32'd0;
    dmem[2359] = 32'd0;
    dmem[2360] = 32'd0;
    dmem[2361] = 32'd0;
    dmem[2362] = 32'd0;
    dmem[2363] = 32'd0;
    dmem[2364] = 32'd0;
    dmem[2365] = 32'd0;
    dmem[2366] = 32'd0;
    dmem[2367] = 32'd0;
    dmem[2368] = 32'd0;
    dmem[2369] = 32'd0;
    dmem[2370] = 32'd0;
    dmem[2371] = 32'd0;
    dmem[2372] = 32'd0;
    dmem[2373] = 32'd0;
    dmem[2374] = 32'd0;
    dmem[2375] = 32'd0;
    dmem[2376] = 32'd0;
    dmem[2377] = 32'd0;
    dmem[2378] = 32'd0;
    dmem[2379] = 32'd0;
    dmem[2380] = 32'd0;
    dmem[2381] = 32'd0;
    dmem[2382] = 32'd0;
    dmem[2383] = 32'd0;
    dmem[2384] = 32'd0;
    dmem[2385] = 32'd0;
    dmem[2386] = 32'd0;
    dmem[2387] = 32'd0;
    dmem[2388] = 32'd0;
    dmem[2389] = 32'd0;
    dmem[2390] = 32'd0;
    dmem[2391] = 32'd0;
    dmem[2392] = 32'd0;
    dmem[2393] = 32'd0;
    dmem[2394] = 32'd0;
    dmem[2395] = 32'd0;
    dmem[2396] = 32'd0;
    dmem[2397] = 32'd0;
    dmem[2398] = 32'd0;
    dmem[2399] = 32'd0;
    dmem[2400] = 32'd0;
    dmem[2401] = 32'd0;
    dmem[2402] = 32'd0;
    dmem[2403] = 32'd0;
    dmem[2404] = 32'd0;
    dmem[2405] = 32'd0;
    dmem[2406] = 32'd0;
    dmem[2407] = 32'd0;
    dmem[2408] = 32'd0;
    dmem[2409] = 32'd0;
    dmem[2410] = 32'd0;
    dmem[2411] = 32'd0;
    dmem[2412] = 32'd0;
    dmem[2413] = 32'd0;
    dmem[2414] = 32'd0;
    dmem[2415] = 32'd0;
    dmem[2416] = 32'd0;
    dmem[2417] = 32'd0;
    dmem[2418] = 32'd0;
    dmem[2419] = 32'd0;
    dmem[2420] = 32'd0;
    dmem[2421] = 32'd0;
    dmem[2422] = 32'd0;
    dmem[2423] = 32'd0;
    dmem[2424] = 32'd0;
    dmem[2425] = 32'd0;
    dmem[2426] = 32'd0;
    dmem[2427] = 32'd0;
    dmem[2428] = 32'd0;
    dmem[2429] = 32'd0;
    dmem[2430] = 32'd0;
    dmem[2431] = 32'd0;
    dmem[2432] = 32'd0;
    dmem[2433] = 32'd0;
    dmem[2434] = 32'd0;
    dmem[2435] = 32'd0;
    dmem[2436] = 32'd0;
    dmem[2437] = 32'd0;
    dmem[2438] = 32'd0;
    dmem[2439] = 32'd0;
    dmem[2440] = 32'd0;
    dmem[2441] = 32'd0;
    dmem[2442] = 32'd0;
    dmem[2443] = 32'd0;
    dmem[2444] = 32'd0;
    dmem[2445] = 32'd0;
    dmem[2446] = 32'd0;
    dmem[2447] = 32'd0;
    dmem[2448] = 32'd0;
    dmem[2449] = 32'd0;
    dmem[2450] = 32'd0;
    dmem[2451] = 32'd0;
    dmem[2452] = 32'd0;
    dmem[2453] = 32'd0;
    dmem[2454] = 32'd0;
    dmem[2455] = 32'd0;
    dmem[2456] = 32'd0;
    dmem[2457] = 32'd0;
    dmem[2458] = 32'd0;
    dmem[2459] = 32'd0;
    dmem[2460] = 32'd0;
    dmem[2461] = 32'd0;
    dmem[2462] = 32'd0;
    dmem[2463] = 32'd0;
    dmem[2464] = 32'd0;
    dmem[2465] = 32'd0;
    dmem[2466] = 32'd0;
    dmem[2467] = 32'd0;
    dmem[2468] = 32'd0;
    dmem[2469] = 32'd0;
    dmem[2470] = 32'd0;
    dmem[2471] = 32'd0;
    dmem[2472] = 32'd0;
    dmem[2473] = 32'd0;
    dmem[2474] = 32'd0;
    dmem[2475] = 32'd0;
    dmem[2476] = 32'd0;
    dmem[2477] = 32'd0;
    dmem[2478] = 32'd0;
    dmem[2479] = 32'd0;
    dmem[2480] = 32'd0;
    dmem[2481] = 32'd0;
    dmem[2482] = 32'd0;
    dmem[2483] = 32'd0;
    dmem[2484] = 32'd0;
    dmem[2485] = 32'd0;
    dmem[2486] = 32'd0;
    dmem[2487] = 32'd0;
    dmem[2488] = 32'd0;
    dmem[2489] = 32'd0;
    dmem[2490] = 32'd0;
    dmem[2491] = 32'd0;
    dmem[2492] = 32'd0;
    dmem[2493] = 32'd0;
    dmem[2494] = 32'd0;
    dmem[2495] = 32'd0;
    dmem[2496] = 32'd0;
    dmem[2497] = 32'd0;
    dmem[2498] = 32'd0;
    dmem[2499] = 32'd0;
    dmem[2500] = 32'd0;
    dmem[2501] = 32'd0;
    dmem[2502] = 32'd0;
    dmem[2503] = 32'd0;
    dmem[2504] = 32'd0;
    dmem[2505] = 32'd0;
    dmem[2506] = 32'd0;
    dmem[2507] = 32'd0;
    dmem[2508] = 32'd0;
    dmem[2509] = 32'd0;
    dmem[2510] = 32'd0;
    dmem[2511] = 32'd0;
    dmem[2512] = 32'd0;
    dmem[2513] = 32'd0;
    dmem[2514] = 32'd0;
    dmem[2515] = 32'd0;
    dmem[2516] = 32'd0;
    dmem[2517] = 32'd0;
    dmem[2518] = 32'd0;
    dmem[2519] = 32'd0;
    dmem[2520] = 32'd0;
    dmem[2521] = 32'd0;
    dmem[2522] = 32'd0;
    dmem[2523] = 32'd0;
    dmem[2524] = 32'd0;
    dmem[2525] = 32'd0;
    dmem[2526] = 32'd0;
    dmem[2527] = 32'd0;
    dmem[2528] = 32'd0;
    dmem[2529] = 32'd0;
    dmem[2530] = 32'd0;
    dmem[2531] = 32'd0;
    dmem[2532] = 32'd0;
    dmem[2533] = 32'd0;
    dmem[2534] = 32'd0;
    dmem[2535] = 32'd0;
    dmem[2536] = 32'd0;
    dmem[2537] = 32'd0;
    dmem[2538] = 32'd0;
    dmem[2539] = 32'd0;
    dmem[2540] = 32'd0;
    dmem[2541] = 32'd0;
    dmem[2542] = 32'd0;
    dmem[2543] = 32'd0;
    dmem[2544] = 32'd0;
    dmem[2545] = 32'd0;
    dmem[2546] = 32'd0;
    dmem[2547] = 32'd0;
    dmem[2548] = 32'd0;
    dmem[2549] = 32'd0;
    dmem[2550] = 32'd0;
    dmem[2551] = 32'd0;
    dmem[2552] = 32'd0;
    dmem[2553] = 32'd0;
    dmem[2554] = 32'd0;
    dmem[2555] = 32'd0;
    dmem[2556] = 32'd0;
    dmem[2557] = 32'd0;
    dmem[2558] = 32'd0;
    dmem[2559] = 32'd0;
    dmem[2560] = 32'd0;
    dmem[2561] = 32'd0;
    dmem[2562] = 32'd0;
    dmem[2563] = 32'd0;
    dmem[2564] = 32'd0;
    dmem[2565] = 32'd0;
    dmem[2566] = 32'd0;
    dmem[2567] = 32'd0;
    dmem[2568] = 32'd0;
    dmem[2569] = 32'd0;
    dmem[2570] = 32'd0;
    dmem[2571] = 32'd0;
    dmem[2572] = 32'd0;
    dmem[2573] = 32'd0;
    dmem[2574] = 32'd0;
    dmem[2575] = 32'd0;
    dmem[2576] = 32'd0;
    dmem[2577] = 32'd0;
    dmem[2578] = 32'd0;
    dmem[2579] = 32'd0;
    dmem[2580] = 32'd0;
    dmem[2581] = 32'd0;
    dmem[2582] = 32'd0;
    dmem[2583] = 32'd0;
    dmem[2584] = 32'd0;
    dmem[2585] = 32'd0;
    dmem[2586] = 32'd0;
    dmem[2587] = 32'd0;
    dmem[2588] = 32'd0;
    dmem[2589] = 32'd0;
    dmem[2590] = 32'd0;
    dmem[2591] = 32'd0;
    dmem[2592] = 32'd0;
    dmem[2593] = 32'd0;
    dmem[2594] = 32'd0;
    dmem[2595] = 32'd0;
    dmem[2596] = 32'd0;
    dmem[2597] = 32'd0;
    dmem[2598] = 32'd0;
    dmem[2599] = 32'd0;
    dmem[2600] = 32'd0;
    dmem[2601] = 32'd0;
    dmem[2602] = 32'd0;
    dmem[2603] = 32'd0;
    dmem[2604] = 32'd0;
    dmem[2605] = 32'd0;
    dmem[2606] = 32'd0;
    dmem[2607] = 32'd0;
    dmem[2608] = 32'd0;
    dmem[2609] = 32'd0;
    dmem[2610] = 32'd0;
    dmem[2611] = 32'd0;
    dmem[2612] = 32'd0;
    dmem[2613] = 32'd0;
    dmem[2614] = 32'd0;
    dmem[2615] = 32'd0;
    dmem[2616] = 32'd0;
    dmem[2617] = 32'd0;
    dmem[2618] = 32'd0;
    dmem[2619] = 32'd0;
    dmem[2620] = 32'd0;
    dmem[2621] = 32'd0;
    dmem[2622] = 32'd0;
    dmem[2623] = 32'd0;
    dmem[2624] = 32'd0;
    dmem[2625] = 32'd0;
    dmem[2626] = 32'd0;
    dmem[2627] = 32'd0;
    dmem[2628] = 32'd0;
    dmem[2629] = 32'd0;
    dmem[2630] = 32'd0;
    dmem[2631] = 32'd0;
    dmem[2632] = 32'd0;
    dmem[2633] = 32'd0;
    dmem[2634] = 32'd0;
    dmem[2635] = 32'd0;
    dmem[2636] = 32'd0;
    dmem[2637] = 32'd0;
    dmem[2638] = 32'd0;
    dmem[2639] = 32'd0;
    dmem[2640] = 32'd0;
    dmem[2641] = 32'd0;
    dmem[2642] = 32'd0;
    dmem[2643] = 32'd0;
    dmem[2644] = 32'd0;
    dmem[2645] = 32'd0;
    dmem[2646] = 32'd0;
    dmem[2647] = 32'd0;
    dmem[2648] = 32'd0;
    dmem[2649] = 32'd0;
    dmem[2650] = 32'd0;
    dmem[2651] = 32'd0;
    dmem[2652] = 32'd0;
    dmem[2653] = 32'd0;
    dmem[2654] = 32'd0;
    dmem[2655] = 32'd0;
    dmem[2656] = 32'd0;
    dmem[2657] = 32'd0;
    dmem[2658] = 32'd0;
    dmem[2659] = 32'd0;
    dmem[2660] = 32'd0;
    dmem[2661] = 32'd0;
    dmem[2662] = 32'd0;
    dmem[2663] = 32'd0;
    dmem[2664] = 32'd0;
    dmem[2665] = 32'd0;
    dmem[2666] = 32'd0;
    dmem[2667] = 32'd0;
    dmem[2668] = 32'd0;
    dmem[2669] = 32'd0;
    dmem[2670] = 32'd0;
    dmem[2671] = 32'd0;
    dmem[2672] = 32'd0;
    dmem[2673] = 32'd0;
    dmem[2674] = 32'd0;
    dmem[2675] = 32'd0;
    dmem[2676] = 32'd0;
    dmem[2677] = 32'd0;
    dmem[2678] = 32'd0;
    dmem[2679] = 32'd0;
    dmem[2680] = 32'd0;
    dmem[2681] = 32'd0;
    dmem[2682] = 32'd0;
    dmem[2683] = 32'd0;
    dmem[2684] = 32'd0;
    dmem[2685] = 32'd0;
    dmem[2686] = 32'd0;
    dmem[2687] = 32'd0;
    dmem[2688] = 32'd0;
    dmem[2689] = 32'd0;
    dmem[2690] = 32'd0;
    dmem[2691] = 32'd0;
    dmem[2692] = 32'd0;
    dmem[2693] = 32'd0;
    dmem[2694] = 32'd0;
    dmem[2695] = 32'd0;
    dmem[2696] = 32'd0;
    dmem[2697] = 32'd0;
    dmem[2698] = 32'd0;
    dmem[2699] = 32'd0;
    dmem[2700] = 32'd0;
    dmem[2701] = 32'd0;
    dmem[2702] = 32'd0;
    dmem[2703] = 32'd0;
    dmem[2704] = 32'd0;
    dmem[2705] = 32'd0;
    dmem[2706] = 32'd0;
    dmem[2707] = 32'd0;
    dmem[2708] = 32'd0;
    dmem[2709] = 32'd0;
    dmem[2710] = 32'd0;
    dmem[2711] = 32'd0;
    dmem[2712] = 32'd0;
    dmem[2713] = 32'd0;
    dmem[2714] = 32'd0;
    dmem[2715] = 32'd0;
    dmem[2716] = 32'd0;
    dmem[2717] = 32'd0;
    dmem[2718] = 32'd0;
    dmem[2719] = 32'd0;
    dmem[2720] = 32'd0;
    dmem[2721] = 32'd0;
    dmem[2722] = 32'd0;
    dmem[2723] = 32'd0;
    dmem[2724] = 32'd0;
    dmem[2725] = 32'd0;
    dmem[2726] = 32'd0;
    dmem[2727] = 32'd0;
    dmem[2728] = 32'd0;
    dmem[2729] = 32'd0;
    dmem[2730] = 32'd0;
    dmem[2731] = 32'd0;
    dmem[2732] = 32'd0;
    dmem[2733] = 32'd0;
    dmem[2734] = 32'd0;
    dmem[2735] = 32'd0;
    dmem[2736] = 32'd0;
    dmem[2737] = 32'd0;
    dmem[2738] = 32'd0;
    dmem[2739] = 32'd0;
    dmem[2740] = 32'd0;
    dmem[2741] = 32'd0;
    dmem[2742] = 32'd0;
    dmem[2743] = 32'd0;
    dmem[2744] = 32'd0;
    dmem[2745] = 32'd0;
    dmem[2746] = 32'd0;
    dmem[2747] = 32'd0;
    dmem[2748] = 32'd0;
    dmem[2749] = 32'd0;
    dmem[2750] = 32'd0;
    dmem[2751] = 32'd0;
    dmem[2752] = 32'd0;
    dmem[2753] = 32'd0;
    dmem[2754] = 32'd0;
    dmem[2755] = 32'd0;
    dmem[2756] = 32'd0;
    dmem[2757] = 32'd0;
    dmem[2758] = 32'd0;
    dmem[2759] = 32'd0;
    dmem[2760] = 32'd0;
    dmem[2761] = 32'd0;
    dmem[2762] = 32'd0;
    dmem[2763] = 32'd0;
    dmem[2764] = 32'd0;
    dmem[2765] = 32'd0;
    dmem[2766] = 32'd0;
    dmem[2767] = 32'd0;
    dmem[2768] = 32'd0;
    dmem[2769] = 32'd0;
    dmem[2770] = 32'd0;
    dmem[2771] = 32'd0;
    dmem[2772] = 32'd0;
    dmem[2773] = 32'd0;
    dmem[2774] = 32'd0;
    dmem[2775] = 32'd0;
    dmem[2776] = 32'd0;
    dmem[2777] = 32'd0;
    dmem[2778] = 32'd0;
    dmem[2779] = 32'd0;
    dmem[2780] = 32'd0;
    dmem[2781] = 32'd0;
    dmem[2782] = 32'd0;
    dmem[2783] = 32'd0;
    dmem[2784] = 32'd0;
    dmem[2785] = 32'd0;
    dmem[2786] = 32'd0;
    dmem[2787] = 32'd0;
    dmem[2788] = 32'd0;
    dmem[2789] = 32'd0;
    dmem[2790] = 32'd0;
    dmem[2791] = 32'd0;
    dmem[2792] = 32'd0;
    dmem[2793] = 32'd0;
    dmem[2794] = 32'd0;
    dmem[2795] = 32'd0;
    dmem[2796] = 32'd0;
    dmem[2797] = 32'd0;
    dmem[2798] = 32'd0;
    dmem[2799] = 32'd0;
    dmem[2800] = 32'd0;
    dmem[2801] = 32'd0;
    dmem[2802] = 32'd0;
    dmem[2803] = 32'd0;
    dmem[2804] = 32'd0;
    dmem[2805] = 32'd0;
    dmem[2806] = 32'd0;
    dmem[2807] = 32'd0;
    dmem[2808] = 32'd0;
    dmem[2809] = 32'd0;
    dmem[2810] = 32'd0;
    dmem[2811] = 32'd0;
    dmem[2812] = 32'd0;
    dmem[2813] = 32'd0;
    dmem[2814] = 32'd0;
    dmem[2815] = 32'd0;
    dmem[2816] = 32'd0;
    dmem[2817] = 32'd0;
    dmem[2818] = 32'd0;
    dmem[2819] = 32'd0;
    dmem[2820] = 32'd0;
    dmem[2821] = 32'd0;
    dmem[2822] = 32'd0;
    dmem[2823] = 32'd0;
    dmem[2824] = 32'd0;
    dmem[2825] = 32'd0;
    dmem[2826] = 32'd0;
    dmem[2827] = 32'd0;
    dmem[2828] = 32'd0;
    dmem[2829] = 32'd0;
    dmem[2830] = 32'd0;
    dmem[2831] = 32'd0;
    dmem[2832] = 32'd0;
    dmem[2833] = 32'd0;
    dmem[2834] = 32'd0;
    dmem[2835] = 32'd0;
    dmem[2836] = 32'd0;
    dmem[2837] = 32'd0;
    dmem[2838] = 32'd0;
    dmem[2839] = 32'd0;
    dmem[2840] = 32'd0;
    dmem[2841] = 32'd0;
    dmem[2842] = 32'd0;
    dmem[2843] = 32'd0;
    dmem[2844] = 32'd0;
    dmem[2845] = 32'd0;
    dmem[2846] = 32'd0;
    dmem[2847] = 32'd0;
    dmem[2848] = 32'd0;
    dmem[2849] = 32'd0;
    dmem[2850] = 32'd0;
    dmem[2851] = 32'd0;
    dmem[2852] = 32'd0;
    dmem[2853] = 32'd0;
    dmem[2854] = 32'd0;
    dmem[2855] = 32'd0;
    dmem[2856] = 32'd0;
    dmem[2857] = 32'd0;
    dmem[2858] = 32'd0;
    dmem[2859] = 32'd0;
    dmem[2860] = 32'd0;
    dmem[2861] = 32'd0;
    dmem[2862] = 32'd0;
    dmem[2863] = 32'd0;
    dmem[2864] = 32'd0;
    dmem[2865] = 32'd0;
    dmem[2866] = 32'd0;
    dmem[2867] = 32'd0;
    dmem[2868] = 32'd0;
    dmem[2869] = 32'd0;
    dmem[2870] = 32'd0;
    dmem[2871] = 32'd0;
    dmem[2872] = 32'd0;
    dmem[2873] = 32'd0;
    dmem[2874] = 32'd0;
    dmem[2875] = 32'd0;
    dmem[2876] = 32'd0;
    dmem[2877] = 32'd0;
    dmem[2878] = 32'd0;
    dmem[2879] = 32'd0;
    dmem[2880] = 32'd0;
    dmem[2881] = 32'd0;
    dmem[2882] = 32'd0;
    dmem[2883] = 32'd0;
    dmem[2884] = 32'd0;
    dmem[2885] = 32'd0;
    dmem[2886] = 32'd0;
    dmem[2887] = 32'd0;
    dmem[2888] = 32'd0;
    dmem[2889] = 32'd0;
    dmem[2890] = 32'd0;
    dmem[2891] = 32'd0;
    dmem[2892] = 32'd0;
    dmem[2893] = 32'd0;
    dmem[2894] = 32'd0;
    dmem[2895] = 32'd0;
    dmem[2896] = 32'd0;
    dmem[2897] = 32'd0;
    dmem[2898] = 32'd0;
    dmem[2899] = 32'd0;
    dmem[2900] = 32'd0;
    dmem[2901] = 32'd0;
    dmem[2902] = 32'd0;
    dmem[2903] = 32'd0;
    dmem[2904] = 32'd0;
    dmem[2905] = 32'd0;
    dmem[2906] = 32'd0;
    dmem[2907] = 32'd0;
    dmem[2908] = 32'd0;
    dmem[2909] = 32'd0;
    dmem[2910] = 32'd0;
    dmem[2911] = 32'd0;
    dmem[2912] = 32'd0;
    dmem[2913] = 32'd0;
    dmem[2914] = 32'd0;
    dmem[2915] = 32'd0;
    dmem[2916] = 32'd0;
    dmem[2917] = 32'd0;
    dmem[2918] = 32'd0;
    dmem[2919] = 32'd0;
    dmem[2920] = 32'd0;
    dmem[2921] = 32'd0;
    dmem[2922] = 32'd0;
    dmem[2923] = 32'd0;
    dmem[2924] = 32'd0;
    dmem[2925] = 32'd0;
    dmem[2926] = 32'd0;
    dmem[2927] = 32'd0;
    dmem[2928] = 32'd0;
    dmem[2929] = 32'd0;
    dmem[2930] = 32'd0;
    dmem[2931] = 32'd0;
    dmem[2932] = 32'd0;
    dmem[2933] = 32'd0;
    dmem[2934] = 32'd0;
    dmem[2935] = 32'd0;
    dmem[2936] = 32'd0;
    dmem[2937] = 32'd0;
    dmem[2938] = 32'd0;
    dmem[2939] = 32'd0;
    dmem[2940] = 32'd0;
    dmem[2941] = 32'd0;
    dmem[2942] = 32'd0;
    dmem[2943] = 32'd0;
    dmem[2944] = 32'd0;
    dmem[2945] = 32'd0;
    dmem[2946] = 32'd0;
    dmem[2947] = 32'd0;
    dmem[2948] = 32'd0;
    dmem[2949] = 32'd0;
    dmem[2950] = 32'd0;
    dmem[2951] = 32'd0;
    dmem[2952] = 32'd0;
    dmem[2953] = 32'd0;
    dmem[2954] = 32'd0;
    dmem[2955] = 32'd0;
    dmem[2956] = 32'd0;
    dmem[2957] = 32'd0;
    dmem[2958] = 32'd0;
    dmem[2959] = 32'd0;
    dmem[2960] = 32'd0;
    dmem[2961] = 32'd0;
    dmem[2962] = 32'd0;
    dmem[2963] = 32'd0;
    dmem[2964] = 32'd0;
    dmem[2965] = 32'd0;
    dmem[2966] = 32'd0;
    dmem[2967] = 32'd0;
    dmem[2968] = 32'd0;
    dmem[2969] = 32'd0;
    dmem[2970] = 32'd0;
    dmem[2971] = 32'd0;
    dmem[2972] = 32'd0;
    dmem[2973] = 32'd0;
    dmem[2974] = 32'd0;
    dmem[2975] = 32'd0;
    dmem[2976] = 32'd0;
    dmem[2977] = 32'd0;
    dmem[2978] = 32'd0;
    dmem[2979] = 32'd0;
    dmem[2980] = 32'd0;
    dmem[2981] = 32'd0;
    dmem[2982] = 32'd0;
    dmem[2983] = 32'd0;
    dmem[2984] = 32'd0;
    dmem[2985] = 32'd0;
    dmem[2986] = 32'd0;
    dmem[2987] = 32'd0;
    dmem[2988] = 32'd0;
    dmem[2989] = 32'd0;
    dmem[2990] = 32'd0;
    dmem[2991] = 32'd0;
    dmem[2992] = 32'd0;
    dmem[2993] = 32'd0;
    dmem[2994] = 32'd0;
    dmem[2995] = 32'd0;
    dmem[2996] = 32'd0;
    dmem[2997] = 32'd0;
    dmem[2998] = 32'd0;
    dmem[2999] = 32'd0;
    dmem[3000] = 32'd0;
    dmem[3001] = 32'd0;
    dmem[3002] = 32'd0;
    dmem[3003] = 32'd0;
    dmem[3004] = 32'd0;
    dmem[3005] = 32'd0;
    dmem[3006] = 32'd0;
    dmem[3007] = 32'd0;
    dmem[3008] = 32'd0;
    dmem[3009] = 32'd0;
    dmem[3010] = 32'd0;
    dmem[3011] = 32'd0;
    dmem[3012] = 32'd0;
    dmem[3013] = 32'd0;
    dmem[3014] = 32'd0;
    dmem[3015] = 32'd0;
    dmem[3016] = 32'd0;
    dmem[3017] = 32'd0;
    dmem[3018] = 32'd0;
    dmem[3019] = 32'd0;
    dmem[3020] = 32'd0;
    dmem[3021] = 32'd0;
    dmem[3022] = 32'd0;
    dmem[3023] = 32'd0;
    dmem[3024] = 32'd0;
    dmem[3025] = 32'd0;
    dmem[3026] = 32'd0;
    dmem[3027] = 32'd0;
    dmem[3028] = 32'd0;
    dmem[3029] = 32'd0;
    dmem[3030] = 32'd0;
    dmem[3031] = 32'd0;
    dmem[3032] = 32'd0;
    dmem[3033] = 32'd0;
    dmem[3034] = 32'd0;
    dmem[3035] = 32'd0;
    dmem[3036] = 32'd0;
    dmem[3037] = 32'd0;
    dmem[3038] = 32'd0;
    dmem[3039] = 32'd0;
    dmem[3040] = 32'd0;
    dmem[3041] = 32'd0;
    dmem[3042] = 32'd0;
    dmem[3043] = 32'd0;
    dmem[3044] = 32'd0;
    dmem[3045] = 32'd0;
    dmem[3046] = 32'd0;
    dmem[3047] = 32'd0;
    dmem[3048] = 32'd0;
    dmem[3049] = 32'd0;
    dmem[3050] = 32'd0;
    dmem[3051] = 32'd0;
    dmem[3052] = 32'd0;
    dmem[3053] = 32'd0;
    dmem[3054] = 32'd0;
    dmem[3055] = 32'd0;
    dmem[3056] = 32'd0;
    dmem[3057] = 32'd0;
    dmem[3058] = 32'd0;
    dmem[3059] = 32'd0;
    dmem[3060] = 32'd0;
    dmem[3061] = 32'd0;
    dmem[3062] = 32'd0;
    dmem[3063] = 32'd0;
    dmem[3064] = 32'd0;
    dmem[3065] = 32'd0;
    dmem[3066] = 32'd0;
    dmem[3067] = 32'd0;
    dmem[3068] = 32'd0;
    dmem[3069] = 32'd0;
    dmem[3070] = 32'd0;
    dmem[3071] = 32'd0;
    dmem[3072] = 32'd0;
    dmem[3073] = 32'd0;
    dmem[3074] = 32'd0;
    dmem[3075] = 32'd0;
    dmem[3076] = 32'd0;
    dmem[3077] = 32'd0;
    dmem[3078] = 32'd0;
    dmem[3079] = 32'd0;
    dmem[3080] = 32'd0;
    dmem[3081] = 32'd0;
    dmem[3082] = 32'd0;
    dmem[3083] = 32'd0;
    dmem[3084] = 32'd0;
    dmem[3085] = 32'd0;
    dmem[3086] = 32'd0;
    dmem[3087] = 32'd0;
    dmem[3088] = 32'd0;
    dmem[3089] = 32'd0;
    dmem[3090] = 32'd0;
    dmem[3091] = 32'd0;
    dmem[3092] = 32'd0;
    dmem[3093] = 32'd0;
    dmem[3094] = 32'd0;
    dmem[3095] = 32'd0;
    dmem[3096] = 32'd0;
    dmem[3097] = 32'd0;
    dmem[3098] = 32'd0;
    dmem[3099] = 32'd0;
    dmem[3100] = 32'd0;
    dmem[3101] = 32'd0;
    dmem[3102] = 32'd0;
    dmem[3103] = 32'd0;
    dmem[3104] = 32'd0;
    dmem[3105] = 32'd0;
    dmem[3106] = 32'd0;
    dmem[3107] = 32'd0;
    dmem[3108] = 32'd0;
    dmem[3109] = 32'd0;
    dmem[3110] = 32'd0;
    dmem[3111] = 32'd0;
    dmem[3112] = 32'd0;
    dmem[3113] = 32'd0;
    dmem[3114] = 32'd0;
    dmem[3115] = 32'd0;
    dmem[3116] = 32'd0;
    dmem[3117] = 32'd0;
    dmem[3118] = 32'd0;
    dmem[3119] = 32'd0;
    dmem[3120] = 32'd0;
    dmem[3121] = 32'd0;
    dmem[3122] = 32'd0;
    dmem[3123] = 32'd0;
    dmem[3124] = 32'd0;
    dmem[3125] = 32'd0;
    dmem[3126] = 32'd0;
    dmem[3127] = 32'd0;
    dmem[3128] = 32'd0;
    dmem[3129] = 32'd0;
    dmem[3130] = 32'd0;
    dmem[3131] = 32'd0;
    dmem[3132] = 32'd0;
    dmem[3133] = 32'd0;
    dmem[3134] = 32'd0;
    dmem[3135] = 32'd0;
    dmem[3136] = 32'd0;
    dmem[3137] = 32'd0;
    dmem[3138] = 32'd0;
    dmem[3139] = 32'd0;
    dmem[3140] = 32'd0;
    dmem[3141] = 32'd0;
    dmem[3142] = 32'd0;
    dmem[3143] = 32'd0;
    dmem[3144] = 32'd0;
    dmem[3145] = 32'd0;
    dmem[3146] = 32'd0;
    dmem[3147] = 32'd0;
    dmem[3148] = 32'd0;
    dmem[3149] = 32'd0;
    dmem[3150] = 32'd0;
    dmem[3151] = 32'd0;
    dmem[3152] = 32'd0;
    dmem[3153] = 32'd0;
    dmem[3154] = 32'd0;
    dmem[3155] = 32'd0;
    dmem[3156] = 32'd0;
    dmem[3157] = 32'd0;
    dmem[3158] = 32'd0;
    dmem[3159] = 32'd0;
    dmem[3160] = 32'd0;
    dmem[3161] = 32'd0;
    dmem[3162] = 32'd0;
    dmem[3163] = 32'd0;
    dmem[3164] = 32'd0;
    dmem[3165] = 32'd0;
    dmem[3166] = 32'd0;
    dmem[3167] = 32'd0;
    dmem[3168] = 32'd0;
    dmem[3169] = 32'd0;
    dmem[3170] = 32'd0;
    dmem[3171] = 32'd0;
    dmem[3172] = 32'd0;
    dmem[3173] = 32'd0;
    dmem[3174] = 32'd0;
    dmem[3175] = 32'd0;
    dmem[3176] = 32'd0;
    dmem[3177] = 32'd0;
    dmem[3178] = 32'd0;
    dmem[3179] = 32'd0;
    dmem[3180] = 32'd0;
    dmem[3181] = 32'd0;
    dmem[3182] = 32'd0;
    dmem[3183] = 32'd0;
    dmem[3184] = 32'd0;
    dmem[3185] = 32'd0;
    dmem[3186] = 32'd0;
    dmem[3187] = 32'd0;
    dmem[3188] = 32'd0;
    dmem[3189] = 32'd0;
    dmem[3190] = 32'd0;
    dmem[3191] = 32'd0;
    dmem[3192] = 32'd0;
    dmem[3193] = 32'd0;
    dmem[3194] = 32'd0;
    dmem[3195] = 32'd0;
    dmem[3196] = 32'd0;
    dmem[3197] = 32'd0;
    dmem[3198] = 32'd0;
    dmem[3199] = 32'd0;
    dmem[3200] = 32'd0;
    dmem[3201] = 32'd0;
    dmem[3202] = 32'd0;
    dmem[3203] = 32'd0;
    dmem[3204] = 32'd0;
    dmem[3205] = 32'd0;
    dmem[3206] = 32'd0;
    dmem[3207] = 32'd0;
    dmem[3208] = 32'd0;
    dmem[3209] = 32'd0;
    dmem[3210] = 32'd0;
    dmem[3211] = 32'd0;
    dmem[3212] = 32'd0;
    dmem[3213] = 32'd0;
    dmem[3214] = 32'd0;
    dmem[3215] = 32'd0;
    dmem[3216] = 32'd0;
    dmem[3217] = 32'd0;
    dmem[3218] = 32'd0;
    dmem[3219] = 32'd0;
    dmem[3220] = 32'd0;
    dmem[3221] = 32'd0;
    dmem[3222] = 32'd0;
    dmem[3223] = 32'd0;
    dmem[3224] = 32'd0;
    dmem[3225] = 32'd0;
    dmem[3226] = 32'd0;
    dmem[3227] = 32'd0;
    dmem[3228] = 32'd0;
    dmem[3229] = 32'd0;
    dmem[3230] = 32'd0;
    dmem[3231] = 32'd0;
    dmem[3232] = 32'd0;
    dmem[3233] = 32'd0;
    dmem[3234] = 32'd0;
    dmem[3235] = 32'd0;
    dmem[3236] = 32'd0;
    dmem[3237] = 32'd0;
    dmem[3238] = 32'd0;
    dmem[3239] = 32'd0;
    dmem[3240] = 32'd0;
    dmem[3241] = 32'd0;
    dmem[3242] = 32'd0;
    dmem[3243] = 32'd0;
    dmem[3244] = 32'd0;
    dmem[3245] = 32'd0;
    dmem[3246] = 32'd0;
    dmem[3247] = 32'd0;
    dmem[3248] = 32'd0;
    dmem[3249] = 32'd0;
    dmem[3250] = 32'd0;
    dmem[3251] = 32'd0;
    dmem[3252] = 32'd0;
    dmem[3253] = 32'd0;
    dmem[3254] = 32'd0;
    dmem[3255] = 32'd0;
    dmem[3256] = 32'd0;
    dmem[3257] = 32'd0;
    dmem[3258] = 32'd0;
    dmem[3259] = 32'd0;
    dmem[3260] = 32'd0;
    dmem[3261] = 32'd0;
    dmem[3262] = 32'd0;
    dmem[3263] = 32'd0;
    dmem[3264] = 32'd0;
    dmem[3265] = 32'd0;
    dmem[3266] = 32'd0;
    dmem[3267] = 32'd0;
    dmem[3268] = 32'd0;
    dmem[3269] = 32'd0;
    dmem[3270] = 32'd0;
    dmem[3271] = 32'd0;
    dmem[3272] = 32'd0;
    dmem[3273] = 32'd0;
    dmem[3274] = 32'd0;
    dmem[3275] = 32'd0;
    dmem[3276] = 32'd0;
    dmem[3277] = 32'd0;
    dmem[3278] = 32'd0;
    dmem[3279] = 32'd0;
    dmem[3280] = 32'd0;
    dmem[3281] = 32'd0;
    dmem[3282] = 32'd0;
    dmem[3283] = 32'd0;
    dmem[3284] = 32'd0;
    dmem[3285] = 32'd0;
    dmem[3286] = 32'd0;
    dmem[3287] = 32'd0;
    dmem[3288] = 32'd0;
    dmem[3289] = 32'd0;
    dmem[3290] = 32'd0;
    dmem[3291] = 32'd0;
    dmem[3292] = 32'd0;
    dmem[3293] = 32'd0;
    dmem[3294] = 32'd0;
    dmem[3295] = 32'd0;
    dmem[3296] = 32'd0;
    dmem[3297] = 32'd0;
    dmem[3298] = 32'd0;
    dmem[3299] = 32'd0;
    dmem[3300] = 32'd0;
    dmem[3301] = 32'd0;
    dmem[3302] = 32'd0;
    dmem[3303] = 32'd0;
    dmem[3304] = 32'd0;
    dmem[3305] = 32'd0;
    dmem[3306] = 32'd0;
    dmem[3307] = 32'd0;
    dmem[3308] = 32'd0;
    dmem[3309] = 32'd0;
    dmem[3310] = 32'd0;
    dmem[3311] = 32'd0;
    dmem[3312] = 32'd0;
    dmem[3313] = 32'd0;
    dmem[3314] = 32'd0;
    dmem[3315] = 32'd0;
    dmem[3316] = 32'd0;
    dmem[3317] = 32'd0;
    dmem[3318] = 32'd0;
    dmem[3319] = 32'd0;
    dmem[3320] = 32'd0;
    dmem[3321] = 32'd0;
    dmem[3322] = 32'd0;
    dmem[3323] = 32'd0;
    dmem[3324] = 32'd0;
    dmem[3325] = 32'd0;
    dmem[3326] = 32'd0;
    dmem[3327] = 32'd0;
    dmem[3328] = 32'd0;
    dmem[3329] = 32'd0;
    dmem[3330] = 32'd0;
    dmem[3331] = 32'd0;
    dmem[3332] = 32'd0;
    dmem[3333] = 32'd0;
    dmem[3334] = 32'd0;
    dmem[3335] = 32'd0;
    dmem[3336] = 32'd0;
    dmem[3337] = 32'd0;
    dmem[3338] = 32'd0;
    dmem[3339] = 32'd0;
    dmem[3340] = 32'd0;
    dmem[3341] = 32'd0;
    dmem[3342] = 32'd0;
    dmem[3343] = 32'd0;
    dmem[3344] = 32'd0;
    dmem[3345] = 32'd0;
    dmem[3346] = 32'd0;
    dmem[3347] = 32'd0;
    dmem[3348] = 32'd0;
    dmem[3349] = 32'd0;
    dmem[3350] = 32'd0;
    dmem[3351] = 32'd0;
    dmem[3352] = 32'd0;
    dmem[3353] = 32'd0;
    dmem[3354] = 32'd0;
    dmem[3355] = 32'd0;
    dmem[3356] = 32'd0;
    dmem[3357] = 32'd0;
    dmem[3358] = 32'd0;
    dmem[3359] = 32'd0;
    dmem[3360] = 32'd0;
    dmem[3361] = 32'd0;
    dmem[3362] = 32'd0;
    dmem[3363] = 32'd0;
    dmem[3364] = 32'd0;
    dmem[3365] = 32'd0;
    dmem[3366] = 32'd0;
    dmem[3367] = 32'd0;
    dmem[3368] = 32'd0;
    dmem[3369] = 32'd0;
    dmem[3370] = 32'd0;
    dmem[3371] = 32'd0;
    dmem[3372] = 32'd0;
    dmem[3373] = 32'd0;
    dmem[3374] = 32'd0;
    dmem[3375] = 32'd0;
    dmem[3376] = 32'd0;
    dmem[3377] = 32'd0;
    dmem[3378] = 32'd0;
    dmem[3379] = 32'd0;
    dmem[3380] = 32'd0;
    dmem[3381] = 32'd0;
    dmem[3382] = 32'd0;
    dmem[3383] = 32'd0;
    dmem[3384] = 32'd0;
    dmem[3385] = 32'd0;
    dmem[3386] = 32'd0;
    dmem[3387] = 32'd0;
    dmem[3388] = 32'd0;
    dmem[3389] = 32'd0;
    dmem[3390] = 32'd0;
    dmem[3391] = 32'd0;
    dmem[3392] = 32'd0;
    dmem[3393] = 32'd0;
    dmem[3394] = 32'd0;
    dmem[3395] = 32'd0;
    dmem[3396] = 32'd0;
    dmem[3397] = 32'd0;
    dmem[3398] = 32'd0;
    dmem[3399] = 32'd0;
    dmem[3400] = 32'd0;
    dmem[3401] = 32'd0;
    dmem[3402] = 32'd0;
    dmem[3403] = 32'd0;
    dmem[3404] = 32'd0;
    dmem[3405] = 32'd0;
    dmem[3406] = 32'd0;
    dmem[3407] = 32'd0;
    dmem[3408] = 32'd0;
    dmem[3409] = 32'd0;
    dmem[3410] = 32'd0;
    dmem[3411] = 32'd0;
    dmem[3412] = 32'd0;
    dmem[3413] = 32'd0;
    dmem[3414] = 32'd0;
    dmem[3415] = 32'd0;
    dmem[3416] = 32'd0;
    dmem[3417] = 32'd0;
    dmem[3418] = 32'd0;
    dmem[3419] = 32'd0;
    dmem[3420] = 32'd0;
    dmem[3421] = 32'd0;
    dmem[3422] = 32'd0;
    dmem[3423] = 32'd0;
    dmem[3424] = 32'd0;
    dmem[3425] = 32'd0;
    dmem[3426] = 32'd0;
    dmem[3427] = 32'd0;
    dmem[3428] = 32'd0;
    dmem[3429] = 32'd0;
    dmem[3430] = 32'd0;
    dmem[3431] = 32'd0;
    dmem[3432] = 32'd0;
    dmem[3433] = 32'd0;
    dmem[3434] = 32'd0;
    dmem[3435] = 32'd0;
    dmem[3436] = 32'd0;
    dmem[3437] = 32'd0;
    dmem[3438] = 32'd0;
    dmem[3439] = 32'd0;
    dmem[3440] = 32'd0;
    dmem[3441] = 32'd0;
    dmem[3442] = 32'd0;
    dmem[3443] = 32'd0;
    dmem[3444] = 32'd0;
    dmem[3445] = 32'd0;
    dmem[3446] = 32'd0;
    dmem[3447] = 32'd0;
    dmem[3448] = 32'd0;
    dmem[3449] = 32'd0;
    dmem[3450] = 32'd0;
    dmem[3451] = 32'd0;
    dmem[3452] = 32'd0;
    dmem[3453] = 32'd0;
    dmem[3454] = 32'd0;
    dmem[3455] = 32'd0;
    dmem[3456] = 32'd0;
    dmem[3457] = 32'd0;
    dmem[3458] = 32'd0;
    dmem[3459] = 32'd0;
    dmem[3460] = 32'd0;
    dmem[3461] = 32'd0;
    dmem[3462] = 32'd0;
    dmem[3463] = 32'd0;
    dmem[3464] = 32'd0;
    dmem[3465] = 32'd0;
    dmem[3466] = 32'd0;
    dmem[3467] = 32'd0;
    dmem[3468] = 32'd0;
    dmem[3469] = 32'd0;
    dmem[3470] = 32'd0;
    dmem[3471] = 32'd0;
    dmem[3472] = 32'd0;
    dmem[3473] = 32'd0;
    dmem[3474] = 32'd0;
    dmem[3475] = 32'd0;
    dmem[3476] = 32'd0;
    dmem[3477] = 32'd0;
    dmem[3478] = 32'd0;
    dmem[3479] = 32'd0;
    dmem[3480] = 32'd0;
    dmem[3481] = 32'd0;
    dmem[3482] = 32'd0;
    dmem[3483] = 32'd0;
    dmem[3484] = 32'd0;
    dmem[3485] = 32'd0;
    dmem[3486] = 32'd0;
    dmem[3487] = 32'd0;
    dmem[3488] = 32'd0;
    dmem[3489] = 32'd0;
    dmem[3490] = 32'd0;
    dmem[3491] = 32'd0;
    dmem[3492] = 32'd0;
    dmem[3493] = 32'd0;
    dmem[3494] = 32'd0;
    dmem[3495] = 32'd0;
    dmem[3496] = 32'd0;
    dmem[3497] = 32'd0;
    dmem[3498] = 32'd0;
    dmem[3499] = 32'd0;
    dmem[3500] = 32'd0;
    dmem[3501] = 32'd0;
    dmem[3502] = 32'd0;
    dmem[3503] = 32'd0;
    dmem[3504] = 32'd0;
    dmem[3505] = 32'd0;
    dmem[3506] = 32'd0;
    dmem[3507] = 32'd0;
    dmem[3508] = 32'd0;
    dmem[3509] = 32'd0;
    dmem[3510] = 32'd0;
    dmem[3511] = 32'd0;
    dmem[3512] = 32'd0;
    dmem[3513] = 32'd0;
    dmem[3514] = 32'd0;
    dmem[3515] = 32'd0;
    dmem[3516] = 32'd0;
    dmem[3517] = 32'd0;
    dmem[3518] = 32'd0;
    dmem[3519] = 32'd0;
    dmem[3520] = 32'd0;
    dmem[3521] = 32'd0;
    dmem[3522] = 32'd0;
    dmem[3523] = 32'd0;
    dmem[3524] = 32'd0;
    dmem[3525] = 32'd0;
    dmem[3526] = 32'd0;
    dmem[3527] = 32'd0;
    dmem[3528] = 32'd0;
    dmem[3529] = 32'd0;
    dmem[3530] = 32'd0;
    dmem[3531] = 32'd0;
    dmem[3532] = 32'd0;
    dmem[3533] = 32'd0;
    dmem[3534] = 32'd0;
    dmem[3535] = 32'd0;
    dmem[3536] = 32'd0;
    dmem[3537] = 32'd0;
    dmem[3538] = 32'd0;
    dmem[3539] = 32'd0;
    dmem[3540] = 32'd0;
    dmem[3541] = 32'd0;
    dmem[3542] = 32'd0;
    dmem[3543] = 32'd0;
    dmem[3544] = 32'd0;
    dmem[3545] = 32'd0;
    dmem[3546] = 32'd0;
    dmem[3547] = 32'd0;
    dmem[3548] = 32'd0;
    dmem[3549] = 32'd0;
    dmem[3550] = 32'd0;
    dmem[3551] = 32'd0;
    dmem[3552] = 32'd0;
    dmem[3553] = 32'd0;
    dmem[3554] = 32'd0;
    dmem[3555] = 32'd0;
    dmem[3556] = 32'd0;
    dmem[3557] = 32'd0;
    dmem[3558] = 32'd0;
    dmem[3559] = 32'd0;
    dmem[3560] = 32'd0;
    dmem[3561] = 32'd0;
    dmem[3562] = 32'd0;
    dmem[3563] = 32'd0;
    dmem[3564] = 32'd0;
    dmem[3565] = 32'd0;
    dmem[3566] = 32'd0;
    dmem[3567] = 32'd0;
    dmem[3568] = 32'd0;
    dmem[3569] = 32'd0;
    dmem[3570] = 32'd0;
    dmem[3571] = 32'd0;
    dmem[3572] = 32'd0;
    dmem[3573] = 32'd0;
    dmem[3574] = 32'd0;
    dmem[3575] = 32'd0;
    dmem[3576] = 32'd0;
    dmem[3577] = 32'd0;
    dmem[3578] = 32'd0;
    dmem[3579] = 32'd0;
    dmem[3580] = 32'd0;
    dmem[3581] = 32'd0;
    dmem[3582] = 32'd0;
    dmem[3583] = 32'd0;
    dmem[3584] = 32'd0;
    dmem[3585] = 32'd0;
    dmem[3586] = 32'd0;
    dmem[3587] = 32'd0;
    dmem[3588] = 32'd0;
    dmem[3589] = 32'd0;
    dmem[3590] = 32'd0;
    dmem[3591] = 32'd0;
    dmem[3592] = 32'd0;
    dmem[3593] = 32'd0;
    dmem[3594] = 32'd0;
    dmem[3595] = 32'd0;
    dmem[3596] = 32'd0;
    dmem[3597] = 32'd0;
    dmem[3598] = 32'd0;
    dmem[3599] = 32'd0;
    dmem[3600] = 32'd0;
    dmem[3601] = 32'd0;
    dmem[3602] = 32'd0;
    dmem[3603] = 32'd0;
    dmem[3604] = 32'd0;
    dmem[3605] = 32'd0;
    dmem[3606] = 32'd0;
    dmem[3607] = 32'd0;
    dmem[3608] = 32'd0;
    dmem[3609] = 32'd0;
    dmem[3610] = 32'd0;
    dmem[3611] = 32'd0;
    dmem[3612] = 32'd0;
    dmem[3613] = 32'd0;
    dmem[3614] = 32'd0;
    dmem[3615] = 32'd0;
    dmem[3616] = 32'd0;
    dmem[3617] = 32'd0;
    dmem[3618] = 32'd0;
    dmem[3619] = 32'd0;
    dmem[3620] = 32'd0;
    dmem[3621] = 32'd0;
    dmem[3622] = 32'd0;
    dmem[3623] = 32'd0;
    dmem[3624] = 32'd0;
    dmem[3625] = 32'd0;
    dmem[3626] = 32'd0;
    dmem[3627] = 32'd0;
    dmem[3628] = 32'd0;
    dmem[3629] = 32'd0;
    dmem[3630] = 32'd0;
    dmem[3631] = 32'd0;
    dmem[3632] = 32'd0;
    dmem[3633] = 32'd0;
    dmem[3634] = 32'd0;
    dmem[3635] = 32'd0;
    dmem[3636] = 32'd0;
    dmem[3637] = 32'd0;
    dmem[3638] = 32'd0;
    dmem[3639] = 32'd0;
    dmem[3640] = 32'd0;
    dmem[3641] = 32'd0;
    dmem[3642] = 32'd0;
    dmem[3643] = 32'd0;
    dmem[3644] = 32'd0;
    dmem[3645] = 32'd0;
    dmem[3646] = 32'd0;
    dmem[3647] = 32'd0;
    dmem[3648] = 32'd0;
    dmem[3649] = 32'd0;
    dmem[3650] = 32'd0;
    dmem[3651] = 32'd0;
    dmem[3652] = 32'd0;
    dmem[3653] = 32'd0;
    dmem[3654] = 32'd0;
    dmem[3655] = 32'd0;
    dmem[3656] = 32'd0;
    dmem[3657] = 32'd0;
    dmem[3658] = 32'd0;
    dmem[3659] = 32'd0;
    dmem[3660] = 32'd0;
    dmem[3661] = 32'd0;
    dmem[3662] = 32'd0;
    dmem[3663] = 32'd0;
    dmem[3664] = 32'd0;
    dmem[3665] = 32'd0;
    dmem[3666] = 32'd0;
    dmem[3667] = 32'd0;
    dmem[3668] = 32'd0;
    dmem[3669] = 32'd0;
    dmem[3670] = 32'd0;
    dmem[3671] = 32'd0;
    dmem[3672] = 32'd0;
    dmem[3673] = 32'd0;
    dmem[3674] = 32'd0;
    dmem[3675] = 32'd0;
    dmem[3676] = 32'd0;
    dmem[3677] = 32'd0;
    dmem[3678] = 32'd0;
    dmem[3679] = 32'd0;
    dmem[3680] = 32'd0;
    dmem[3681] = 32'd0;
    dmem[3682] = 32'd0;
    dmem[3683] = 32'd0;
    dmem[3684] = 32'd0;
    dmem[3685] = 32'd0;
    dmem[3686] = 32'd0;
    dmem[3687] = 32'd0;
    dmem[3688] = 32'd0;
    dmem[3689] = 32'd0;
    dmem[3690] = 32'd0;
    dmem[3691] = 32'd0;
    dmem[3692] = 32'd0;
    dmem[3693] = 32'd0;
    dmem[3694] = 32'd0;
    dmem[3695] = 32'd0;
    dmem[3696] = 32'd0;
    dmem[3697] = 32'd0;
    dmem[3698] = 32'd0;
    dmem[3699] = 32'd0;
    dmem[3700] = 32'd0;
    dmem[3701] = 32'd0;
    dmem[3702] = 32'd0;
    dmem[3703] = 32'd0;
    dmem[3704] = 32'd0;
    dmem[3705] = 32'd0;
    dmem[3706] = 32'd0;
    dmem[3707] = 32'd0;
    dmem[3708] = 32'd0;
    dmem[3709] = 32'd0;
    dmem[3710] = 32'd0;
    dmem[3711] = 32'd0;
    dmem[3712] = 32'd0;
    dmem[3713] = 32'd0;
    dmem[3714] = 32'd0;
    dmem[3715] = 32'd0;
    dmem[3716] = 32'd0;
    dmem[3717] = 32'd0;
    dmem[3718] = 32'd0;
    dmem[3719] = 32'd0;
    dmem[3720] = 32'd0;
    dmem[3721] = 32'd0;
    dmem[3722] = 32'd0;
    dmem[3723] = 32'd0;
    dmem[3724] = 32'd0;
    dmem[3725] = 32'd0;
    dmem[3726] = 32'd0;
    dmem[3727] = 32'd0;
    dmem[3728] = 32'd0;
    dmem[3729] = 32'd0;
    dmem[3730] = 32'd0;
    dmem[3731] = 32'd0;
    dmem[3732] = 32'd0;
    dmem[3733] = 32'd0;
    dmem[3734] = 32'd0;
    dmem[3735] = 32'd0;
    dmem[3736] = 32'd0;
    dmem[3737] = 32'd0;
    dmem[3738] = 32'd0;
    dmem[3739] = 32'd0;
    dmem[3740] = 32'd0;
    dmem[3741] = 32'd0;
    dmem[3742] = 32'd0;
    dmem[3743] = 32'd0;
    dmem[3744] = 32'd0;
    dmem[3745] = 32'd0;
    dmem[3746] = 32'd0;
    dmem[3747] = 32'd0;
    dmem[3748] = 32'd0;
    dmem[3749] = 32'd0;
    dmem[3750] = 32'd0;
    dmem[3751] = 32'd0;
    dmem[3752] = 32'd0;
    dmem[3753] = 32'd0;
    dmem[3754] = 32'd0;
    dmem[3755] = 32'd0;
    dmem[3756] = 32'd0;
    dmem[3757] = 32'd0;
    dmem[3758] = 32'd0;
    dmem[3759] = 32'd0;
    dmem[3760] = 32'd0;
    dmem[3761] = 32'd0;
    dmem[3762] = 32'd0;
    dmem[3763] = 32'd0;
    dmem[3764] = 32'd0;
    dmem[3765] = 32'd0;
    dmem[3766] = 32'd0;
    dmem[3767] = 32'd0;
    dmem[3768] = 32'd0;
    dmem[3769] = 32'd0;
    dmem[3770] = 32'd0;
    dmem[3771] = 32'd0;
    dmem[3772] = 32'd0;
    dmem[3773] = 32'd0;
    dmem[3774] = 32'd0;
    dmem[3775] = 32'd0;
    dmem[3776] = 32'd0;
    dmem[3777] = 32'd0;
    dmem[3778] = 32'd0;
    dmem[3779] = 32'd0;
    dmem[3780] = 32'd0;
    dmem[3781] = 32'd0;
    dmem[3782] = 32'd0;
    dmem[3783] = 32'd0;
    dmem[3784] = 32'd0;
    dmem[3785] = 32'd0;
    dmem[3786] = 32'd0;
    dmem[3787] = 32'd0;
    dmem[3788] = 32'd0;
    dmem[3789] = 32'd0;
    dmem[3790] = 32'd0;
    dmem[3791] = 32'd0;
    dmem[3792] = 32'd0;
    dmem[3793] = 32'd0;
    dmem[3794] = 32'd0;
    dmem[3795] = 32'd0;
    dmem[3796] = 32'd0;
    dmem[3797] = 32'd0;
    dmem[3798] = 32'd0;
    dmem[3799] = 32'd0;
    dmem[3800] = 32'd0;
    dmem[3801] = 32'd0;
    dmem[3802] = 32'd0;
    dmem[3803] = 32'd0;
    dmem[3804] = 32'd0;
    dmem[3805] = 32'd0;
    dmem[3806] = 32'd0;
    dmem[3807] = 32'd0;
    dmem[3808] = 32'd0;
    dmem[3809] = 32'd0;
    dmem[3810] = 32'd0;
    dmem[3811] = 32'd0;
    dmem[3812] = 32'd0;
    dmem[3813] = 32'd0;
    dmem[3814] = 32'd0;
    dmem[3815] = 32'd0;
    dmem[3816] = 32'd0;
    dmem[3817] = 32'd0;
    dmem[3818] = 32'd0;
    dmem[3819] = 32'd0;
    dmem[3820] = 32'd0;
    dmem[3821] = 32'd0;
    dmem[3822] = 32'd0;
    dmem[3823] = 32'd0;
    dmem[3824] = 32'd0;
    dmem[3825] = 32'd0;
    dmem[3826] = 32'd0;
    dmem[3827] = 32'd0;
    dmem[3828] = 32'd0;
    dmem[3829] = 32'd0;
    dmem[3830] = 32'd0;
    dmem[3831] = 32'd0;
    dmem[3832] = 32'd0;
    dmem[3833] = 32'd0;
    dmem[3834] = 32'd0;
    dmem[3835] = 32'd0;
    dmem[3836] = 32'd0;
    dmem[3837] = 32'd0;
    dmem[3838] = 32'd0;
    dmem[3839] = 32'd0;
    dmem[3840] = 32'd0;
    dmem[3841] = 32'd0;
    dmem[3842] = 32'd0;
    dmem[3843] = 32'd0;
    dmem[3844] = 32'd0;
    dmem[3845] = 32'd0;
    dmem[3846] = 32'd0;
    dmem[3847] = 32'd0;
    dmem[3848] = 32'd0;
    dmem[3849] = 32'd0;
    dmem[3850] = 32'd0;
    dmem[3851] = 32'd0;
    dmem[3852] = 32'd0;
    dmem[3853] = 32'd0;
    dmem[3854] = 32'd0;
    dmem[3855] = 32'd0;
    dmem[3856] = 32'd0;
    dmem[3857] = 32'd0;
    dmem[3858] = 32'd0;
    dmem[3859] = 32'd0;
    dmem[3860] = 32'd0;
    dmem[3861] = 32'd0;
    dmem[3862] = 32'd0;
    dmem[3863] = 32'd0;
    dmem[3864] = 32'd0;
    dmem[3865] = 32'd0;
    dmem[3866] = 32'd0;
    dmem[3867] = 32'd0;
    dmem[3868] = 32'd0;
    dmem[3869] = 32'd0;
    dmem[3870] = 32'd0;
    dmem[3871] = 32'd0;
    dmem[3872] = 32'd0;
    dmem[3873] = 32'd0;
    dmem[3874] = 32'd0;
    dmem[3875] = 32'd0;
    dmem[3876] = 32'd0;
    dmem[3877] = 32'd0;
    dmem[3878] = 32'd0;
    dmem[3879] = 32'd0;
    dmem[3880] = 32'd0;
    dmem[3881] = 32'd0;
    dmem[3882] = 32'd0;
    dmem[3883] = 32'd0;
    dmem[3884] = 32'd0;
    dmem[3885] = 32'd0;
    dmem[3886] = 32'd0;
    dmem[3887] = 32'd0;
    dmem[3888] = 32'd0;
    dmem[3889] = 32'd0;
    dmem[3890] = 32'd0;
    dmem[3891] = 32'd0;
    dmem[3892] = 32'd0;
    dmem[3893] = 32'd0;
    dmem[3894] = 32'd0;
    dmem[3895] = 32'd0;
    dmem[3896] = 32'd0;
    dmem[3897] = 32'd0;
    dmem[3898] = 32'd0;
    dmem[3899] = 32'd0;
    dmem[3900] = 32'd0;
    dmem[3901] = 32'd0;
    dmem[3902] = 32'd0;
    dmem[3903] = 32'd0;
    dmem[3904] = 32'd0;
    dmem[3905] = 32'd0;
    dmem[3906] = 32'd0;
    dmem[3907] = 32'd0;
    dmem[3908] = 32'd0;
    dmem[3909] = 32'd0;
    dmem[3910] = 32'd0;
    dmem[3911] = 32'd0;
    dmem[3912] = 32'd0;
    dmem[3913] = 32'd0;
    dmem[3914] = 32'd0;
    dmem[3915] = 32'd0;
    dmem[3916] = 32'd0;
    dmem[3917] = 32'd0;
    dmem[3918] = 32'd0;
    dmem[3919] = 32'd0;
    dmem[3920] = 32'd0;
    dmem[3921] = 32'd0;
    dmem[3922] = 32'd0;
    dmem[3923] = 32'd0;
    dmem[3924] = 32'd0;
    dmem[3925] = 32'd0;
    dmem[3926] = 32'd0;
    dmem[3927] = 32'd0;
    dmem[3928] = 32'd0;
    dmem[3929] = 32'd0;
    dmem[3930] = 32'd0;
    dmem[3931] = 32'd0;
    dmem[3932] = 32'd0;
    dmem[3933] = 32'd0;
    dmem[3934] = 32'd0;
    dmem[3935] = 32'd0;
    dmem[3936] = 32'd0;
    dmem[3937] = 32'd0;
    dmem[3938] = 32'd0;
    dmem[3939] = 32'd0;
    dmem[3940] = 32'd0;
    dmem[3941] = 32'd0;
    dmem[3942] = 32'd0;
    dmem[3943] = 32'd0;
    dmem[3944] = 32'd0;
    dmem[3945] = 32'd0;
    dmem[3946] = 32'd0;
    dmem[3947] = 32'd0;
    dmem[3948] = 32'd0;
    dmem[3949] = 32'd0;
    dmem[3950] = 32'd0;
    dmem[3951] = 32'd0;
    dmem[3952] = 32'd0;
    dmem[3953] = 32'd0;
    dmem[3954] = 32'd0;
    dmem[3955] = 32'd0;
    dmem[3956] = 32'd0;
    dmem[3957] = 32'd0;
    dmem[3958] = 32'd0;
    dmem[3959] = 32'd0;
    dmem[3960] = 32'd0;
    dmem[3961] = 32'd0;
    dmem[3962] = 32'd0;
    dmem[3963] = 32'd0;
    dmem[3964] = 32'd0;
    dmem[3965] = 32'd0;
    dmem[3966] = 32'd0;
    dmem[3967] = 32'd0;
    dmem[3968] = 32'd0;
    dmem[3969] = 32'd0;
    dmem[3970] = 32'd0;
    dmem[3971] = 32'd0;
    dmem[3972] = 32'd0;
    dmem[3973] = 32'd0;
    dmem[3974] = 32'd0;
    dmem[3975] = 32'd0;
    dmem[3976] = 32'd0;
    dmem[3977] = 32'd0;
    dmem[3978] = 32'd0;
    dmem[3979] = 32'd0;
    dmem[3980] = 32'd0;
    dmem[3981] = 32'd0;
    dmem[3982] = 32'd0;
    dmem[3983] = 32'd0;
    dmem[3984] = 32'd0;
    dmem[3985] = 32'd0;
    dmem[3986] = 32'd0;
    dmem[3987] = 32'd0;
    dmem[3988] = 32'd0;
    dmem[3989] = 32'd0;
    dmem[3990] = 32'd0;
    dmem[3991] = 32'd0;
    dmem[3992] = 32'd0;
    dmem[3993] = 32'd0;
    dmem[3994] = 32'd0;
    dmem[3995] = 32'd0;
    dmem[3996] = 32'd0;
    dmem[3997] = 32'd0;
    dmem[3998] = 32'd0;
    dmem[3999] = 32'd0;
    dmem[4000] = 32'd0;
    dmem[4001] = 32'd0;
    dmem[4002] = 32'd0;
    dmem[4003] = 32'd0;
    dmem[4004] = 32'd0;
    dmem[4005] = 32'd0;
    dmem[4006] = 32'd0;
    dmem[4007] = 32'd0;
    dmem[4008] = 32'd0;
    dmem[4009] = 32'd0;
    dmem[4010] = 32'd0;
    dmem[4011] = 32'd0;
    dmem[4012] = 32'd0;
    dmem[4013] = 32'd0;
    dmem[4014] = 32'd0;
    dmem[4015] = 32'd0;
    dmem[4016] = 32'd0;
    dmem[4017] = 32'd0;
    dmem[4018] = 32'd0;
    dmem[4019] = 32'd0;
    dmem[4020] = 32'd0;
    dmem[4021] = 32'd0;
    dmem[4022] = 32'd0;
    dmem[4023] = 32'd0;
    dmem[4024] = 32'd0;
    dmem[4025] = 32'd0;
    dmem[4026] = 32'd0;
    dmem[4027] = 32'd0;
    dmem[4028] = 32'd0;
    dmem[4029] = 32'd0;
    dmem[4030] = 32'd0;
    dmem[4031] = 32'd0;
    dmem[4032] = 32'd0;
    dmem[4033] = 32'd0;
    dmem[4034] = 32'd0;
    dmem[4035] = 32'd0;
    dmem[4036] = 32'd0;
    dmem[4037] = 32'd0;
    dmem[4038] = 32'd0;
    dmem[4039] = 32'd0;
    dmem[4040] = 32'd0;
    dmem[4041] = 32'd0;
    dmem[4042] = 32'd0;
    dmem[4043] = 32'd0;
    dmem[4044] = 32'd0;
    dmem[4045] = 32'd0;
    dmem[4046] = 32'd0;
    dmem[4047] = 32'd0;
    dmem[4048] = 32'd0;
    dmem[4049] = 32'd0;
    dmem[4050] = 32'd0;
    dmem[4051] = 32'd0;
    dmem[4052] = 32'd0;
    dmem[4053] = 32'd0;
    dmem[4054] = 32'd0;
    dmem[4055] = 32'd0;
    dmem[4056] = 32'd0;
    dmem[4057] = 32'd0;
    dmem[4058] = 32'd0;
    dmem[4059] = 32'd0;
    dmem[4060] = 32'd0;
    dmem[4061] = 32'd0;
    dmem[4062] = 32'd0;
    dmem[4063] = 32'd0;
    dmem[4064] = 32'd0;
    dmem[4065] = 32'd0;
    dmem[4066] = 32'd0;
    dmem[4067] = 32'd0;
    dmem[4068] = 32'd0;
    dmem[4069] = 32'd0;
    dmem[4070] = 32'd0;
    dmem[4071] = 32'd0;
    dmem[4072] = 32'd0;
    dmem[4073] = 32'd0;
    dmem[4074] = 32'd0;
    dmem[4075] = 32'd0;
    dmem[4076] = 32'd0;
    dmem[4077] = 32'd0;
    dmem[4078] = 32'd0;
    dmem[4079] = 32'd0;
    dmem[4080] = 32'd0;
    dmem[4081] = 32'd0;
    dmem[4082] = 32'd0;
    dmem[4083] = 32'd0;
    dmem[4084] = 32'd0;
    dmem[4085] = 32'd0;
    dmem[4086] = 32'd0;
    dmem[4087] = 32'd0;
    dmem[4088] = 32'd0;
    dmem[4089] = 32'd0;
    dmem[4090] = 32'd0;
    dmem[4091] = 32'd0;
    dmem[4092] = 32'd0;
    dmem[4093] = 32'd0;
    dmem[4094] = 32'd0;
    dmem[4095] = 32'd0;
    dmem[4096] = 32'd0;
    dmem[4097] = 32'd0;
    dmem[4098] = 32'd0;
    dmem[4099] = 32'd0;
    dmem[4100] = 32'd0;
    dmem[4101] = 32'd0;
    dmem[4102] = 32'd0;
    dmem[4103] = 32'd0;
    dmem[4104] = 32'd0;
    dmem[4105] = 32'd0;
    dmem[4106] = 32'd0;
    dmem[4107] = 32'd0;
    dmem[4108] = 32'd0;
    dmem[4109] = 32'd0;
    dmem[4110] = 32'd0;
    dmem[4111] = 32'd0;
    dmem[4112] = 32'd0;
    dmem[4113] = 32'd0;
    dmem[4114] = 32'd0;
    dmem[4115] = 32'd0;
    dmem[4116] = 32'd0;
    dmem[4117] = 32'd0;
    dmem[4118] = 32'd0;
    dmem[4119] = 32'd0;
    dmem[4120] = 32'd0;
    dmem[4121] = 32'd0;
    dmem[4122] = 32'd0;
    dmem[4123] = 32'd0;
    dmem[4124] = 32'd0;
    dmem[4125] = 32'd0;
    dmem[4126] = 32'd0;
    dmem[4127] = 32'd0;
    dmem[4128] = 32'd0;
    dmem[4129] = 32'd0;
    dmem[4130] = 32'd0;
    dmem[4131] = 32'd0;
    dmem[4132] = 32'd0;
    dmem[4133] = 32'd0;
    dmem[4134] = 32'd0;
    dmem[4135] = 32'd0;
    dmem[4136] = 32'd0;
    dmem[4137] = 32'd0;
    dmem[4138] = 32'd0;
    dmem[4139] = 32'd0;
    dmem[4140] = 32'd0;
    dmem[4141] = 32'd0;
    dmem[4142] = 32'd0;
    dmem[4143] = 32'd0;
    dmem[4144] = 32'd0;
    dmem[4145] = 32'd0;
    dmem[4146] = 32'd0;
    dmem[4147] = 32'd0;
    dmem[4148] = 32'd0;
    dmem[4149] = 32'd0;
    dmem[4150] = 32'd0;
    dmem[4151] = 32'd0;
    dmem[4152] = 32'd0;
    dmem[4153] = 32'd0;
    dmem[4154] = 32'd0;
    dmem[4155] = 32'd0;
    dmem[4156] = 32'd0;
    dmem[4157] = 32'd0;
    dmem[4158] = 32'd0;
    dmem[4159] = 32'd0;
    dmem[4160] = 32'd0;
    dmem[4161] = 32'd0;
    dmem[4162] = 32'd0;
    dmem[4163] = 32'd0;
    dmem[4164] = 32'd0;
    dmem[4165] = 32'd0;
    dmem[4166] = 32'd0;
    dmem[4167] = 32'd0;
    dmem[4168] = 32'd0;
    dmem[4169] = 32'd0;
    dmem[4170] = 32'd0;
    dmem[4171] = 32'd0;
    dmem[4172] = 32'd0;
    dmem[4173] = 32'd0;
    dmem[4174] = 32'd0;
    dmem[4175] = 32'd0;
    dmem[4176] = 32'd0;
    dmem[4177] = 32'd0;
    dmem[4178] = 32'd0;
    dmem[4179] = 32'd0;
    dmem[4180] = 32'd0;
    dmem[4181] = 32'd0;
    dmem[4182] = 32'd0;
    dmem[4183] = 32'd0;
    dmem[4184] = 32'd0;
    dmem[4185] = 32'd0;
    dmem[4186] = 32'd0;
    dmem[4187] = 32'd0;
    dmem[4188] = 32'd0;
    dmem[4189] = 32'd0;
    dmem[4190] = 32'd0;
    dmem[4191] = 32'd0;
    dmem[4192] = 32'd0;
    dmem[4193] = 32'd0;
    dmem[4194] = 32'd0;
    dmem[4195] = 32'd0;
    dmem[4196] = 32'd0;
    dmem[4197] = 32'd0;
    dmem[4198] = 32'd0;
    dmem[4199] = 32'd0;
    dmem[4200] = 32'd0;
    dmem[4201] = 32'd0;
    dmem[4202] = 32'd0;
    dmem[4203] = 32'd0;
    dmem[4204] = 32'd0;
    dmem[4205] = 32'd0;
    dmem[4206] = 32'd0;
    dmem[4207] = 32'd0;
    dmem[4208] = 32'd0;
    dmem[4209] = 32'd0;
    dmem[4210] = 32'd0;
    dmem[4211] = 32'd0;
    dmem[4212] = 32'd0;
    dmem[4213] = 32'd0;
    dmem[4214] = 32'd0;
    dmem[4215] = 32'd0;
    dmem[4216] = 32'd0;
    dmem[4217] = 32'd0;
    dmem[4218] = 32'd0;
    dmem[4219] = 32'd0;
    dmem[4220] = 32'd0;
    dmem[4221] = 32'd0;
    dmem[4222] = 32'd0;
    dmem[4223] = 32'd0;
    dmem[4224] = 32'd0;
    dmem[4225] = 32'd0;
    dmem[4226] = 32'd0;
    dmem[4227] = 32'd0;
    dmem[4228] = 32'd0;
    dmem[4229] = 32'd0;
    dmem[4230] = 32'd0;
    dmem[4231] = 32'd0;
    dmem[4232] = 32'd0;
    dmem[4233] = 32'd0;
    dmem[4234] = 32'd0;
    dmem[4235] = 32'd0;
    dmem[4236] = 32'd0;
    dmem[4237] = 32'd0;
    dmem[4238] = 32'd0;
    dmem[4239] = 32'd0;
    dmem[4240] = 32'd0;
    dmem[4241] = 32'd0;
    dmem[4242] = 32'd0;
    dmem[4243] = 32'd0;
    dmem[4244] = 32'd0;
    dmem[4245] = 32'd0;
    dmem[4246] = 32'd0;
    dmem[4247] = 32'd0;
    dmem[4248] = 32'd0;
    dmem[4249] = 32'd0;
    dmem[4250] = 32'd0;
    dmem[4251] = 32'd0;
    dmem[4252] = 32'd0;
    dmem[4253] = 32'd0;
    dmem[4254] = 32'd0;
    dmem[4255] = 32'd0;
    dmem[4256] = 32'd0;
    dmem[4257] = 32'd0;
    dmem[4258] = 32'd0;
    dmem[4259] = 32'd0;
    dmem[4260] = 32'd0;
    dmem[4261] = 32'd0;
    dmem[4262] = 32'd0;
    dmem[4263] = 32'd0;
    dmem[4264] = 32'd0;
    dmem[4265] = 32'd0;
    dmem[4266] = 32'd0;
    dmem[4267] = 32'd0;
    dmem[4268] = 32'd0;
    dmem[4269] = 32'd0;
    dmem[4270] = 32'd0;
    dmem[4271] = 32'd0;
    dmem[4272] = 32'd0;
    dmem[4273] = 32'd0;
    dmem[4274] = 32'd0;
    dmem[4275] = 32'd0;
    dmem[4276] = 32'd0;
    dmem[4277] = 32'd0;
    dmem[4278] = 32'd0;
    dmem[4279] = 32'd0;
    dmem[4280] = 32'd0;
    dmem[4281] = 32'd0;
    dmem[4282] = 32'd0;
    dmem[4283] = 32'd0;
    dmem[4284] = 32'd0;
    dmem[4285] = 32'd0;
    dmem[4286] = 32'd0;
    dmem[4287] = 32'd0;
    dmem[4288] = 32'd0;
    dmem[4289] = 32'd0;
    dmem[4290] = 32'd0;
    dmem[4291] = 32'd0;
    dmem[4292] = 32'd0;
    dmem[4293] = 32'd0;
    dmem[4294] = 32'd0;
    dmem[4295] = 32'd0;
    dmem[4296] = 32'd0;
    dmem[4297] = 32'd0;
    dmem[4298] = 32'd0;
    dmem[4299] = 32'd0;
    dmem[4300] = 32'd0;
    dmem[4301] = 32'd0;
    dmem[4302] = 32'd0;
    dmem[4303] = 32'd0;
    dmem[4304] = 32'd0;
    dmem[4305] = 32'd0;
    dmem[4306] = 32'd0;
    dmem[4307] = 32'd0;
    dmem[4308] = 32'd0;
    dmem[4309] = 32'd0;
    dmem[4310] = 32'd0;
    dmem[4311] = 32'd0;
    dmem[4312] = 32'd0;
    dmem[4313] = 32'd0;
    dmem[4314] = 32'd0;
    dmem[4315] = 32'd0;
    dmem[4316] = 32'd0;
    dmem[4317] = 32'd0;
    dmem[4318] = 32'd0;
    dmem[4319] = 32'd0;
    dmem[4320] = 32'd0;
    dmem[4321] = 32'd0;
    dmem[4322] = 32'd0;
    dmem[4323] = 32'd0;
    dmem[4324] = 32'd0;
    dmem[4325] = 32'd0;
    dmem[4326] = 32'd0;
    dmem[4327] = 32'd0;
    dmem[4328] = 32'd0;
    dmem[4329] = 32'd0;
    dmem[4330] = 32'd0;
    dmem[4331] = 32'd0;
    dmem[4332] = 32'd0;
    dmem[4333] = 32'd0;
    dmem[4334] = 32'd0;
    dmem[4335] = 32'd0;
    dmem[4336] = 32'd0;
    dmem[4337] = 32'd0;
    dmem[4338] = 32'd0;
    dmem[4339] = 32'd0;
    dmem[4340] = 32'd0;
    dmem[4341] = 32'd0;
    dmem[4342] = 32'd0;
    dmem[4343] = 32'd0;
    dmem[4344] = 32'd0;
    dmem[4345] = 32'd0;
    dmem[4346] = 32'd0;
    dmem[4347] = 32'd0;
    dmem[4348] = 32'd0;
    dmem[4349] = 32'd0;
    dmem[4350] = 32'd0;
    dmem[4351] = 32'd0;
    dmem[4352] = 32'd0;
    dmem[4353] = 32'd0;
    dmem[4354] = 32'd0;
    dmem[4355] = 32'd0;
    dmem[4356] = 32'd0;
    dmem[4357] = 32'd0;
    dmem[4358] = 32'd0;
    dmem[4359] = 32'd0;
    dmem[4360] = 32'd0;
    dmem[4361] = 32'd0;
    dmem[4362] = 32'd0;
    dmem[4363] = 32'd0;
    dmem[4364] = 32'd0;
    dmem[4365] = 32'd0;
    dmem[4366] = 32'd0;
    dmem[4367] = 32'd0;
    dmem[4368] = 32'd0;
    dmem[4369] = 32'd0;
    dmem[4370] = 32'd0;
    dmem[4371] = 32'd0;
    dmem[4372] = 32'd0;
    dmem[4373] = 32'd0;
    dmem[4374] = 32'd0;
    dmem[4375] = 32'd0;
    dmem[4376] = 32'd0;
    dmem[4377] = 32'd0;
    dmem[4378] = 32'd0;
    dmem[4379] = 32'd0;
    dmem[4380] = 32'd0;
    dmem[4381] = 32'd0;
    dmem[4382] = 32'd0;
    dmem[4383] = 32'd0;
    dmem[4384] = 32'd0;
    dmem[4385] = 32'd0;
    dmem[4386] = 32'd0;
    dmem[4387] = 32'd0;
    dmem[4388] = 32'd0;
    dmem[4389] = 32'd0;
    dmem[4390] = 32'd0;
    dmem[4391] = 32'd0;
    dmem[4392] = 32'd0;
    dmem[4393] = 32'd0;
    dmem[4394] = 32'd0;
    dmem[4395] = 32'd0;
    dmem[4396] = 32'd0;
    dmem[4397] = 32'd0;
    dmem[4398] = 32'd0;
    dmem[4399] = 32'd0;
    dmem[4400] = 32'd0;
    dmem[4401] = 32'd0;
    dmem[4402] = 32'd0;
    dmem[4403] = 32'd0;
    dmem[4404] = 32'd0;
    dmem[4405] = 32'd0;
    dmem[4406] = 32'd0;
    dmem[4407] = 32'd0;
    dmem[4408] = 32'd0;
    dmem[4409] = 32'd0;
    dmem[4410] = 32'd0;
    dmem[4411] = 32'd0;
    dmem[4412] = 32'd0;
    dmem[4413] = 32'd0;
    dmem[4414] = 32'd0;
    dmem[4415] = 32'd0;
    dmem[4416] = 32'd0;
    dmem[4417] = 32'd0;
    dmem[4418] = 32'd0;
    dmem[4419] = 32'd0;
    dmem[4420] = 32'd0;
    dmem[4421] = 32'd0;
    dmem[4422] = 32'd0;
    dmem[4423] = 32'd0;
    dmem[4424] = 32'd0;
    dmem[4425] = 32'd0;
    dmem[4426] = 32'd0;
    dmem[4427] = 32'd0;
    dmem[4428] = 32'd0;
    dmem[4429] = 32'd0;
    dmem[4430] = 32'd0;
    dmem[4431] = 32'd0;
    dmem[4432] = 32'd0;
    dmem[4433] = 32'd0;
    dmem[4434] = 32'd0;
    dmem[4435] = 32'd0;
    dmem[4436] = 32'd0;
    dmem[4437] = 32'd0;
    dmem[4438] = 32'd0;
    dmem[4439] = 32'd0;
    dmem[4440] = 32'd0;
    dmem[4441] = 32'd0;
    dmem[4442] = 32'd0;
    dmem[4443] = 32'd0;
    dmem[4444] = 32'd0;
    dmem[4445] = 32'd0;
    dmem[4446] = 32'd0;
    dmem[4447] = 32'd0;
    dmem[4448] = 32'd0;
    dmem[4449] = 32'd0;
    dmem[4450] = 32'd0;
    dmem[4451] = 32'd0;
    dmem[4452] = 32'd0;
    dmem[4453] = 32'd0;
    dmem[4454] = 32'd0;
    dmem[4455] = 32'd0;
    dmem[4456] = 32'd0;
    dmem[4457] = 32'd0;
    dmem[4458] = 32'd0;
    dmem[4459] = 32'd0;
    dmem[4460] = 32'd0;
    dmem[4461] = 32'd0;
    dmem[4462] = 32'd0;
    dmem[4463] = 32'd0;
    dmem[4464] = 32'd0;
    dmem[4465] = 32'd0;
    dmem[4466] = 32'd0;
    dmem[4467] = 32'd0;
    dmem[4468] = 32'd0;
    dmem[4469] = 32'd0;
    dmem[4470] = 32'd0;
    dmem[4471] = 32'd0;
    dmem[4472] = 32'd0;
    dmem[4473] = 32'd0;
    dmem[4474] = 32'd0;
    dmem[4475] = 32'd0;
    dmem[4476] = 32'd0;
    dmem[4477] = 32'd0;
    dmem[4478] = 32'd0;
    dmem[4479] = 32'd0;
    dmem[4480] = 32'd0;
    dmem[4481] = 32'd0;
    dmem[4482] = 32'd0;
    dmem[4483] = 32'd0;
    dmem[4484] = 32'd0;
    dmem[4485] = 32'd0;
    dmem[4486] = 32'd0;
    dmem[4487] = 32'd0;
    dmem[4488] = 32'd0;
    dmem[4489] = 32'd0;
    dmem[4490] = 32'd0;
    dmem[4491] = 32'd0;
    dmem[4492] = 32'd0;
    dmem[4493] = 32'd0;
    dmem[4494] = 32'd0;
    dmem[4495] = 32'd0;
    dmem[4496] = 32'd0;
    dmem[4497] = 32'd0;
    dmem[4498] = 32'd0;
    dmem[4499] = 32'd0;
    dmem[4500] = 32'd0;
    dmem[4501] = 32'd0;
    dmem[4502] = 32'd0;
    dmem[4503] = 32'd0;
    dmem[4504] = 32'd0;
    dmem[4505] = 32'd0;
    dmem[4506] = 32'd0;
    dmem[4507] = 32'd0;
    dmem[4508] = 32'd0;
    dmem[4509] = 32'd0;
    dmem[4510] = 32'd0;
    dmem[4511] = 32'd0;
    dmem[4512] = 32'd0;
    dmem[4513] = 32'd0;
    dmem[4514] = 32'd0;
    dmem[4515] = 32'd0;
    dmem[4516] = 32'd0;
    dmem[4517] = 32'd0;
    dmem[4518] = 32'd0;
    dmem[4519] = 32'd0;
    dmem[4520] = 32'd0;
    dmem[4521] = 32'd0;
    dmem[4522] = 32'd0;
    dmem[4523] = 32'd0;
    dmem[4524] = 32'd0;
    dmem[4525] = 32'd0;
    dmem[4526] = 32'd0;
    dmem[4527] = 32'd0;
    dmem[4528] = 32'd0;
    dmem[4529] = 32'd0;
    dmem[4530] = 32'd0;
    dmem[4531] = 32'd0;
    dmem[4532] = 32'd0;
    dmem[4533] = 32'd0;
    dmem[4534] = 32'd0;
    dmem[4535] = 32'd0;
    dmem[4536] = 32'd0;
    dmem[4537] = 32'd0;
    dmem[4538] = 32'd0;
    dmem[4539] = 32'd0;
    dmem[4540] = 32'd0;
    dmem[4541] = 32'd0;
    dmem[4542] = 32'd0;
    dmem[4543] = 32'd0;
    dmem[4544] = 32'd0;
    dmem[4545] = 32'd0;
    dmem[4546] = 32'd0;
    dmem[4547] = 32'd0;
    dmem[4548] = 32'd0;
    dmem[4549] = 32'd0;
    dmem[4550] = 32'd0;
    dmem[4551] = 32'd0;
    dmem[4552] = 32'd0;
    dmem[4553] = 32'd0;
    dmem[4554] = 32'd0;
    dmem[4555] = 32'd0;
    dmem[4556] = 32'd0;
    dmem[4557] = 32'd0;
    dmem[4558] = 32'd0;
    dmem[4559] = 32'd0;
    dmem[4560] = 32'd0;
    dmem[4561] = 32'd0;
    dmem[4562] = 32'd0;
    dmem[4563] = 32'd0;
    dmem[4564] = 32'd0;
    dmem[4565] = 32'd0;
    dmem[4566] = 32'd0;
    dmem[4567] = 32'd0;
    dmem[4568] = 32'd0;
    dmem[4569] = 32'd0;
    dmem[4570] = 32'd0;
    dmem[4571] = 32'd0;
    dmem[4572] = 32'd0;
    dmem[4573] = 32'd0;
    dmem[4574] = 32'd0;
    dmem[4575] = 32'd0;
    dmem[4576] = 32'd0;
    dmem[4577] = 32'd0;
    dmem[4578] = 32'd0;
    dmem[4579] = 32'd0;
    dmem[4580] = 32'd0;
    dmem[4581] = 32'd0;
    dmem[4582] = 32'd0;
    dmem[4583] = 32'd0;
    dmem[4584] = 32'd0;
    dmem[4585] = 32'd0;
    dmem[4586] = 32'd0;
    dmem[4587] = 32'd0;
    dmem[4588] = 32'd0;
    dmem[4589] = 32'd0;
    dmem[4590] = 32'd0;
    dmem[4591] = 32'd0;
    dmem[4592] = 32'd0;
    dmem[4593] = 32'd0;
    dmem[4594] = 32'd0;
    dmem[4595] = 32'd0;
    dmem[4596] = 32'd0;
    dmem[4597] = 32'd0;
    dmem[4598] = 32'd0;
    dmem[4599] = 32'd0;
    dmem[4600] = 32'd0;
    dmem[4601] = 32'd0;
    dmem[4602] = 32'd0;
    dmem[4603] = 32'd0;
    dmem[4604] = 32'd0;
    dmem[4605] = 32'd0;
    dmem[4606] = 32'd0;
    dmem[4607] = 32'd0;
    dmem[4608] = 32'd0;
    dmem[4609] = 32'd0;
    dmem[4610] = 32'd0;
    dmem[4611] = 32'd0;
    dmem[4612] = 32'd0;
    dmem[4613] = 32'd0;
    dmem[4614] = 32'd0;
    dmem[4615] = 32'd0;
    dmem[4616] = 32'd0;
    dmem[4617] = 32'd0;
    dmem[4618] = 32'd0;
    dmem[4619] = 32'd0;
    dmem[4620] = 32'd0;
    dmem[4621] = 32'd0;
    dmem[4622] = 32'd0;
    dmem[4623] = 32'd0;
    dmem[4624] = 32'd0;
    dmem[4625] = 32'd0;
    dmem[4626] = 32'd0;
    dmem[4627] = 32'd0;
    dmem[4628] = 32'd0;
    dmem[4629] = 32'd0;
    dmem[4630] = 32'd0;
    dmem[4631] = 32'd0;
    dmem[4632] = 32'd0;
    dmem[4633] = 32'd0;
    dmem[4634] = 32'd0;
    dmem[4635] = 32'd0;
    dmem[4636] = 32'd0;
    dmem[4637] = 32'd0;
    dmem[4638] = 32'd0;
    dmem[4639] = 32'd0;
    dmem[4640] = 32'd0;
    dmem[4641] = 32'd0;
    dmem[4642] = 32'd0;
    dmem[4643] = 32'd0;
    dmem[4644] = 32'd0;
    dmem[4645] = 32'd0;
    dmem[4646] = 32'd0;
    dmem[4647] = 32'd0;
    dmem[4648] = 32'd0;
    dmem[4649] = 32'd0;
    dmem[4650] = 32'd0;
    dmem[4651] = 32'd0;
    dmem[4652] = 32'd0;
    dmem[4653] = 32'd0;
    dmem[4654] = 32'd0;
    dmem[4655] = 32'd0;
    dmem[4656] = 32'd0;
    dmem[4657] = 32'd0;
    dmem[4658] = 32'd0;
    dmem[4659] = 32'd0;
    dmem[4660] = 32'd0;
    dmem[4661] = 32'd0;
    dmem[4662] = 32'd0;
    dmem[4663] = 32'd0;
    dmem[4664] = 32'd0;
    dmem[4665] = 32'd0;
    dmem[4666] = 32'd0;
    dmem[4667] = 32'd0;
    dmem[4668] = 32'd0;
    dmem[4669] = 32'd0;
    dmem[4670] = 32'd0;
    dmem[4671] = 32'd0;
    dmem[4672] = 32'd0;
    dmem[4673] = 32'd0;
    dmem[4674] = 32'd0;
    dmem[4675] = 32'd0;
    dmem[4676] = 32'd0;
    dmem[4677] = 32'd0;
    dmem[4678] = 32'd0;
    dmem[4679] = 32'd0;
    dmem[4680] = 32'd0;
    dmem[4681] = 32'd0;
    dmem[4682] = 32'd0;
    dmem[4683] = 32'd0;
    dmem[4684] = 32'd0;
    dmem[4685] = 32'd0;
    dmem[4686] = 32'd0;
    dmem[4687] = 32'd0;
    dmem[4688] = 32'd0;
    dmem[4689] = 32'd0;
    dmem[4690] = 32'd0;
    dmem[4691] = 32'd0;
    dmem[4692] = 32'd0;
    dmem[4693] = 32'd0;
    dmem[4694] = 32'd0;
    dmem[4695] = 32'd0;
    dmem[4696] = 32'd0;
    dmem[4697] = 32'd0;
    dmem[4698] = 32'd0;
    dmem[4699] = 32'd0;
    dmem[4700] = 32'd0;
    dmem[4701] = 32'd0;
    dmem[4702] = 32'd0;
    dmem[4703] = 32'd0;
    dmem[4704] = 32'd0;
    dmem[4705] = 32'd0;
    dmem[4706] = 32'd0;
    dmem[4707] = 32'd0;
    dmem[4708] = 32'd0;
    dmem[4709] = 32'd0;
    dmem[4710] = 32'd0;
    dmem[4711] = 32'd0;
    dmem[4712] = 32'd0;
    dmem[4713] = 32'd0;
    dmem[4714] = 32'd0;
    dmem[4715] = 32'd0;
    dmem[4716] = 32'd0;
    dmem[4717] = 32'd0;
    dmem[4718] = 32'd0;
    dmem[4719] = 32'd0;
    dmem[4720] = 32'd0;
    dmem[4721] = 32'd0;
    dmem[4722] = 32'd0;
    dmem[4723] = 32'd0;
    dmem[4724] = 32'd0;
    dmem[4725] = 32'd0;
    dmem[4726] = 32'd0;
    dmem[4727] = 32'd0;
    dmem[4728] = 32'd0;
    dmem[4729] = 32'd0;
    dmem[4730] = 32'd0;
    dmem[4731] = 32'd0;
    dmem[4732] = 32'd0;
    dmem[4733] = 32'd0;
    dmem[4734] = 32'd0;
    dmem[4735] = 32'd0;
    dmem[4736] = 32'd0;
    dmem[4737] = 32'd0;
    dmem[4738] = 32'd0;
    dmem[4739] = 32'd0;
    dmem[4740] = 32'd0;
    dmem[4741] = 32'd0;
    dmem[4742] = 32'd0;
    dmem[4743] = 32'd0;
    dmem[4744] = 32'd0;
    dmem[4745] = 32'd0;
    dmem[4746] = 32'd0;
    dmem[4747] = 32'd0;
    dmem[4748] = 32'd0;
    dmem[4749] = 32'd0;
    dmem[4750] = 32'd0;
    dmem[4751] = 32'd0;
    dmem[4752] = 32'd0;
    dmem[4753] = 32'd0;
    dmem[4754] = 32'd0;
    dmem[4755] = 32'd0;
    dmem[4756] = 32'd0;
    dmem[4757] = 32'd0;
    dmem[4758] = 32'd0;
    dmem[4759] = 32'd0;
    dmem[4760] = 32'd0;
    dmem[4761] = 32'd0;
    dmem[4762] = 32'd0;
    dmem[4763] = 32'd0;
    dmem[4764] = 32'd0;
    dmem[4765] = 32'd0;
    dmem[4766] = 32'd0;
    dmem[4767] = 32'd0;
    dmem[4768] = 32'd0;
    dmem[4769] = 32'd0;
    dmem[4770] = 32'd0;
    dmem[4771] = 32'd0;
    dmem[4772] = 32'd0;
    dmem[4773] = 32'd0;
    dmem[4774] = 32'd0;
    dmem[4775] = 32'd0;
    dmem[4776] = 32'd0;
    dmem[4777] = 32'd0;
    dmem[4778] = 32'd0;
    dmem[4779] = 32'd0;
    dmem[4780] = 32'd0;
    dmem[4781] = 32'd0;
    dmem[4782] = 32'd0;
    dmem[4783] = 32'd0;
    dmem[4784] = 32'd0;
    dmem[4785] = 32'd0;
    dmem[4786] = 32'd0;
    dmem[4787] = 32'd0;
    dmem[4788] = 32'd0;
    dmem[4789] = 32'd0;
    dmem[4790] = 32'd0;
    dmem[4791] = 32'd0;
    dmem[4792] = 32'd0;
    dmem[4793] = 32'd0;
    dmem[4794] = 32'd0;
    dmem[4795] = 32'd0;
    dmem[4796] = 32'd0;
    dmem[4797] = 32'd0;
    dmem[4798] = 32'd0;
    dmem[4799] = 32'd0;
    dmem[4800] = 32'd0;
    dmem[4801] = 32'd0;
    dmem[4802] = 32'd0;
    dmem[4803] = 32'd0;
    dmem[4804] = 32'd0;
    dmem[4805] = 32'd0;
    dmem[4806] = 32'd0;
    dmem[4807] = 32'd0;
    dmem[4808] = 32'd0;
    dmem[4809] = 32'd0;
    dmem[4810] = 32'd0;
    dmem[4811] = 32'd0;
    dmem[4812] = 32'd0;
    dmem[4813] = 32'd0;
    dmem[4814] = 32'd0;
    dmem[4815] = 32'd0;
    dmem[4816] = 32'd0;
    dmem[4817] = 32'd0;
    dmem[4818] = 32'd0;
    dmem[4819] = 32'd0;
    dmem[4820] = 32'd0;
    dmem[4821] = 32'd0;
    dmem[4822] = 32'd0;
    dmem[4823] = 32'd0;
    dmem[4824] = 32'd0;
    dmem[4825] = 32'd0;
    dmem[4826] = 32'd0;
    dmem[4827] = 32'd0;
    dmem[4828] = 32'd0;
    dmem[4829] = 32'd0;
    dmem[4830] = 32'd0;
    dmem[4831] = 32'd0;
    dmem[4832] = 32'd0;
    dmem[4833] = 32'd0;
    dmem[4834] = 32'd0;
    dmem[4835] = 32'd0;
    dmem[4836] = 32'd0;
    dmem[4837] = 32'd0;
    dmem[4838] = 32'd0;
    dmem[4839] = 32'd0;
    dmem[4840] = 32'd0;
    dmem[4841] = 32'd0;
    dmem[4842] = 32'd0;
    dmem[4843] = 32'd0;
    dmem[4844] = 32'd0;
    dmem[4845] = 32'd0;
    dmem[4846] = 32'd0;
    dmem[4847] = 32'd0;
    dmem[4848] = 32'd0;
    dmem[4849] = 32'd0;
    dmem[4850] = 32'd0;
    dmem[4851] = 32'd0;
    dmem[4852] = 32'd0;
    dmem[4853] = 32'd0;
    dmem[4854] = 32'd0;
    dmem[4855] = 32'd0;
    dmem[4856] = 32'd0;
    dmem[4857] = 32'd0;
    dmem[4858] = 32'd0;
    dmem[4859] = 32'd0;
    dmem[4860] = 32'd0;
    dmem[4861] = 32'd0;
    dmem[4862] = 32'd0;
    dmem[4863] = 32'd0;
    dmem[4864] = 32'd0;
    dmem[4865] = 32'd0;
    dmem[4866] = 32'd0;
    dmem[4867] = 32'd0;
    dmem[4868] = 32'd0;
    dmem[4869] = 32'd0;
    dmem[4870] = 32'd0;
    dmem[4871] = 32'd0;
    dmem[4872] = 32'd0;
    dmem[4873] = 32'd0;
    dmem[4874] = 32'd0;
    dmem[4875] = 32'd0;
    dmem[4876] = 32'd0;
    dmem[4877] = 32'd0;
    dmem[4878] = 32'd0;
    dmem[4879] = 32'd0;
    dmem[4880] = 32'd0;
    dmem[4881] = 32'd0;
    dmem[4882] = 32'd0;
    dmem[4883] = 32'd0;
    dmem[4884] = 32'd0;
    dmem[4885] = 32'd0;
    dmem[4886] = 32'd0;
    dmem[4887] = 32'd0;
    dmem[4888] = 32'd0;
    dmem[4889] = 32'd0;
    dmem[4890] = 32'd0;
    dmem[4891] = 32'd0;
    dmem[4892] = 32'd0;
    dmem[4893] = 32'd0;
    dmem[4894] = 32'd0;
    dmem[4895] = 32'd0;
    dmem[4896] = 32'd0;
    dmem[4897] = 32'd0;
    dmem[4898] = 32'd0;
    dmem[4899] = 32'd0;
    dmem[4900] = 32'd0;
    dmem[4901] = 32'd0;
    dmem[4902] = 32'd0;
    dmem[4903] = 32'd0;
    dmem[4904] = 32'd0;
    dmem[4905] = 32'd0;
    dmem[4906] = 32'd0;
    dmem[4907] = 32'd0;
    dmem[4908] = 32'd0;
    dmem[4909] = 32'd0;
    dmem[4910] = 32'd0;
    dmem[4911] = 32'd0;
    dmem[4912] = 32'd0;
    dmem[4913] = 32'd0;
    dmem[4914] = 32'd0;
    dmem[4915] = 32'd0;
    dmem[4916] = 32'd0;
    dmem[4917] = 32'd0;
    dmem[4918] = 32'd0;
    dmem[4919] = 32'd0;
    dmem[4920] = 32'd0;
    dmem[4921] = 32'd0;
    dmem[4922] = 32'd0;
    dmem[4923] = 32'd0;
    dmem[4924] = 32'd0;
    dmem[4925] = 32'd0;
    dmem[4926] = 32'd0;
    dmem[4927] = 32'd0;
    dmem[4928] = 32'd0;
    dmem[4929] = 32'd0;
    dmem[4930] = 32'd0;
    dmem[4931] = 32'd0;
    dmem[4932] = 32'd0;
    dmem[4933] = 32'd0;
    dmem[4934] = 32'd0;
    dmem[4935] = 32'd0;
    dmem[4936] = 32'd0;
    dmem[4937] = 32'd0;
    dmem[4938] = 32'd0;
    dmem[4939] = 32'd0;
    dmem[4940] = 32'd0;
    dmem[4941] = 32'd0;
    dmem[4942] = 32'd0;
    dmem[4943] = 32'd0;
    dmem[4944] = 32'd0;
    dmem[4945] = 32'd0;
    dmem[4946] = 32'd0;
    dmem[4947] = 32'd0;
    dmem[4948] = 32'd0;
    dmem[4949] = 32'd0;
    dmem[4950] = 32'd0;
    dmem[4951] = 32'd0;
    dmem[4952] = 32'd0;
    dmem[4953] = 32'd0;
    dmem[4954] = 32'd0;
    dmem[4955] = 32'd0;
    dmem[4956] = 32'd0;
    dmem[4957] = 32'd0;
    dmem[4958] = 32'd0;
    dmem[4959] = 32'd0;
    dmem[4960] = 32'd0;
    dmem[4961] = 32'd0;
    dmem[4962] = 32'd0;
    dmem[4963] = 32'd0;
    dmem[4964] = 32'd0;
    dmem[4965] = 32'd0;
    dmem[4966] = 32'd0;
    dmem[4967] = 32'd0;
    dmem[4968] = 32'd0;
    dmem[4969] = 32'd0;
    dmem[4970] = 32'd0;
    dmem[4971] = 32'd0;
    dmem[4972] = 32'd0;
    dmem[4973] = 32'd0;
    dmem[4974] = 32'd0;
    dmem[4975] = 32'd0;
    dmem[4976] = 32'd0;
    dmem[4977] = 32'd0;
    dmem[4978] = 32'd0;
    dmem[4979] = 32'd0;
    dmem[4980] = 32'd0;
    dmem[4981] = 32'd0;
    dmem[4982] = 32'd0;
    dmem[4983] = 32'd0;
    dmem[4984] = 32'd0;
    dmem[4985] = 32'd0;
    dmem[4986] = 32'd0;
    dmem[4987] = 32'd0;
    dmem[4988] = 32'd0;
    dmem[4989] = 32'd0;
    dmem[4990] = 32'd0;
    dmem[4991] = 32'd0;
    dmem[4992] = 32'd0;
    dmem[4993] = 32'd0;
    dmem[4994] = 32'd0;
    dmem[4995] = 32'd0;
    dmem[4996] = 32'd0;
    dmem[4997] = 32'd0;
    dmem[4998] = 32'd0;
    dmem[4999] = 32'd0;
    dmem[5000] = 32'd0;
    dmem[5001] = 32'd0;
    dmem[5002] = 32'd0;
    dmem[5003] = 32'd0;
    dmem[5004] = 32'd0;
    dmem[5005] = 32'd0;
    dmem[5006] = 32'd0;
    dmem[5007] = 32'd0;
    dmem[5008] = 32'd0;
    dmem[5009] = 32'd0;
    dmem[5010] = 32'd0;
    dmem[5011] = 32'd0;
    dmem[5012] = 32'd0;
    dmem[5013] = 32'd0;
    dmem[5014] = 32'd0;
    dmem[5015] = 32'd0;
    dmem[5016] = 32'd0;
    dmem[5017] = 32'd0;
    dmem[5018] = 32'd0;
    dmem[5019] = 32'd0;
    dmem[5020] = 32'd0;
    dmem[5021] = 32'd0;
    dmem[5022] = 32'd0;
    dmem[5023] = 32'd0;
    dmem[5024] = 32'd0;
    dmem[5025] = 32'd0;
    dmem[5026] = 32'd0;
    dmem[5027] = 32'd0;
    dmem[5028] = 32'd0;
    dmem[5029] = 32'd0;
    dmem[5030] = 32'd0;
    dmem[5031] = 32'd0;
    dmem[5032] = 32'd0;
    dmem[5033] = 32'd0;
    dmem[5034] = 32'd0;
    dmem[5035] = 32'd0;
    dmem[5036] = 32'd0;
    dmem[5037] = 32'd0;
    dmem[5038] = 32'd0;
    dmem[5039] = 32'd0;
    dmem[5040] = 32'd0;
    dmem[5041] = 32'd0;
    dmem[5042] = 32'd0;
    dmem[5043] = 32'd0;
    dmem[5044] = 32'd0;
    dmem[5045] = 32'd0;
    dmem[5046] = 32'd0;
    dmem[5047] = 32'd0;
    dmem[5048] = 32'd0;
    dmem[5049] = 32'd0;
    dmem[5050] = 32'd0;
    dmem[5051] = 32'd0;
    dmem[5052] = 32'd0;
    dmem[5053] = 32'd0;
    dmem[5054] = 32'd0;
    dmem[5055] = 32'd0;
    dmem[5056] = 32'd0;
    dmem[5057] = 32'd0;
    dmem[5058] = 32'd0;
    dmem[5059] = 32'd0;
    dmem[5060] = 32'd0;
    dmem[5061] = 32'd0;
    dmem[5062] = 32'd0;
    dmem[5063] = 32'd0;
    dmem[5064] = 32'd0;
    dmem[5065] = 32'd0;
    dmem[5066] = 32'd0;
    dmem[5067] = 32'd0;
    dmem[5068] = 32'd0;
    dmem[5069] = 32'd0;
    dmem[5070] = 32'd0;
    dmem[5071] = 32'd0;
    dmem[5072] = 32'd0;
    dmem[5073] = 32'd0;
    dmem[5074] = 32'd0;
    dmem[5075] = 32'd0;
    dmem[5076] = 32'd0;
    dmem[5077] = 32'd0;
    dmem[5078] = 32'd0;
    dmem[5079] = 32'd0;
    dmem[5080] = 32'd0;
    dmem[5081] = 32'd0;
    dmem[5082] = 32'd0;
    dmem[5083] = 32'd0;
    dmem[5084] = 32'd0;
    dmem[5085] = 32'd0;
    dmem[5086] = 32'd0;
    dmem[5087] = 32'd0;
    dmem[5088] = 32'd0;
    dmem[5089] = 32'd0;
    dmem[5090] = 32'd0;
    dmem[5091] = 32'd0;
    dmem[5092] = 32'd0;
    dmem[5093] = 32'd0;
    dmem[5094] = 32'd0;
    dmem[5095] = 32'd0;
    dmem[5096] = 32'd0;
    dmem[5097] = 32'd0;
    dmem[5098] = 32'd0;
    dmem[5099] = 32'd0;
    dmem[5100] = 32'd0;
    dmem[5101] = 32'd0;
    dmem[5102] = 32'd0;
    dmem[5103] = 32'd0;
    dmem[5104] = 32'd0;
    dmem[5105] = 32'd0;
    dmem[5106] = 32'd0;
    dmem[5107] = 32'd0;
    dmem[5108] = 32'd0;
    dmem[5109] = 32'd0;
    dmem[5110] = 32'd0;
    dmem[5111] = 32'd0;
    dmem[5112] = 32'd0;
    dmem[5113] = 32'd0;
    dmem[5114] = 32'd0;
    dmem[5115] = 32'd0;
    dmem[5116] = 32'd0;
    dmem[5117] = 32'd0;
    dmem[5118] = 32'd0;
    dmem[5119] = 32'd0;
    dmem[5120] = 32'd0;
    dmem[5121] = 32'd0;
    dmem[5122] = 32'd0;
    dmem[5123] = 32'd0;
    dmem[5124] = 32'd0;
    dmem[5125] = 32'd0;
    dmem[5126] = 32'd0;
    dmem[5127] = 32'd0;
    dmem[5128] = 32'd0;
    dmem[5129] = 32'd0;
    dmem[5130] = 32'd0;
    dmem[5131] = 32'd0;
    dmem[5132] = 32'd0;
    dmem[5133] = 32'd0;
    dmem[5134] = 32'd0;
    dmem[5135] = 32'd0;
    dmem[5136] = 32'd0;
    dmem[5137] = 32'd0;
    dmem[5138] = 32'd0;
    dmem[5139] = 32'd0;
    dmem[5140] = 32'd0;
    dmem[5141] = 32'd0;
    dmem[5142] = 32'd0;
    dmem[5143] = 32'd0;
    dmem[5144] = 32'd0;
    dmem[5145] = 32'd0;
    dmem[5146] = 32'd0;
    dmem[5147] = 32'd0;
    dmem[5148] = 32'd0;
    dmem[5149] = 32'd0;
    dmem[5150] = 32'd0;
    dmem[5151] = 32'd0;
    dmem[5152] = 32'd0;
    dmem[5153] = 32'd0;
    dmem[5154] = 32'd0;
    dmem[5155] = 32'd0;
    dmem[5156] = 32'd0;
    dmem[5157] = 32'd0;
    dmem[5158] = 32'd0;
    dmem[5159] = 32'd0;
    dmem[5160] = 32'd0;
    dmem[5161] = 32'd0;
    dmem[5162] = 32'd0;
    dmem[5163] = 32'd0;
    dmem[5164] = 32'd0;
    dmem[5165] = 32'd0;
    dmem[5166] = 32'd0;
    dmem[5167] = 32'd0;
    dmem[5168] = 32'd0;
    dmem[5169] = 32'd0;
    dmem[5170] = 32'd0;
    dmem[5171] = 32'd0;
    dmem[5172] = 32'd0;
    dmem[5173] = 32'd0;
    dmem[5174] = 32'd0;
    dmem[5175] = 32'd0;
    dmem[5176] = 32'd0;
    dmem[5177] = 32'd0;
    dmem[5178] = 32'd0;
    dmem[5179] = 32'd0;
    dmem[5180] = 32'd0;
    dmem[5181] = 32'd0;
    dmem[5182] = 32'd0;
    dmem[5183] = 32'd0;
    dmem[5184] = 32'd0;
    dmem[5185] = 32'd0;
    dmem[5186] = 32'd0;
    dmem[5187] = 32'd0;
    dmem[5188] = 32'd0;
    dmem[5189] = 32'd0;
    dmem[5190] = 32'd0;
    dmem[5191] = 32'd0;
    dmem[5192] = 32'd0;
    dmem[5193] = 32'd0;
    dmem[5194] = 32'd0;
    dmem[5195] = 32'd0;
    dmem[5196] = 32'd0;
    dmem[5197] = 32'd0;
    dmem[5198] = 32'd0;
    dmem[5199] = 32'd0;
    dmem[5200] = 32'd0;
    dmem[5201] = 32'd0;
    dmem[5202] = 32'd0;
    dmem[5203] = 32'd0;
    dmem[5204] = 32'd0;
    dmem[5205] = 32'd0;
    dmem[5206] = 32'd0;
    dmem[5207] = 32'd0;
    dmem[5208] = 32'd0;
    dmem[5209] = 32'd0;
    dmem[5210] = 32'd0;
    dmem[5211] = 32'd0;
    dmem[5212] = 32'd0;
    dmem[5213] = 32'd0;
    dmem[5214] = 32'd0;
    dmem[5215] = 32'd0;
    dmem[5216] = 32'd0;
    dmem[5217] = 32'd0;
    dmem[5218] = 32'd0;
    dmem[5219] = 32'd0;
    dmem[5220] = 32'd0;
    dmem[5221] = 32'd0;
    dmem[5222] = 32'd0;
    dmem[5223] = 32'd0;
    dmem[5224] = 32'd0;
    dmem[5225] = 32'd0;
    dmem[5226] = 32'd0;
    dmem[5227] = 32'd0;
    dmem[5228] = 32'd0;
    dmem[5229] = 32'd0;
    dmem[5230] = 32'd0;
    dmem[5231] = 32'd0;
    dmem[5232] = 32'd0;
    dmem[5233] = 32'd0;
    dmem[5234] = 32'd0;
    dmem[5235] = 32'd0;
    dmem[5236] = 32'd0;
    dmem[5237] = 32'd0;
    dmem[5238] = 32'd0;
    dmem[5239] = 32'd0;
    dmem[5240] = 32'd0;
    dmem[5241] = 32'd0;
    dmem[5242] = 32'd0;
    dmem[5243] = 32'd0;
    dmem[5244] = 32'd0;
    dmem[5245] = 32'd0;
    dmem[5246] = 32'd0;
    dmem[5247] = 32'd0;
    dmem[5248] = 32'd0;
    dmem[5249] = 32'd0;
    dmem[5250] = 32'd0;
    dmem[5251] = 32'd0;
    dmem[5252] = 32'd0;
    dmem[5253] = 32'd0;
    dmem[5254] = 32'd0;
    dmem[5255] = 32'd0;
    dmem[5256] = 32'd0;
    dmem[5257] = 32'd0;
    dmem[5258] = 32'd0;
    dmem[5259] = 32'd0;
    dmem[5260] = 32'd0;
    dmem[5261] = 32'd0;
    dmem[5262] = 32'd0;
    dmem[5263] = 32'd0;
    dmem[5264] = 32'd0;
    dmem[5265] = 32'd0;
    dmem[5266] = 32'd0;
    dmem[5267] = 32'd0;
    dmem[5268] = 32'd0;
    dmem[5269] = 32'd0;
    dmem[5270] = 32'd0;
    dmem[5271] = 32'd0;
    dmem[5272] = 32'd0;
    dmem[5273] = 32'd0;
    dmem[5274] = 32'd0;
    dmem[5275] = 32'd0;
    dmem[5276] = 32'd0;
    dmem[5277] = 32'd0;
    dmem[5278] = 32'd0;
    dmem[5279] = 32'd0;
    dmem[5280] = 32'd0;
    dmem[5281] = 32'd0;
    dmem[5282] = 32'd0;
    dmem[5283] = 32'd0;
    dmem[5284] = 32'd0;
    dmem[5285] = 32'd0;
    dmem[5286] = 32'd0;
    dmem[5287] = 32'd0;
    dmem[5288] = 32'd0;
    dmem[5289] = 32'd0;
    dmem[5290] = 32'd0;
    dmem[5291] = 32'd0;
    dmem[5292] = 32'd0;
    dmem[5293] = 32'd0;
    dmem[5294] = 32'd0;
    dmem[5295] = 32'd0;
    dmem[5296] = 32'd0;
    dmem[5297] = 32'd0;
    dmem[5298] = 32'd0;
    dmem[5299] = 32'd0;
    dmem[5300] = 32'd0;
    dmem[5301] = 32'd0;
    dmem[5302] = 32'd0;
    dmem[5303] = 32'd0;
    dmem[5304] = 32'd0;
    dmem[5305] = 32'd0;
    dmem[5306] = 32'd0;
    dmem[5307] = 32'd0;
    dmem[5308] = 32'd0;
    dmem[5309] = 32'd0;
    dmem[5310] = 32'd0;
    dmem[5311] = 32'd0;
    dmem[5312] = 32'd0;
    dmem[5313] = 32'd0;
    dmem[5314] = 32'd0;
    dmem[5315] = 32'd0;
    dmem[5316] = 32'd0;
    dmem[5317] = 32'd0;
    dmem[5318] = 32'd0;
    dmem[5319] = 32'd0;
    dmem[5320] = 32'd0;
    dmem[5321] = 32'd0;
    dmem[5322] = 32'd0;
    dmem[5323] = 32'd0;
    dmem[5324] = 32'd0;
    dmem[5325] = 32'd0;
    dmem[5326] = 32'd0;
    dmem[5327] = 32'd0;
    dmem[5328] = 32'd0;
    dmem[5329] = 32'd0;
    dmem[5330] = 32'd0;
    dmem[5331] = 32'd0;
    dmem[5332] = 32'd0;
    dmem[5333] = 32'd0;
    dmem[5334] = 32'd0;
    dmem[5335] = 32'd0;
    dmem[5336] = 32'd0;
    dmem[5337] = 32'd0;
    dmem[5338] = 32'd0;
    dmem[5339] = 32'd0;
    dmem[5340] = 32'd0;
    dmem[5341] = 32'd0;
    dmem[5342] = 32'd0;
    dmem[5343] = 32'd0;
    dmem[5344] = 32'd0;
    dmem[5345] = 32'd0;
    dmem[5346] = 32'd0;
    dmem[5347] = 32'd0;
    dmem[5348] = 32'd0;
    dmem[5349] = 32'd0;
    dmem[5350] = 32'd0;
    dmem[5351] = 32'd0;
    dmem[5352] = 32'd0;
    dmem[5353] = 32'd0;
    dmem[5354] = 32'd0;
    dmem[5355] = 32'd0;
    dmem[5356] = 32'd0;
    dmem[5357] = 32'd0;
    dmem[5358] = 32'd0;
    dmem[5359] = 32'd0;
    dmem[5360] = 32'd0;
    dmem[5361] = 32'd0;
    dmem[5362] = 32'd0;
    dmem[5363] = 32'd0;
    dmem[5364] = 32'd0;
    dmem[5365] = 32'd0;
    dmem[5366] = 32'd0;
    dmem[5367] = 32'd0;
    dmem[5368] = 32'd0;
    dmem[5369] = 32'd0;
    dmem[5370] = 32'd0;
    dmem[5371] = 32'd0;
    dmem[5372] = 32'd0;
    dmem[5373] = 32'd0;
    dmem[5374] = 32'd0;
    dmem[5375] = 32'd0;
    dmem[5376] = 32'd0;
    dmem[5377] = 32'd0;
    dmem[5378] = 32'd0;
    dmem[5379] = 32'd0;
    dmem[5380] = 32'd0;
    dmem[5381] = 32'd0;
    dmem[5382] = 32'd0;
    dmem[5383] = 32'd0;
    dmem[5384] = 32'd0;
    dmem[5385] = 32'd0;
    dmem[5386] = 32'd0;
    dmem[5387] = 32'd0;
    dmem[5388] = 32'd0;
    dmem[5389] = 32'd0;
    dmem[5390] = 32'd0;
    dmem[5391] = 32'd0;
    dmem[5392] = 32'd0;
    dmem[5393] = 32'd0;
    dmem[5394] = 32'd0;
    dmem[5395] = 32'd0;
    dmem[5396] = 32'd0;
    dmem[5397] = 32'd0;
    dmem[5398] = 32'd0;
    dmem[5399] = 32'd0;
    dmem[5400] = 32'd0;
    dmem[5401] = 32'd0;
    dmem[5402] = 32'd0;
    dmem[5403] = 32'd0;
    dmem[5404] = 32'd0;
    dmem[5405] = 32'd0;
    dmem[5406] = 32'd0;
    dmem[5407] = 32'd0;
    dmem[5408] = 32'd0;
    dmem[5409] = 32'd0;
    dmem[5410] = 32'd0;
    dmem[5411] = 32'd0;
    dmem[5412] = 32'd0;
    dmem[5413] = 32'd0;
    dmem[5414] = 32'd0;
    dmem[5415] = 32'd0;
    dmem[5416] = 32'd0;
    dmem[5417] = 32'd0;
    dmem[5418] = 32'd0;
    dmem[5419] = 32'd0;
    dmem[5420] = 32'd0;
    dmem[5421] = 32'd0;
    dmem[5422] = 32'd0;
    dmem[5423] = 32'd0;
    dmem[5424] = 32'd0;
    dmem[5425] = 32'd0;
    dmem[5426] = 32'd0;
    dmem[5427] = 32'd0;
    dmem[5428] = 32'd0;
    dmem[5429] = 32'd0;
    dmem[5430] = 32'd0;
    dmem[5431] = 32'd0;
    dmem[5432] = 32'd0;
    dmem[5433] = 32'd0;
    dmem[5434] = 32'd0;
    dmem[5435] = 32'd0;
    dmem[5436] = 32'd0;
    dmem[5437] = 32'd0;
    dmem[5438] = 32'd0;
    dmem[5439] = 32'd0;
    dmem[5440] = 32'd0;
    dmem[5441] = 32'd0;
    dmem[5442] = 32'd0;
    dmem[5443] = 32'd0;
    dmem[5444] = 32'd0;
    dmem[5445] = 32'd0;
    dmem[5446] = 32'd0;
    dmem[5447] = 32'd0;
    dmem[5448] = 32'd0;
    dmem[5449] = 32'd0;
    dmem[5450] = 32'd0;
    dmem[5451] = 32'd0;
    dmem[5452] = 32'd0;
    dmem[5453] = 32'd0;
    dmem[5454] = 32'd0;
    dmem[5455] = 32'd0;
    dmem[5456] = 32'd0;
    dmem[5457] = 32'd0;
    dmem[5458] = 32'd0;
    dmem[5459] = 32'd0;
    dmem[5460] = 32'd0;
    dmem[5461] = 32'd0;
    dmem[5462] = 32'd0;
    dmem[5463] = 32'd0;
    dmem[5464] = 32'd0;
    dmem[5465] = 32'd0;
    dmem[5466] = 32'd0;
    dmem[5467] = 32'd0;
    dmem[5468] = 32'd0;
    dmem[5469] = 32'd0;
    dmem[5470] = 32'd0;
    dmem[5471] = 32'd0;
    dmem[5472] = 32'd0;
    dmem[5473] = 32'd0;
    dmem[5474] = 32'd0;
    dmem[5475] = 32'd0;
    dmem[5476] = 32'd0;
    dmem[5477] = 32'd0;
    dmem[5478] = 32'd0;
    dmem[5479] = 32'd0;
    dmem[5480] = 32'd0;
    dmem[5481] = 32'd0;
    dmem[5482] = 32'd0;
    dmem[5483] = 32'd0;
    dmem[5484] = 32'd0;
    dmem[5485] = 32'd0;
    dmem[5486] = 32'd0;
    dmem[5487] = 32'd0;
    dmem[5488] = 32'd0;
    dmem[5489] = 32'd0;
    dmem[5490] = 32'd0;
    dmem[5491] = 32'd0;
    dmem[5492] = 32'd0;
    dmem[5493] = 32'd0;
    dmem[5494] = 32'd0;
    dmem[5495] = 32'd0;
    dmem[5496] = 32'd0;
    dmem[5497] = 32'd0;
    dmem[5498] = 32'd0;
    dmem[5499] = 32'd0;
    dmem[5500] = 32'd0;
    dmem[5501] = 32'd0;
    dmem[5502] = 32'd0;
    dmem[5503] = 32'd0;
    dmem[5504] = 32'd0;
    dmem[5505] = 32'd0;
    dmem[5506] = 32'd0;
    dmem[5507] = 32'd0;
    dmem[5508] = 32'd0;
    dmem[5509] = 32'd0;
    dmem[5510] = 32'd0;
    dmem[5511] = 32'd0;
    dmem[5512] = 32'd0;
    dmem[5513] = 32'd0;
    dmem[5514] = 32'd0;
    dmem[5515] = 32'd0;
    dmem[5516] = 32'd0;
    dmem[5517] = 32'd0;
    dmem[5518] = 32'd0;
    dmem[5519] = 32'd0;
    dmem[5520] = 32'd0;
    dmem[5521] = 32'd0;
    dmem[5522] = 32'd0;
    dmem[5523] = 32'd0;
    dmem[5524] = 32'd0;
    dmem[5525] = 32'd0;
    dmem[5526] = 32'd0;
    dmem[5527] = 32'd0;
    dmem[5528] = 32'd0;
    dmem[5529] = 32'd0;
    dmem[5530] = 32'd0;
    dmem[5531] = 32'd0;
    dmem[5532] = 32'd0;
    dmem[5533] = 32'd0;
    dmem[5534] = 32'd0;
    dmem[5535] = 32'd0;
    dmem[5536] = 32'd0;
    dmem[5537] = 32'd0;
    dmem[5538] = 32'd0;
    dmem[5539] = 32'd0;
    dmem[5540] = 32'd0;
    dmem[5541] = 32'd0;
    dmem[5542] = 32'd0;
    dmem[5543] = 32'd0;
    dmem[5544] = 32'd0;
    dmem[5545] = 32'd0;
    dmem[5546] = 32'd0;
    dmem[5547] = 32'd0;
    dmem[5548] = 32'd0;
    dmem[5549] = 32'd0;
    dmem[5550] = 32'd0;
    dmem[5551] = 32'd0;
    dmem[5552] = 32'd0;
    dmem[5553] = 32'd0;
    dmem[5554] = 32'd0;
    dmem[5555] = 32'd0;
    dmem[5556] = 32'd0;
    dmem[5557] = 32'd0;
    dmem[5558] = 32'd0;
    dmem[5559] = 32'd0;
    dmem[5560] = 32'd0;
    dmem[5561] = 32'd0;
    dmem[5562] = 32'd0;
    dmem[5563] = 32'd0;
    dmem[5564] = 32'd0;
    dmem[5565] = 32'd0;
    dmem[5566] = 32'd0;
    dmem[5567] = 32'd0;
    dmem[5568] = 32'd0;
    dmem[5569] = 32'd0;
    dmem[5570] = 32'd0;
    dmem[5571] = 32'd0;
    dmem[5572] = 32'd0;
    dmem[5573] = 32'd0;
    dmem[5574] = 32'd0;
    dmem[5575] = 32'd0;
    dmem[5576] = 32'd0;
    dmem[5577] = 32'd0;
    dmem[5578] = 32'd0;
    dmem[5579] = 32'd0;
    dmem[5580] = 32'd0;
    dmem[5581] = 32'd0;
    dmem[5582] = 32'd0;
    dmem[5583] = 32'd0;
    dmem[5584] = 32'd0;
    dmem[5585] = 32'd0;
    dmem[5586] = 32'd0;
    dmem[5587] = 32'd0;
    dmem[5588] = 32'd0;
    dmem[5589] = 32'd0;
    dmem[5590] = 32'd0;
    dmem[5591] = 32'd0;
    dmem[5592] = 32'd0;
    dmem[5593] = 32'd0;
    dmem[5594] = 32'd0;
    dmem[5595] = 32'd0;
    dmem[5596] = 32'd0;
    dmem[5597] = 32'd0;
    dmem[5598] = 32'd0;
    dmem[5599] = 32'd0;
    dmem[5600] = 32'd0;
    dmem[5601] = 32'd0;
    dmem[5602] = 32'd0;
    dmem[5603] = 32'd0;
    dmem[5604] = 32'd0;
    dmem[5605] = 32'd0;
    dmem[5606] = 32'd0;
    dmem[5607] = 32'd0;
    dmem[5608] = 32'd0;
    dmem[5609] = 32'd0;
    dmem[5610] = 32'd0;
    dmem[5611] = 32'd0;
    dmem[5612] = 32'd0;
    dmem[5613] = 32'd0;
    dmem[5614] = 32'd0;
    dmem[5615] = 32'd0;
    dmem[5616] = 32'd0;
    dmem[5617] = 32'd0;
    dmem[5618] = 32'd0;
    dmem[5619] = 32'd0;
    dmem[5620] = 32'd0;
    dmem[5621] = 32'd0;
    dmem[5622] = 32'd0;
    dmem[5623] = 32'd0;
    dmem[5624] = 32'd0;
    dmem[5625] = 32'd0;
    dmem[5626] = 32'd0;
    dmem[5627] = 32'd0;
    dmem[5628] = 32'd0;
    dmem[5629] = 32'd0;
    dmem[5630] = 32'd0;
    dmem[5631] = 32'd0;
    dmem[5632] = 32'd0;
    dmem[5633] = 32'd0;
    dmem[5634] = 32'd0;
    dmem[5635] = 32'd0;
    dmem[5636] = 32'd0;
    dmem[5637] = 32'd0;
    dmem[5638] = 32'd0;
    dmem[5639] = 32'd0;
    dmem[5640] = 32'd0;
    dmem[5641] = 32'd0;
    dmem[5642] = 32'd0;
    dmem[5643] = 32'd0;
    dmem[5644] = 32'd0;
    dmem[5645] = 32'd0;
    dmem[5646] = 32'd0;
    dmem[5647] = 32'd0;
    dmem[5648] = 32'd0;
    dmem[5649] = 32'd0;
    dmem[5650] = 32'd0;
    dmem[5651] = 32'd0;
    dmem[5652] = 32'd0;
    dmem[5653] = 32'd0;
    dmem[5654] = 32'd0;
    dmem[5655] = 32'd0;
    dmem[5656] = 32'd0;
    dmem[5657] = 32'd0;
    dmem[5658] = 32'd0;
    dmem[5659] = 32'd0;
    dmem[5660] = 32'd0;
    dmem[5661] = 32'd0;
    dmem[5662] = 32'd0;
    dmem[5663] = 32'd0;
    dmem[5664] = 32'd0;
    dmem[5665] = 32'd0;
    dmem[5666] = 32'd0;
    dmem[5667] = 32'd0;
    dmem[5668] = 32'd0;
    dmem[5669] = 32'd0;
    dmem[5670] = 32'd0;
    dmem[5671] = 32'd0;
    dmem[5672] = 32'd0;
    dmem[5673] = 32'd0;
    dmem[5674] = 32'd0;
    dmem[5675] = 32'd0;
    dmem[5676] = 32'd0;
    dmem[5677] = 32'd0;
    dmem[5678] = 32'd0;
    dmem[5679] = 32'd0;
    dmem[5680] = 32'd0;
    dmem[5681] = 32'd0;
    dmem[5682] = 32'd0;
    dmem[5683] = 32'd0;
    dmem[5684] = 32'd0;
    dmem[5685] = 32'd0;
    dmem[5686] = 32'd0;
    dmem[5687] = 32'd0;
    dmem[5688] = 32'd0;
    dmem[5689] = 32'd0;
    dmem[5690] = 32'd0;
    dmem[5691] = 32'd0;
    dmem[5692] = 32'd0;
    dmem[5693] = 32'd0;
    dmem[5694] = 32'd0;
    dmem[5695] = 32'd0;
    dmem[5696] = 32'd0;
    dmem[5697] = 32'd0;
    dmem[5698] = 32'd0;
    dmem[5699] = 32'd0;
    dmem[5700] = 32'd0;
    dmem[5701] = 32'd0;
    dmem[5702] = 32'd0;
    dmem[5703] = 32'd0;
    dmem[5704] = 32'd0;
    dmem[5705] = 32'd0;
    dmem[5706] = 32'd0;
    dmem[5707] = 32'd0;
    dmem[5708] = 32'd0;
    dmem[5709] = 32'd0;
    dmem[5710] = 32'd0;
    dmem[5711] = 32'd0;
    dmem[5712] = 32'd0;
    dmem[5713] = 32'd0;
    dmem[5714] = 32'd0;
    dmem[5715] = 32'd0;
    dmem[5716] = 32'd0;
    dmem[5717] = 32'd0;
    dmem[5718] = 32'd0;
    dmem[5719] = 32'd0;
    dmem[5720] = 32'd0;
    dmem[5721] = 32'd0;
    dmem[5722] = 32'd0;
    dmem[5723] = 32'd0;
    dmem[5724] = 32'd0;
    dmem[5725] = 32'd0;
    dmem[5726] = 32'd0;
    dmem[5727] = 32'd0;
    dmem[5728] = 32'd0;
    dmem[5729] = 32'd0;
    dmem[5730] = 32'd0;
    dmem[5731] = 32'd0;
    dmem[5732] = 32'd0;
    dmem[5733] = 32'd0;
    dmem[5734] = 32'd0;
    dmem[5735] = 32'd0;
    dmem[5736] = 32'd0;
    dmem[5737] = 32'd0;
    dmem[5738] = 32'd0;
    dmem[5739] = 32'd0;
    dmem[5740] = 32'd0;
    dmem[5741] = 32'd0;
    dmem[5742] = 32'd0;
    dmem[5743] = 32'd0;
    dmem[5744] = 32'd0;
    dmem[5745] = 32'd0;
    dmem[5746] = 32'd0;
    dmem[5747] = 32'd0;
    dmem[5748] = 32'd0;
    dmem[5749] = 32'd0;
    dmem[5750] = 32'd0;
    dmem[5751] = 32'd0;
    dmem[5752] = 32'd0;
    dmem[5753] = 32'd0;
    dmem[5754] = 32'd0;
    dmem[5755] = 32'd0;
    dmem[5756] = 32'd0;
    dmem[5757] = 32'd0;
    dmem[5758] = 32'd0;
    dmem[5759] = 32'd0;
    dmem[5760] = 32'd0;
    dmem[5761] = 32'd0;
    dmem[5762] = 32'd0;
    dmem[5763] = 32'd0;
    dmem[5764] = 32'd0;
    dmem[5765] = 32'd0;
    dmem[5766] = 32'd0;
    dmem[5767] = 32'd0;
    dmem[5768] = 32'd0;
    dmem[5769] = 32'd0;
    dmem[5770] = 32'd0;
    dmem[5771] = 32'd0;
    dmem[5772] = 32'd0;
    dmem[5773] = 32'd0;
    dmem[5774] = 32'd0;
    dmem[5775] = 32'd0;
    dmem[5776] = 32'd0;
    dmem[5777] = 32'd0;
    dmem[5778] = 32'd0;
    dmem[5779] = 32'd0;
    dmem[5780] = 32'd0;
    dmem[5781] = 32'd0;
    dmem[5782] = 32'd0;
    dmem[5783] = 32'd0;
    dmem[5784] = 32'd0;
    dmem[5785] = 32'd0;
    dmem[5786] = 32'd0;
    dmem[5787] = 32'd0;
    dmem[5788] = 32'd0;
    dmem[5789] = 32'd0;
    dmem[5790] = 32'd0;
    dmem[5791] = 32'd0;
    dmem[5792] = 32'd0;
    dmem[5793] = 32'd0;
    dmem[5794] = 32'd0;
    dmem[5795] = 32'd0;
    dmem[5796] = 32'd0;
    dmem[5797] = 32'd0;
    dmem[5798] = 32'd0;
    dmem[5799] = 32'd0;
    dmem[5800] = 32'd0;
    dmem[5801] = 32'd0;
    dmem[5802] = 32'd0;
    dmem[5803] = 32'd0;
    dmem[5804] = 32'd0;
    dmem[5805] = 32'd0;
    dmem[5806] = 32'd0;
    dmem[5807] = 32'd0;
    dmem[5808] = 32'd0;
    dmem[5809] = 32'd0;
    dmem[5810] = 32'd0;
    dmem[5811] = 32'd0;
    dmem[5812] = 32'd0;
    dmem[5813] = 32'd0;
    dmem[5814] = 32'd0;
    dmem[5815] = 32'd0;
    dmem[5816] = 32'd0;
    dmem[5817] = 32'd0;
    dmem[5818] = 32'd0;
    dmem[5819] = 32'd0;
    dmem[5820] = 32'd0;
    dmem[5821] = 32'd0;
    dmem[5822] = 32'd0;
    dmem[5823] = 32'd0;
    dmem[5824] = 32'd0;
    dmem[5825] = 32'd0;
    dmem[5826] = 32'd0;
    dmem[5827] = 32'd0;
    dmem[5828] = 32'd0;
    dmem[5829] = 32'd0;
    dmem[5830] = 32'd0;
    dmem[5831] = 32'd0;
    dmem[5832] = 32'd0;
    dmem[5833] = 32'd0;
    dmem[5834] = 32'd0;
    dmem[5835] = 32'd0;
    dmem[5836] = 32'd0;
    dmem[5837] = 32'd0;
    dmem[5838] = 32'd0;
    dmem[5839] = 32'd0;
    dmem[5840] = 32'd0;
    dmem[5841] = 32'd0;
    dmem[5842] = 32'd0;
    dmem[5843] = 32'd0;
    dmem[5844] = 32'd0;
    dmem[5845] = 32'd0;
    dmem[5846] = 32'd0;
    dmem[5847] = 32'd0;
    dmem[5848] = 32'd0;
    dmem[5849] = 32'd0;
    dmem[5850] = 32'd0;
    dmem[5851] = 32'd0;
    dmem[5852] = 32'd0;
    dmem[5853] = 32'd0;
    dmem[5854] = 32'd0;
    dmem[5855] = 32'd0;
    dmem[5856] = 32'd0;
    dmem[5857] = 32'd0;
    dmem[5858] = 32'd0;
    dmem[5859] = 32'd0;
    dmem[5860] = 32'd0;
    dmem[5861] = 32'd0;
    dmem[5862] = 32'd0;
    dmem[5863] = 32'd0;
    dmem[5864] = 32'd0;
    dmem[5865] = 32'd0;
    dmem[5866] = 32'd0;
    dmem[5867] = 32'd0;
    dmem[5868] = 32'd0;
    dmem[5869] = 32'd0;
    dmem[5870] = 32'd0;
    dmem[5871] = 32'd0;
    dmem[5872] = 32'd0;
    dmem[5873] = 32'd0;
    dmem[5874] = 32'd0;
    dmem[5875] = 32'd0;
    dmem[5876] = 32'd0;
    dmem[5877] = 32'd0;
    dmem[5878] = 32'd0;
    dmem[5879] = 32'd0;
    dmem[5880] = 32'd0;
    dmem[5881] = 32'd0;
    dmem[5882] = 32'd0;
    dmem[5883] = 32'd0;
    dmem[5884] = 32'd0;
    dmem[5885] = 32'd0;
    dmem[5886] = 32'd0;
    dmem[5887] = 32'd0;
    dmem[5888] = 32'd0;
    dmem[5889] = 32'd0;
    dmem[5890] = 32'd0;
    dmem[5891] = 32'd0;
    dmem[5892] = 32'd0;
    dmem[5893] = 32'd0;
    dmem[5894] = 32'd0;
    dmem[5895] = 32'd0;
    dmem[5896] = 32'd0;
    dmem[5897] = 32'd0;
    dmem[5898] = 32'd0;
    dmem[5899] = 32'd0;
    dmem[5900] = 32'd0;
    dmem[5901] = 32'd0;
    dmem[5902] = 32'd0;
    dmem[5903] = 32'd0;
    dmem[5904] = 32'd0;
    dmem[5905] = 32'd0;
    dmem[5906] = 32'd0;
    dmem[5907] = 32'd0;
    dmem[5908] = 32'd0;
    dmem[5909] = 32'd0;
    dmem[5910] = 32'd0;
    dmem[5911] = 32'd0;
    dmem[5912] = 32'd0;
    dmem[5913] = 32'd0;
    dmem[5914] = 32'd0;
    dmem[5915] = 32'd0;
    dmem[5916] = 32'd0;
    dmem[5917] = 32'd0;
    dmem[5918] = 32'd0;
    dmem[5919] = 32'd0;
    dmem[5920] = 32'd0;
    dmem[5921] = 32'd0;
    dmem[5922] = 32'd0;
    dmem[5923] = 32'd0;
    dmem[5924] = 32'd0;
    dmem[5925] = 32'd0;
    dmem[5926] = 32'd0;
    dmem[5927] = 32'd0;
    dmem[5928] = 32'd0;
    dmem[5929] = 32'd0;
    dmem[5930] = 32'd0;
    dmem[5931] = 32'd0;
    dmem[5932] = 32'd0;
    dmem[5933] = 32'd0;
    dmem[5934] = 32'd0;
    dmem[5935] = 32'd0;
    dmem[5936] = 32'd0;
    dmem[5937] = 32'd0;
    dmem[5938] = 32'd0;
    dmem[5939] = 32'd0;
    dmem[5940] = 32'd0;
    dmem[5941] = 32'd0;
    dmem[5942] = 32'd0;
    dmem[5943] = 32'd0;
    dmem[5944] = 32'd0;
    dmem[5945] = 32'd0;
    dmem[5946] = 32'd0;
    dmem[5947] = 32'd0;
    dmem[5948] = 32'd0;
    dmem[5949] = 32'd0;
    dmem[5950] = 32'd0;
    dmem[5951] = 32'd0;
    dmem[5952] = 32'd0;
    dmem[5953] = 32'd0;
    dmem[5954] = 32'd0;
    dmem[5955] = 32'd0;
    dmem[5956] = 32'd0;
    dmem[5957] = 32'd0;
    dmem[5958] = 32'd0;
    dmem[5959] = 32'd0;
    dmem[5960] = 32'd0;
    dmem[5961] = 32'd0;
    dmem[5962] = 32'd0;
    dmem[5963] = 32'd0;
    dmem[5964] = 32'd0;
    dmem[5965] = 32'd0;
    dmem[5966] = 32'd0;
    dmem[5967] = 32'd0;
    dmem[5968] = 32'd0;
    dmem[5969] = 32'd0;
    dmem[5970] = 32'd0;
    dmem[5971] = 32'd0;
    dmem[5972] = 32'd0;
    dmem[5973] = 32'd0;
    dmem[5974] = 32'd0;
    dmem[5975] = 32'd0;
    dmem[5976] = 32'd0;
    dmem[5977] = 32'd0;
    dmem[5978] = 32'd0;
    dmem[5979] = 32'd0;
    dmem[5980] = 32'd0;
    dmem[5981] = 32'd0;
    dmem[5982] = 32'd0;
    dmem[5983] = 32'd0;
    dmem[5984] = 32'd0;
    dmem[5985] = 32'd0;
    dmem[5986] = 32'd0;
    dmem[5987] = 32'd0;
    dmem[5988] = 32'd0;
    dmem[5989] = 32'd0;
    dmem[5990] = 32'd0;
    dmem[5991] = 32'd0;
    dmem[5992] = 32'd0;
    dmem[5993] = 32'd0;
    dmem[5994] = 32'd0;
    dmem[5995] = 32'd0;
    dmem[5996] = 32'd0;
    dmem[5997] = 32'd0;
    dmem[5998] = 32'd0;
    dmem[5999] = 32'd0;
    dmem[6000] = 32'd0;
    dmem[6001] = 32'd0;
    dmem[6002] = 32'd0;
    dmem[6003] = 32'd0;
    dmem[6004] = 32'd0;
    dmem[6005] = 32'd0;
    dmem[6006] = 32'd0;
    dmem[6007] = 32'd0;
    dmem[6008] = 32'd0;
    dmem[6009] = 32'd0;
    dmem[6010] = 32'd0;
    dmem[6011] = 32'd0;
    dmem[6012] = 32'd0;
    dmem[6013] = 32'd0;
    dmem[6014] = 32'd0;
    dmem[6015] = 32'd0;
    dmem[6016] = 32'd0;
    dmem[6017] = 32'd0;
    dmem[6018] = 32'd0;
    dmem[6019] = 32'd0;
    dmem[6020] = 32'd0;
    dmem[6021] = 32'd0;
    dmem[6022] = 32'd0;
    dmem[6023] = 32'd0;
    dmem[6024] = 32'd0;
    dmem[6025] = 32'd0;
    dmem[6026] = 32'd0;
    dmem[6027] = 32'd0;
    dmem[6028] = 32'd0;
    dmem[6029] = 32'd0;
    dmem[6030] = 32'd0;
    dmem[6031] = 32'd0;
    dmem[6032] = 32'd0;
    dmem[6033] = 32'd0;
    dmem[6034] = 32'd0;
    dmem[6035] = 32'd0;
    dmem[6036] = 32'd0;
    dmem[6037] = 32'd0;
    dmem[6038] = 32'd0;
    dmem[6039] = 32'd0;
    dmem[6040] = 32'd0;
    dmem[6041] = 32'd0;
    dmem[6042] = 32'd0;
    dmem[6043] = 32'd0;
    dmem[6044] = 32'd0;
    dmem[6045] = 32'd0;
    dmem[6046] = 32'd0;
    dmem[6047] = 32'd0;
    dmem[6048] = 32'd0;
    dmem[6049] = 32'd0;
    dmem[6050] = 32'd0;
    dmem[6051] = 32'd0;
    dmem[6052] = 32'd0;
    dmem[6053] = 32'd0;
    dmem[6054] = 32'd0;
    dmem[6055] = 32'd0;
    dmem[6056] = 32'd0;
    dmem[6057] = 32'd0;
    dmem[6058] = 32'd0;
    dmem[6059] = 32'd0;
    dmem[6060] = 32'd0;
    dmem[6061] = 32'd0;
    dmem[6062] = 32'd0;
    dmem[6063] = 32'd0;
    dmem[6064] = 32'd0;
    dmem[6065] = 32'd0;
    dmem[6066] = 32'd0;
    dmem[6067] = 32'd0;
    dmem[6068] = 32'd0;
    dmem[6069] = 32'd0;
    dmem[6070] = 32'd0;
    dmem[6071] = 32'd0;
    dmem[6072] = 32'd0;
    dmem[6073] = 32'd0;
    dmem[6074] = 32'd0;
    dmem[6075] = 32'd0;
    dmem[6076] = 32'd0;
    dmem[6077] = 32'd0;
    dmem[6078] = 32'd0;
    dmem[6079] = 32'd0;
    dmem[6080] = 32'd0;
    dmem[6081] = 32'd0;
    dmem[6082] = 32'd0;
    dmem[6083] = 32'd0;
    dmem[6084] = 32'd0;
    dmem[6085] = 32'd0;
    dmem[6086] = 32'd0;
    dmem[6087] = 32'd0;
    dmem[6088] = 32'd0;
    dmem[6089] = 32'd0;
    dmem[6090] = 32'd0;
    dmem[6091] = 32'd0;
    dmem[6092] = 32'd0;
    dmem[6093] = 32'd0;
    dmem[6094] = 32'd0;
    dmem[6095] = 32'd0;
    dmem[6096] = 32'd0;
    dmem[6097] = 32'd0;
    dmem[6098] = 32'd0;
    dmem[6099] = 32'd0;
    dmem[6100] = 32'd0;
    dmem[6101] = 32'd0;
    dmem[6102] = 32'd0;
    dmem[6103] = 32'd0;
    dmem[6104] = 32'd0;
    dmem[6105] = 32'd0;
    dmem[6106] = 32'd0;
    dmem[6107] = 32'd0;
    dmem[6108] = 32'd0;
    dmem[6109] = 32'd0;
    dmem[6110] = 32'd0;
    dmem[6111] = 32'd0;
    dmem[6112] = 32'd0;
    dmem[6113] = 32'd0;
    dmem[6114] = 32'd0;
    dmem[6115] = 32'd0;
    dmem[6116] = 32'd0;
    dmem[6117] = 32'd0;
    dmem[6118] = 32'd0;
    dmem[6119] = 32'd0;
    dmem[6120] = 32'd0;
    dmem[6121] = 32'd0;
    dmem[6122] = 32'd0;
    dmem[6123] = 32'd0;
    dmem[6124] = 32'd0;
    dmem[6125] = 32'd0;
    dmem[6126] = 32'd0;
    dmem[6127] = 32'd0;
    dmem[6128] = 32'd0;
    dmem[6129] = 32'd0;
    dmem[6130] = 32'd0;
    dmem[6131] = 32'd0;
    dmem[6132] = 32'd0;
    dmem[6133] = 32'd0;
    dmem[6134] = 32'd0;
    dmem[6135] = 32'd0;
    dmem[6136] = 32'd0;
    dmem[6137] = 32'd0;
    dmem[6138] = 32'd0;
    dmem[6139] = 32'd0;
    dmem[6140] = 32'd0;
    dmem[6141] = 32'd0;
    dmem[6142] = 32'd0;
    dmem[6143] = 32'd0;
    dmem[6144] = 32'd0;
    dmem[6145] = 32'd0;
    dmem[6146] = 32'd0;
    dmem[6147] = 32'd0;
    dmem[6148] = 32'd0;
    dmem[6149] = 32'd0;
    dmem[6150] = 32'd0;
    dmem[6151] = 32'd0;
    dmem[6152] = 32'd0;
    dmem[6153] = 32'd0;
    dmem[6154] = 32'd0;
    dmem[6155] = 32'd0;
    dmem[6156] = 32'd0;
    dmem[6157] = 32'd0;
    dmem[6158] = 32'd0;
    dmem[6159] = 32'd0;
    dmem[6160] = 32'd0;
    dmem[6161] = 32'd0;
    dmem[6162] = 32'd0;
    dmem[6163] = 32'd0;
    dmem[6164] = 32'd0;
    dmem[6165] = 32'd0;
    dmem[6166] = 32'd0;
    dmem[6167] = 32'd0;
    dmem[6168] = 32'd0;
    dmem[6169] = 32'd0;
    dmem[6170] = 32'd0;
    dmem[6171] = 32'd0;
    dmem[6172] = 32'd0;
    dmem[6173] = 32'd0;
    dmem[6174] = 32'd0;
    dmem[6175] = 32'd0;
    dmem[6176] = 32'd0;
    dmem[6177] = 32'd0;
    dmem[6178] = 32'd0;
    dmem[6179] = 32'd0;
    dmem[6180] = 32'd0;
    dmem[6181] = 32'd0;
    dmem[6182] = 32'd0;
    dmem[6183] = 32'd0;
    dmem[6184] = 32'd0;
    dmem[6185] = 32'd0;
    dmem[6186] = 32'd0;
    dmem[6187] = 32'd0;
    dmem[6188] = 32'd0;
    dmem[6189] = 32'd0;
    dmem[6190] = 32'd0;
    dmem[6191] = 32'd0;
    dmem[6192] = 32'd0;
    dmem[6193] = 32'd0;
    dmem[6194] = 32'd0;
    dmem[6195] = 32'd0;
    dmem[6196] = 32'd0;
    dmem[6197] = 32'd0;
    dmem[6198] = 32'd0;
    dmem[6199] = 32'd0;
    dmem[6200] = 32'd0;
    dmem[6201] = 32'd0;
    dmem[6202] = 32'd0;
    dmem[6203] = 32'd0;
    dmem[6204] = 32'd0;
    dmem[6205] = 32'd0;
    dmem[6206] = 32'd0;
    dmem[6207] = 32'd0;
    dmem[6208] = 32'd0;
    dmem[6209] = 32'd0;
    dmem[6210] = 32'd0;
    dmem[6211] = 32'd0;
    dmem[6212] = 32'd0;
    dmem[6213] = 32'd0;
    dmem[6214] = 32'd0;
    dmem[6215] = 32'd0;
    dmem[6216] = 32'd0;
    dmem[6217] = 32'd0;
    dmem[6218] = 32'd0;
    dmem[6219] = 32'd0;
    dmem[6220] = 32'd0;
    dmem[6221] = 32'd0;
    dmem[6222] = 32'd0;
    dmem[6223] = 32'd0;
    dmem[6224] = 32'd0;
    dmem[6225] = 32'd0;
    dmem[6226] = 32'd0;
    dmem[6227] = 32'd0;
    dmem[6228] = 32'd0;
    dmem[6229] = 32'd0;
    dmem[6230] = 32'd0;
    dmem[6231] = 32'd0;
    dmem[6232] = 32'd0;
    dmem[6233] = 32'd0;
    dmem[6234] = 32'd0;
    dmem[6235] = 32'd0;
    dmem[6236] = 32'd0;
    dmem[6237] = 32'd0;
    dmem[6238] = 32'd0;
    dmem[6239] = 32'd0;
    dmem[6240] = 32'd0;
    dmem[6241] = 32'd0;
    dmem[6242] = 32'd0;
    dmem[6243] = 32'd0;
    dmem[6244] = 32'd0;
    dmem[6245] = 32'd0;
    dmem[6246] = 32'd0;
    dmem[6247] = 32'd0;
    dmem[6248] = 32'd0;
    dmem[6249] = 32'd0;
    dmem[6250] = 32'd0;
    dmem[6251] = 32'd0;
    dmem[6252] = 32'd0;
    dmem[6253] = 32'd0;
    dmem[6254] = 32'd0;
    dmem[6255] = 32'd0;
    dmem[6256] = 32'd0;
    dmem[6257] = 32'd0;
    dmem[6258] = 32'd0;
    dmem[6259] = 32'd0;
    dmem[6260] = 32'd0;
    dmem[6261] = 32'd0;
    dmem[6262] = 32'd0;
    dmem[6263] = 32'd0;
    dmem[6264] = 32'd0;
    dmem[6265] = 32'd0;
    dmem[6266] = 32'd0;
    dmem[6267] = 32'd0;
    dmem[6268] = 32'd0;
    dmem[6269] = 32'd0;
    dmem[6270] = 32'd0;
    dmem[6271] = 32'd0;
    dmem[6272] = 32'd0;
    dmem[6273] = 32'd0;
    dmem[6274] = 32'd0;
    dmem[6275] = 32'd0;
    dmem[6276] = 32'd0;
    dmem[6277] = 32'd0;
    dmem[6278] = 32'd0;
    dmem[6279] = 32'd0;
    dmem[6280] = 32'd0;
    dmem[6281] = 32'd0;
    dmem[6282] = 32'd0;
    dmem[6283] = 32'd0;
    dmem[6284] = 32'd0;
    dmem[6285] = 32'd0;
    dmem[6286] = 32'd0;
    dmem[6287] = 32'd0;
    dmem[6288] = 32'd0;
    dmem[6289] = 32'd0;
    dmem[6290] = 32'd0;
    dmem[6291] = 32'd0;
    dmem[6292] = 32'd0;
    dmem[6293] = 32'd0;
    dmem[6294] = 32'd0;
    dmem[6295] = 32'd0;
    dmem[6296] = 32'd0;
    dmem[6297] = 32'd0;
    dmem[6298] = 32'd0;
    dmem[6299] = 32'd0;
    dmem[6300] = 32'd0;
    dmem[6301] = 32'd0;
    dmem[6302] = 32'd0;
    dmem[6303] = 32'd0;
    dmem[6304] = 32'd0;
    dmem[6305] = 32'd0;
    dmem[6306] = 32'd0;
    dmem[6307] = 32'd0;
    dmem[6308] = 32'd0;
    dmem[6309] = 32'd0;
    dmem[6310] = 32'd0;
    dmem[6311] = 32'd0;
    dmem[6312] = 32'd0;
    dmem[6313] = 32'd0;
    dmem[6314] = 32'd0;
    dmem[6315] = 32'd0;
    dmem[6316] = 32'd0;
    dmem[6317] = 32'd0;
    dmem[6318] = 32'd0;
    dmem[6319] = 32'd0;
    dmem[6320] = 32'd0;
    dmem[6321] = 32'd0;
    dmem[6322] = 32'd0;
    dmem[6323] = 32'd0;
    dmem[6324] = 32'd0;
    dmem[6325] = 32'd0;
    dmem[6326] = 32'd0;
    dmem[6327] = 32'd0;
    dmem[6328] = 32'd0;
    dmem[6329] = 32'd0;
    dmem[6330] = 32'd0;
    dmem[6331] = 32'd0;
    dmem[6332] = 32'd0;
    dmem[6333] = 32'd0;
    dmem[6334] = 32'd0;
    dmem[6335] = 32'd0;
    dmem[6336] = 32'd0;
    dmem[6337] = 32'd0;
    dmem[6338] = 32'd0;
    dmem[6339] = 32'd0;
    dmem[6340] = 32'd0;
    dmem[6341] = 32'd0;
    dmem[6342] = 32'd0;
    dmem[6343] = 32'd0;
    dmem[6344] = 32'd0;
    dmem[6345] = 32'd0;
    dmem[6346] = 32'd0;
    dmem[6347] = 32'd0;
    dmem[6348] = 32'd0;
    dmem[6349] = 32'd0;
    dmem[6350] = 32'd0;
    dmem[6351] = 32'd0;
    dmem[6352] = 32'd0;
    dmem[6353] = 32'd0;
    dmem[6354] = 32'd0;
    dmem[6355] = 32'd0;
    dmem[6356] = 32'd0;
    dmem[6357] = 32'd0;
    dmem[6358] = 32'd0;
    dmem[6359] = 32'd0;
    dmem[6360] = 32'd0;
    dmem[6361] = 32'd0;
    dmem[6362] = 32'd0;
    dmem[6363] = 32'd0;
    dmem[6364] = 32'd0;
    dmem[6365] = 32'd0;
    dmem[6366] = 32'd0;
    dmem[6367] = 32'd0;
    dmem[6368] = 32'd0;
    dmem[6369] = 32'd0;
    dmem[6370] = 32'd0;
    dmem[6371] = 32'd0;
    dmem[6372] = 32'd0;
    dmem[6373] = 32'd0;
    dmem[6374] = 32'd0;
    dmem[6375] = 32'd0;
    dmem[6376] = 32'd0;
    dmem[6377] = 32'd0;
    dmem[6378] = 32'd0;
    dmem[6379] = 32'd0;
    dmem[6380] = 32'd0;
    dmem[6381] = 32'd0;
    dmem[6382] = 32'd0;
    dmem[6383] = 32'd0;
    dmem[6384] = 32'd0;
    dmem[6385] = 32'd0;
    dmem[6386] = 32'd0;
    dmem[6387] = 32'd0;
    dmem[6388] = 32'd0;
    dmem[6389] = 32'd0;
    dmem[6390] = 32'd0;
    dmem[6391] = 32'd0;
    dmem[6392] = 32'd0;
    dmem[6393] = 32'd0;
    dmem[6394] = 32'd0;
    dmem[6395] = 32'd0;
    dmem[6396] = 32'd0;
    dmem[6397] = 32'd0;
    dmem[6398] = 32'd0;
    dmem[6399] = 32'd0;
    dmem[6400] = 32'd0;
    dmem[6401] = 32'd0;
    dmem[6402] = 32'd0;
    dmem[6403] = 32'd0;
    dmem[6404] = 32'd0;
    dmem[6405] = 32'd0;
    dmem[6406] = 32'd0;
    dmem[6407] = 32'd0;
    dmem[6408] = 32'd0;
    dmem[6409] = 32'd0;
    dmem[6410] = 32'd0;
    dmem[6411] = 32'd0;
    dmem[6412] = 32'd0;
    dmem[6413] = 32'd0;
    dmem[6414] = 32'd0;
    dmem[6415] = 32'd0;
    dmem[6416] = 32'd0;
    dmem[6417] = 32'd0;
    dmem[6418] = 32'd0;
    dmem[6419] = 32'd0;
    dmem[6420] = 32'd0;
    dmem[6421] = 32'd0;
    dmem[6422] = 32'd0;
    dmem[6423] = 32'd0;
    dmem[6424] = 32'd0;
    dmem[6425] = 32'd0;
    dmem[6426] = 32'd0;
    dmem[6427] = 32'd0;
    dmem[6428] = 32'd0;
    dmem[6429] = 32'd0;
    dmem[6430] = 32'd0;
    dmem[6431] = 32'd0;
    dmem[6432] = 32'd0;
    dmem[6433] = 32'd0;
    dmem[6434] = 32'd0;
    dmem[6435] = 32'd0;
    dmem[6436] = 32'd0;
    dmem[6437] = 32'd0;
    dmem[6438] = 32'd0;
    dmem[6439] = 32'd0;
    dmem[6440] = 32'd0;
    dmem[6441] = 32'd0;
    dmem[6442] = 32'd0;
    dmem[6443] = 32'd0;
    dmem[6444] = 32'd0;
    dmem[6445] = 32'd0;
    dmem[6446] = 32'd0;
    dmem[6447] = 32'd0;
    dmem[6448] = 32'd0;
    dmem[6449] = 32'd0;
    dmem[6450] = 32'd0;
    dmem[6451] = 32'd0;
    dmem[6452] = 32'd0;
    dmem[6453] = 32'd0;
    dmem[6454] = 32'd0;
    dmem[6455] = 32'd0;
    dmem[6456] = 32'd0;
    dmem[6457] = 32'd0;
    dmem[6458] = 32'd0;
    dmem[6459] = 32'd0;
    dmem[6460] = 32'd0;
    dmem[6461] = 32'd0;
    dmem[6462] = 32'd0;
    dmem[6463] = 32'd0;
    dmem[6464] = 32'd0;
    dmem[6465] = 32'd0;
    dmem[6466] = 32'd0;
    dmem[6467] = 32'd0;
    dmem[6468] = 32'd0;
    dmem[6469] = 32'd0;
    dmem[6470] = 32'd0;
    dmem[6471] = 32'd0;
    dmem[6472] = 32'd0;
    dmem[6473] = 32'd0;
    dmem[6474] = 32'd0;
    dmem[6475] = 32'd0;
    dmem[6476] = 32'd0;
    dmem[6477] = 32'd0;
    dmem[6478] = 32'd0;
    dmem[6479] = 32'd0;
    dmem[6480] = 32'd0;
    dmem[6481] = 32'd0;
    dmem[6482] = 32'd0;
    dmem[6483] = 32'd0;
    dmem[6484] = 32'd0;
    dmem[6485] = 32'd0;
    dmem[6486] = 32'd0;
    dmem[6487] = 32'd0;
    dmem[6488] = 32'd0;
    dmem[6489] = 32'd0;
    dmem[6490] = 32'd0;
    dmem[6491] = 32'd0;
    dmem[6492] = 32'd0;
    dmem[6493] = 32'd0;
    dmem[6494] = 32'd0;
    dmem[6495] = 32'd0;
    dmem[6496] = 32'd0;
    dmem[6497] = 32'd0;
    dmem[6498] = 32'd0;
    dmem[6499] = 32'd0;
    dmem[6500] = 32'd0;
    dmem[6501] = 32'd0;
    dmem[6502] = 32'd0;
    dmem[6503] = 32'd0;
    dmem[6504] = 32'd0;
    dmem[6505] = 32'd0;
    dmem[6506] = 32'd0;
    dmem[6507] = 32'd0;
    dmem[6508] = 32'd0;
    dmem[6509] = 32'd0;
    dmem[6510] = 32'd0;
    dmem[6511] = 32'd0;
    dmem[6512] = 32'd0;
    dmem[6513] = 32'd0;
    dmem[6514] = 32'd0;
    dmem[6515] = 32'd0;
    dmem[6516] = 32'd0;
    dmem[6517] = 32'd0;
    dmem[6518] = 32'd0;
    dmem[6519] = 32'd0;
    dmem[6520] = 32'd0;
    dmem[6521] = 32'd0;
    dmem[6522] = 32'd0;
    dmem[6523] = 32'd0;
    dmem[6524] = 32'd0;
    dmem[6525] = 32'd0;
    dmem[6526] = 32'd0;
    dmem[6527] = 32'd0;
    dmem[6528] = 32'd0;
    dmem[6529] = 32'd0;
    dmem[6530] = 32'd0;
    dmem[6531] = 32'd0;
    dmem[6532] = 32'd0;
    dmem[6533] = 32'd0;
    dmem[6534] = 32'd0;
    dmem[6535] = 32'd0;
    dmem[6536] = 32'd0;
    dmem[6537] = 32'd0;
    dmem[6538] = 32'd0;
    dmem[6539] = 32'd0;
    dmem[6540] = 32'd0;
    dmem[6541] = 32'd0;
    dmem[6542] = 32'd0;
    dmem[6543] = 32'd0;
    dmem[6544] = 32'd0;
    dmem[6545] = 32'd0;
    dmem[6546] = 32'd0;
    dmem[6547] = 32'd0;
    dmem[6548] = 32'd0;
    dmem[6549] = 32'd0;
    dmem[6550] = 32'd0;
    dmem[6551] = 32'd0;
    dmem[6552] = 32'd0;
    dmem[6553] = 32'd0;
    dmem[6554] = 32'd0;
    dmem[6555] = 32'd0;
    dmem[6556] = 32'd0;
    dmem[6557] = 32'd0;
    dmem[6558] = 32'd0;
    dmem[6559] = 32'd0;
    dmem[6560] = 32'd0;
    dmem[6561] = 32'd0;
    dmem[6562] = 32'd0;
    dmem[6563] = 32'd0;
    dmem[6564] = 32'd0;
    dmem[6565] = 32'd0;
    dmem[6566] = 32'd0;
    dmem[6567] = 32'd0;
    dmem[6568] = 32'd0;
    dmem[6569] = 32'd0;
    dmem[6570] = 32'd0;
    dmem[6571] = 32'd0;
    dmem[6572] = 32'd0;
    dmem[6573] = 32'd0;
    dmem[6574] = 32'd0;
    dmem[6575] = 32'd0;
    dmem[6576] = 32'd0;
    dmem[6577] = 32'd0;
    dmem[6578] = 32'd0;
    dmem[6579] = 32'd0;
    dmem[6580] = 32'd0;
    dmem[6581] = 32'd0;
    dmem[6582] = 32'd0;
    dmem[6583] = 32'd0;
    dmem[6584] = 32'd0;
    dmem[6585] = 32'd0;
    dmem[6586] = 32'd0;
    dmem[6587] = 32'd0;
    dmem[6588] = 32'd0;
    dmem[6589] = 32'd0;
    dmem[6590] = 32'd0;
    dmem[6591] = 32'd0;
    dmem[6592] = 32'd0;
    dmem[6593] = 32'd0;
    dmem[6594] = 32'd0;
    dmem[6595] = 32'd0;
    dmem[6596] = 32'd0;
    dmem[6597] = 32'd0;
    dmem[6598] = 32'd0;
    dmem[6599] = 32'd0;
    dmem[6600] = 32'd0;
    dmem[6601] = 32'd0;
    dmem[6602] = 32'd0;
    dmem[6603] = 32'd0;
    dmem[6604] = 32'd0;
    dmem[6605] = 32'd0;
    dmem[6606] = 32'd0;
    dmem[6607] = 32'd0;
    dmem[6608] = 32'd0;
    dmem[6609] = 32'd0;
    dmem[6610] = 32'd0;
    dmem[6611] = 32'd0;
    dmem[6612] = 32'd0;
    dmem[6613] = 32'd0;
    dmem[6614] = 32'd0;
    dmem[6615] = 32'd0;
    dmem[6616] = 32'd0;
    dmem[6617] = 32'd0;
    dmem[6618] = 32'd0;
    dmem[6619] = 32'd0;
    dmem[6620] = 32'd0;
    dmem[6621] = 32'd0;
    dmem[6622] = 32'd0;
    dmem[6623] = 32'd0;
    dmem[6624] = 32'd0;
    dmem[6625] = 32'd0;
    dmem[6626] = 32'd0;
    dmem[6627] = 32'd0;
    dmem[6628] = 32'd0;
    dmem[6629] = 32'd0;
    dmem[6630] = 32'd0;
    dmem[6631] = 32'd0;
    dmem[6632] = 32'd0;
    dmem[6633] = 32'd0;
    dmem[6634] = 32'd0;
    dmem[6635] = 32'd0;
    dmem[6636] = 32'd0;
    dmem[6637] = 32'd0;
    dmem[6638] = 32'd0;
    dmem[6639] = 32'd0;
    dmem[6640] = 32'd0;
    dmem[6641] = 32'd0;
    dmem[6642] = 32'd0;
    dmem[6643] = 32'd0;
    dmem[6644] = 32'd0;
    dmem[6645] = 32'd0;
    dmem[6646] = 32'd0;
    dmem[6647] = 32'd0;
    dmem[6648] = 32'd0;
    dmem[6649] = 32'd0;
    dmem[6650] = 32'd0;
    dmem[6651] = 32'd0;
    dmem[6652] = 32'd0;
    dmem[6653] = 32'd0;
    dmem[6654] = 32'd0;
    dmem[6655] = 32'd0;
    dmem[6656] = 32'd0;
    dmem[6657] = 32'd0;
    dmem[6658] = 32'd0;
    dmem[6659] = 32'd0;
    dmem[6660] = 32'd0;
    dmem[6661] = 32'd0;
    dmem[6662] = 32'd0;
    dmem[6663] = 32'd0;
    dmem[6664] = 32'd0;
    dmem[6665] = 32'd0;
    dmem[6666] = 32'd0;
    dmem[6667] = 32'd0;
    dmem[6668] = 32'd0;
    dmem[6669] = 32'd0;
    dmem[6670] = 32'd0;
    dmem[6671] = 32'd0;
    dmem[6672] = 32'd0;
    dmem[6673] = 32'd0;
    dmem[6674] = 32'd0;
    dmem[6675] = 32'd0;
    dmem[6676] = 32'd0;
    dmem[6677] = 32'd0;
    dmem[6678] = 32'd0;
    dmem[6679] = 32'd0;
    dmem[6680] = 32'd0;
    dmem[6681] = 32'd0;
    dmem[6682] = 32'd0;
    dmem[6683] = 32'd0;
    dmem[6684] = 32'd0;
    dmem[6685] = 32'd0;
    dmem[6686] = 32'd0;
    dmem[6687] = 32'd0;
    dmem[6688] = 32'd0;
    dmem[6689] = 32'd0;
    dmem[6690] = 32'd0;
    dmem[6691] = 32'd0;
    dmem[6692] = 32'd0;
    dmem[6693] = 32'd0;
    dmem[6694] = 32'd0;
    dmem[6695] = 32'd0;
    dmem[6696] = 32'd0;
    dmem[6697] = 32'd0;
    dmem[6698] = 32'd0;
    dmem[6699] = 32'd0;
    dmem[6700] = 32'd0;
    dmem[6701] = 32'd0;
    dmem[6702] = 32'd0;
    dmem[6703] = 32'd0;
    dmem[6704] = 32'd0;
    dmem[6705] = 32'd0;
    dmem[6706] = 32'd0;
    dmem[6707] = 32'd0;
    dmem[6708] = 32'd0;
    dmem[6709] = 32'd0;
    dmem[6710] = 32'd0;
    dmem[6711] = 32'd0;
    dmem[6712] = 32'd0;
    dmem[6713] = 32'd0;
    dmem[6714] = 32'd0;
    dmem[6715] = 32'd0;
    dmem[6716] = 32'd0;
    dmem[6717] = 32'd0;
    dmem[6718] = 32'd0;
    dmem[6719] = 32'd0;
    dmem[6720] = 32'd0;
    dmem[6721] = 32'd0;
    dmem[6722] = 32'd0;
    dmem[6723] = 32'd0;
    dmem[6724] = 32'd0;
    dmem[6725] = 32'd0;
    dmem[6726] = 32'd0;
    dmem[6727] = 32'd0;
    dmem[6728] = 32'd0;
    dmem[6729] = 32'd0;
    dmem[6730] = 32'd0;
    dmem[6731] = 32'd0;
    dmem[6732] = 32'd0;
    dmem[6733] = 32'd0;
    dmem[6734] = 32'd0;
    dmem[6735] = 32'd0;
    dmem[6736] = 32'd0;
    dmem[6737] = 32'd0;
    dmem[6738] = 32'd0;
    dmem[6739] = 32'd0;
    dmem[6740] = 32'd0;
    dmem[6741] = 32'd0;
    dmem[6742] = 32'd0;
    dmem[6743] = 32'd0;
    dmem[6744] = 32'd0;
    dmem[6745] = 32'd0;
    dmem[6746] = 32'd0;
    dmem[6747] = 32'd0;
    dmem[6748] = 32'd0;
    dmem[6749] = 32'd0;
    dmem[6750] = 32'd0;
    dmem[6751] = 32'd0;
    dmem[6752] = 32'd0;
    dmem[6753] = 32'd0;
    dmem[6754] = 32'd0;
    dmem[6755] = 32'd0;
    dmem[6756] = 32'd0;
    dmem[6757] = 32'd0;
    dmem[6758] = 32'd0;
    dmem[6759] = 32'd0;
    dmem[6760] = 32'd0;
    dmem[6761] = 32'd0;
    dmem[6762] = 32'd0;
    dmem[6763] = 32'd0;
    dmem[6764] = 32'd0;
    dmem[6765] = 32'd0;
    dmem[6766] = 32'd0;
    dmem[6767] = 32'd0;
    dmem[6768] = 32'd0;
    dmem[6769] = 32'd0;
    dmem[6770] = 32'd0;
    dmem[6771] = 32'd0;
    dmem[6772] = 32'd0;
    dmem[6773] = 32'd0;
    dmem[6774] = 32'd0;
    dmem[6775] = 32'd0;
    dmem[6776] = 32'd0;
    dmem[6777] = 32'd0;
    dmem[6778] = 32'd0;
    dmem[6779] = 32'd0;
    dmem[6780] = 32'd0;
    dmem[6781] = 32'd0;
    dmem[6782] = 32'd0;
    dmem[6783] = 32'd0;
    dmem[6784] = 32'd0;
    dmem[6785] = 32'd0;
    dmem[6786] = 32'd0;
    dmem[6787] = 32'd0;
    dmem[6788] = 32'd0;
    dmem[6789] = 32'd0;
    dmem[6790] = 32'd0;
    dmem[6791] = 32'd0;
    dmem[6792] = 32'd0;
    dmem[6793] = 32'd0;
    dmem[6794] = 32'd0;
    dmem[6795] = 32'd0;
    dmem[6796] = 32'd0;
    dmem[6797] = 32'd0;
    dmem[6798] = 32'd0;
    dmem[6799] = 32'd0;
    dmem[6800] = 32'd0;
    dmem[6801] = 32'd0;
    dmem[6802] = 32'd0;
    dmem[6803] = 32'd0;
    dmem[6804] = 32'd0;
    dmem[6805] = 32'd0;
    dmem[6806] = 32'd0;
    dmem[6807] = 32'd0;
    dmem[6808] = 32'd0;
    dmem[6809] = 32'd0;
    dmem[6810] = 32'd0;
    dmem[6811] = 32'd0;
    dmem[6812] = 32'd0;
    dmem[6813] = 32'd0;
    dmem[6814] = 32'd0;
    dmem[6815] = 32'd0;
    dmem[6816] = 32'd0;
    dmem[6817] = 32'd0;
    dmem[6818] = 32'd0;
    dmem[6819] = 32'd0;
    dmem[6820] = 32'd0;
    dmem[6821] = 32'd0;
    dmem[6822] = 32'd0;
    dmem[6823] = 32'd0;
    dmem[6824] = 32'd0;
    dmem[6825] = 32'd0;
    dmem[6826] = 32'd0;
    dmem[6827] = 32'd0;
    dmem[6828] = 32'd0;
    dmem[6829] = 32'd0;
    dmem[6830] = 32'd0;
    dmem[6831] = 32'd0;
    dmem[6832] = 32'd0;
    dmem[6833] = 32'd0;
    dmem[6834] = 32'd0;
    dmem[6835] = 32'd0;
    dmem[6836] = 32'd0;
    dmem[6837] = 32'd0;
    dmem[6838] = 32'd0;
    dmem[6839] = 32'd0;
    dmem[6840] = 32'd0;
    dmem[6841] = 32'd0;
    dmem[6842] = 32'd0;
    dmem[6843] = 32'd0;
    dmem[6844] = 32'd0;
    dmem[6845] = 32'd0;
    dmem[6846] = 32'd0;
    dmem[6847] = 32'd0;
    dmem[6848] = 32'd0;
    dmem[6849] = 32'd0;
    dmem[6850] = 32'd0;
    dmem[6851] = 32'd0;
    dmem[6852] = 32'd0;
    dmem[6853] = 32'd0;
    dmem[6854] = 32'd0;
    dmem[6855] = 32'd0;
    dmem[6856] = 32'd0;
    dmem[6857] = 32'd0;
    dmem[6858] = 32'd0;
    dmem[6859] = 32'd0;
    dmem[6860] = 32'd0;
    dmem[6861] = 32'd0;
    dmem[6862] = 32'd0;
    dmem[6863] = 32'd0;
    dmem[6864] = 32'd0;
    dmem[6865] = 32'd0;
    dmem[6866] = 32'd0;
    dmem[6867] = 32'd0;
    dmem[6868] = 32'd0;
    dmem[6869] = 32'd0;
    dmem[6870] = 32'd0;
    dmem[6871] = 32'd0;
    dmem[6872] = 32'd0;
    dmem[6873] = 32'd0;
    dmem[6874] = 32'd0;
    dmem[6875] = 32'd0;
    dmem[6876] = 32'd0;
    dmem[6877] = 32'd0;
    dmem[6878] = 32'd0;
    dmem[6879] = 32'd0;
    dmem[6880] = 32'd0;
    dmem[6881] = 32'd0;
    dmem[6882] = 32'd0;
    dmem[6883] = 32'd0;
    dmem[6884] = 32'd0;
    dmem[6885] = 32'd0;
    dmem[6886] = 32'd0;
    dmem[6887] = 32'd0;
    dmem[6888] = 32'd0;
    dmem[6889] = 32'd0;
    dmem[6890] = 32'd0;
    dmem[6891] = 32'd0;
    dmem[6892] = 32'd0;
    dmem[6893] = 32'd0;
    dmem[6894] = 32'd0;
    dmem[6895] = 32'd0;
    dmem[6896] = 32'd0;
    dmem[6897] = 32'd0;
    dmem[6898] = 32'd0;
    dmem[6899] = 32'd0;
    dmem[6900] = 32'd0;
    dmem[6901] = 32'd0;
    dmem[6902] = 32'd0;
    dmem[6903] = 32'd0;
    dmem[6904] = 32'd0;
    dmem[6905] = 32'd0;
    dmem[6906] = 32'd0;
    dmem[6907] = 32'd0;
    dmem[6908] = 32'd0;
    dmem[6909] = 32'd0;
    dmem[6910] = 32'd0;
    dmem[6911] = 32'd0;
    dmem[6912] = 32'd0;
    dmem[6913] = 32'd0;
    dmem[6914] = 32'd0;
    dmem[6915] = 32'd0;
    dmem[6916] = 32'd0;
    dmem[6917] = 32'd0;
    dmem[6918] = 32'd0;
    dmem[6919] = 32'd0;
    dmem[6920] = 32'd0;
    dmem[6921] = 32'd0;
    dmem[6922] = 32'd0;
    dmem[6923] = 32'd0;
    dmem[6924] = 32'd0;
    dmem[6925] = 32'd0;
    dmem[6926] = 32'd0;
    dmem[6927] = 32'd0;
    dmem[6928] = 32'd0;
    dmem[6929] = 32'd0;
    dmem[6930] = 32'd0;
    dmem[6931] = 32'd0;
    dmem[6932] = 32'd0;
    dmem[6933] = 32'd0;
    dmem[6934] = 32'd0;
    dmem[6935] = 32'd0;
    dmem[6936] = 32'd0;
    dmem[6937] = 32'd0;
    dmem[6938] = 32'd0;
    dmem[6939] = 32'd0;
    dmem[6940] = 32'd0;
    dmem[6941] = 32'd0;
    dmem[6942] = 32'd0;
    dmem[6943] = 32'd0;
    dmem[6944] = 32'd0;
    dmem[6945] = 32'd0;
    dmem[6946] = 32'd0;
    dmem[6947] = 32'd0;
    dmem[6948] = 32'd0;
    dmem[6949] = 32'd0;
    dmem[6950] = 32'd0;
    dmem[6951] = 32'd0;
    dmem[6952] = 32'd0;
    dmem[6953] = 32'd0;
    dmem[6954] = 32'd0;
    dmem[6955] = 32'd0;
    dmem[6956] = 32'd0;
    dmem[6957] = 32'd0;
    dmem[6958] = 32'd0;
    dmem[6959] = 32'd0;
    dmem[6960] = 32'd0;
    dmem[6961] = 32'd0;
    dmem[6962] = 32'd0;
    dmem[6963] = 32'd0;
    dmem[6964] = 32'd0;
    dmem[6965] = 32'd0;
    dmem[6966] = 32'd0;
    dmem[6967] = 32'd0;
    dmem[6968] = 32'd0;
    dmem[6969] = 32'd0;
    dmem[6970] = 32'd0;
    dmem[6971] = 32'd0;
    dmem[6972] = 32'd0;
    dmem[6973] = 32'd0;
    dmem[6974] = 32'd0;
    dmem[6975] = 32'd0;
    dmem[6976] = 32'd0;
    dmem[6977] = 32'd0;
    dmem[6978] = 32'd0;
    dmem[6979] = 32'd0;
    dmem[6980] = 32'd0;
    dmem[6981] = 32'd0;
    dmem[6982] = 32'd0;
    dmem[6983] = 32'd0;
    dmem[6984] = 32'd0;
    dmem[6985] = 32'd0;
    dmem[6986] = 32'd0;
    dmem[6987] = 32'd0;
    dmem[6988] = 32'd0;
    dmem[6989] = 32'd0;
    dmem[6990] = 32'd0;
    dmem[6991] = 32'd0;
    dmem[6992] = 32'd0;
    dmem[6993] = 32'd0;
    dmem[6994] = 32'd0;
    dmem[6995] = 32'd0;
    dmem[6996] = 32'd0;
    dmem[6997] = 32'd0;
    dmem[6998] = 32'd0;
    dmem[6999] = 32'd0;
    dmem[7000] = 32'd0;
    dmem[7001] = 32'd0;
    dmem[7002] = 32'd0;
    dmem[7003] = 32'd0;
    dmem[7004] = 32'd0;
    dmem[7005] = 32'd0;
    dmem[7006] = 32'd0;
    dmem[7007] = 32'd0;
    dmem[7008] = 32'd0;
    dmem[7009] = 32'd0;
    dmem[7010] = 32'd0;
    dmem[7011] = 32'd0;
    dmem[7012] = 32'd0;
    dmem[7013] = 32'd0;
    dmem[7014] = 32'd0;
    dmem[7015] = 32'd0;
    dmem[7016] = 32'd0;
    dmem[7017] = 32'd0;
    dmem[7018] = 32'd0;
    dmem[7019] = 32'd0;
    dmem[7020] = 32'd0;
    dmem[7021] = 32'd0;
    dmem[7022] = 32'd0;
    dmem[7023] = 32'd0;
    dmem[7024] = 32'd0;
    dmem[7025] = 32'd0;
    dmem[7026] = 32'd0;
    dmem[7027] = 32'd0;
    dmem[7028] = 32'd0;
    dmem[7029] = 32'd0;
    dmem[7030] = 32'd0;
    dmem[7031] = 32'd0;
    dmem[7032] = 32'd0;
    dmem[7033] = 32'd0;
    dmem[7034] = 32'd0;
    dmem[7035] = 32'd0;
    dmem[7036] = 32'd0;
    dmem[7037] = 32'd0;
    dmem[7038] = 32'd0;
    dmem[7039] = 32'd0;
    dmem[7040] = 32'd0;
    dmem[7041] = 32'd0;
    dmem[7042] = 32'd0;
    dmem[7043] = 32'd0;
    dmem[7044] = 32'd0;
    dmem[7045] = 32'd0;
    dmem[7046] = 32'd0;
    dmem[7047] = 32'd0;
    dmem[7048] = 32'd0;
    dmem[7049] = 32'd0;
    dmem[7050] = 32'd0;
    dmem[7051] = 32'd0;
    dmem[7052] = 32'd0;
    dmem[7053] = 32'd0;
    dmem[7054] = 32'd0;
    dmem[7055] = 32'd0;
    dmem[7056] = 32'd0;
    dmem[7057] = 32'd0;
    dmem[7058] = 32'd0;
    dmem[7059] = 32'd0;
    dmem[7060] = 32'd0;
    dmem[7061] = 32'd0;
    dmem[7062] = 32'd0;
    dmem[7063] = 32'd0;
    dmem[7064] = 32'd0;
    dmem[7065] = 32'd0;
    dmem[7066] = 32'd0;
    dmem[7067] = 32'd0;
    dmem[7068] = 32'd0;
    dmem[7069] = 32'd0;
    dmem[7070] = 32'd0;
    dmem[7071] = 32'd0;
    dmem[7072] = 32'd0;
    dmem[7073] = 32'd0;
    dmem[7074] = 32'd0;
    dmem[7075] = 32'd0;
    dmem[7076] = 32'd0;
    dmem[7077] = 32'd0;
    dmem[7078] = 32'd0;
    dmem[7079] = 32'd0;
    dmem[7080] = 32'd0;
    dmem[7081] = 32'd0;
    dmem[7082] = 32'd0;
    dmem[7083] = 32'd0;
    dmem[7084] = 32'd0;
    dmem[7085] = 32'd0;
    dmem[7086] = 32'd0;
    dmem[7087] = 32'd0;
    dmem[7088] = 32'd0;
    dmem[7089] = 32'd0;
    dmem[7090] = 32'd0;
    dmem[7091] = 32'd0;
    dmem[7092] = 32'd0;
    dmem[7093] = 32'd0;
    dmem[7094] = 32'd0;
    dmem[7095] = 32'd0;
    dmem[7096] = 32'd0;
    dmem[7097] = 32'd0;
    dmem[7098] = 32'd0;
    dmem[7099] = 32'd0;
    dmem[7100] = 32'd0;
    dmem[7101] = 32'd0;
    dmem[7102] = 32'd0;
    dmem[7103] = 32'd0;
    dmem[7104] = 32'd0;
    dmem[7105] = 32'd0;
    dmem[7106] = 32'd0;
    dmem[7107] = 32'd0;
    dmem[7108] = 32'd0;
    dmem[7109] = 32'd0;
    dmem[7110] = 32'd0;
    dmem[7111] = 32'd0;
    dmem[7112] = 32'd0;
    dmem[7113] = 32'd0;
    dmem[7114] = 32'd0;
    dmem[7115] = 32'd0;
    dmem[7116] = 32'd0;
    dmem[7117] = 32'd0;
    dmem[7118] = 32'd0;
    dmem[7119] = 32'd0;
    dmem[7120] = 32'd0;
    dmem[7121] = 32'd0;
    dmem[7122] = 32'd0;
    dmem[7123] = 32'd0;
    dmem[7124] = 32'd0;
    dmem[7125] = 32'd0;
    dmem[7126] = 32'd0;
    dmem[7127] = 32'd0;
    dmem[7128] = 32'd0;
    dmem[7129] = 32'd0;
    dmem[7130] = 32'd0;
    dmem[7131] = 32'd0;
    dmem[7132] = 32'd0;
    dmem[7133] = 32'd0;
    dmem[7134] = 32'd0;
    dmem[7135] = 32'd0;
    dmem[7136] = 32'd0;
    dmem[7137] = 32'd0;
    dmem[7138] = 32'd0;
    dmem[7139] = 32'd0;
    dmem[7140] = 32'd0;
    dmem[7141] = 32'd0;
    dmem[7142] = 32'd0;
    dmem[7143] = 32'd0;
    dmem[7144] = 32'd0;
    dmem[7145] = 32'd0;
    dmem[7146] = 32'd0;
    dmem[7147] = 32'd0;
    dmem[7148] = 32'd0;
    dmem[7149] = 32'd0;
    dmem[7150] = 32'd0;
    dmem[7151] = 32'd0;
    dmem[7152] = 32'd0;
    dmem[7153] = 32'd0;
    dmem[7154] = 32'd0;
    dmem[7155] = 32'd0;
    dmem[7156] = 32'd0;
    dmem[7157] = 32'd0;
    dmem[7158] = 32'd0;
    dmem[7159] = 32'd0;
    dmem[7160] = 32'd0;
    dmem[7161] = 32'd0;
    dmem[7162] = 32'd0;
    dmem[7163] = 32'd0;
    dmem[7164] = 32'd0;
    dmem[7165] = 32'd0;
    dmem[7166] = 32'd0;
    dmem[7167] = 32'd0;
    dmem[7168] = 32'd0;
    dmem[7169] = 32'd0;
    dmem[7170] = 32'd0;
    dmem[7171] = 32'd0;
    dmem[7172] = 32'd0;
    dmem[7173] = 32'd0;
    dmem[7174] = 32'd0;
    dmem[7175] = 32'd0;
    dmem[7176] = 32'd0;
    dmem[7177] = 32'd0;
    dmem[7178] = 32'd0;
    dmem[7179] = 32'd0;
    dmem[7180] = 32'd0;
    dmem[7181] = 32'd0;
    dmem[7182] = 32'd0;
    dmem[7183] = 32'd0;
    dmem[7184] = 32'd0;
    dmem[7185] = 32'd0;
    dmem[7186] = 32'd0;
    dmem[7187] = 32'd0;
    dmem[7188] = 32'd0;
    dmem[7189] = 32'd0;
    dmem[7190] = 32'd0;
    dmem[7191] = 32'd0;
    dmem[7192] = 32'd0;
    dmem[7193] = 32'd0;
    dmem[7194] = 32'd0;
    dmem[7195] = 32'd0;
    dmem[7196] = 32'd0;
    dmem[7197] = 32'd0;
    dmem[7198] = 32'd0;
    dmem[7199] = 32'd0;
    dmem[7200] = 32'd0;
    dmem[7201] = 32'd0;
    dmem[7202] = 32'd0;
    dmem[7203] = 32'd0;
    dmem[7204] = 32'd0;
    dmem[7205] = 32'd0;
    dmem[7206] = 32'd0;
    dmem[7207] = 32'd0;
    dmem[7208] = 32'd0;
    dmem[7209] = 32'd0;
    dmem[7210] = 32'd0;
    dmem[7211] = 32'd0;
    dmem[7212] = 32'd0;
    dmem[7213] = 32'd0;
    dmem[7214] = 32'd0;
    dmem[7215] = 32'd0;
    dmem[7216] = 32'd0;
    dmem[7217] = 32'd0;
    dmem[7218] = 32'd0;
    dmem[7219] = 32'd0;
    dmem[7220] = 32'd0;
    dmem[7221] = 32'd0;
    dmem[7222] = 32'd0;
    dmem[7223] = 32'd0;
    dmem[7224] = 32'd0;
    dmem[7225] = 32'd0;
    dmem[7226] = 32'd0;
    dmem[7227] = 32'd0;
    dmem[7228] = 32'd0;
    dmem[7229] = 32'd0;
    dmem[7230] = 32'd0;
    dmem[7231] = 32'd0;
    dmem[7232] = 32'd0;
    dmem[7233] = 32'd0;
    dmem[7234] = 32'd0;
    dmem[7235] = 32'd0;
    dmem[7236] = 32'd0;
    dmem[7237] = 32'd0;
    dmem[7238] = 32'd0;
    dmem[7239] = 32'd0;
    dmem[7240] = 32'd0;
    dmem[7241] = 32'd0;
    dmem[7242] = 32'd0;
    dmem[7243] = 32'd0;
    dmem[7244] = 32'd0;
    dmem[7245] = 32'd0;
    dmem[7246] = 32'd0;
    dmem[7247] = 32'd0;
    dmem[7248] = 32'd0;
    dmem[7249] = 32'd0;
    dmem[7250] = 32'd0;
    dmem[7251] = 32'd0;
    dmem[7252] = 32'd0;
    dmem[7253] = 32'd0;
    dmem[7254] = 32'd0;
    dmem[7255] = 32'd0;
    dmem[7256] = 32'd0;
    dmem[7257] = 32'd0;
    dmem[7258] = 32'd0;
    dmem[7259] = 32'd0;
    dmem[7260] = 32'd0;
    dmem[7261] = 32'd0;
    dmem[7262] = 32'd0;
    dmem[7263] = 32'd0;
    dmem[7264] = 32'd0;
    dmem[7265] = 32'd0;
    dmem[7266] = 32'd0;
    dmem[7267] = 32'd0;
    dmem[7268] = 32'd0;
    dmem[7269] = 32'd0;
    dmem[7270] = 32'd0;
    dmem[7271] = 32'd0;
    dmem[7272] = 32'd0;
    dmem[7273] = 32'd0;
    dmem[7274] = 32'd0;
    dmem[7275] = 32'd0;
    dmem[7276] = 32'd0;
    dmem[7277] = 32'd0;
    dmem[7278] = 32'd0;
    dmem[7279] = 32'd0;
    dmem[7280] = 32'd0;
    dmem[7281] = 32'd0;
    dmem[7282] = 32'd0;
    dmem[7283] = 32'd0;
    dmem[7284] = 32'd0;
    dmem[7285] = 32'd0;
    dmem[7286] = 32'd0;
    dmem[7287] = 32'd0;
    dmem[7288] = 32'd0;
    dmem[7289] = 32'd0;
    dmem[7290] = 32'd0;
    dmem[7291] = 32'd0;
    dmem[7292] = 32'd0;
    dmem[7293] = 32'd0;
    dmem[7294] = 32'd0;
    dmem[7295] = 32'd0;
    dmem[7296] = 32'd0;
    dmem[7297] = 32'd0;
    dmem[7298] = 32'd0;
    dmem[7299] = 32'd0;
    dmem[7300] = 32'd0;
    dmem[7301] = 32'd0;
    dmem[7302] = 32'd0;
    dmem[7303] = 32'd0;
    dmem[7304] = 32'd0;
    dmem[7305] = 32'd0;
    dmem[7306] = 32'd0;
    dmem[7307] = 32'd0;
    dmem[7308] = 32'd0;
    dmem[7309] = 32'd0;
    dmem[7310] = 32'd0;
    dmem[7311] = 32'd0;
    dmem[7312] = 32'd0;
    dmem[7313] = 32'd0;
    dmem[7314] = 32'd0;
    dmem[7315] = 32'd0;
    dmem[7316] = 32'd0;
    dmem[7317] = 32'd0;
    dmem[7318] = 32'd0;
    dmem[7319] = 32'd0;
    dmem[7320] = 32'd0;
    dmem[7321] = 32'd0;
    dmem[7322] = 32'd0;
    dmem[7323] = 32'd0;
    dmem[7324] = 32'd0;
    dmem[7325] = 32'd0;
    dmem[7326] = 32'd0;
    dmem[7327] = 32'd0;
    dmem[7328] = 32'd0;
    dmem[7329] = 32'd0;
    dmem[7330] = 32'd0;
    dmem[7331] = 32'd0;
    dmem[7332] = 32'd0;
    dmem[7333] = 32'd0;
    dmem[7334] = 32'd0;
    dmem[7335] = 32'd0;
    dmem[7336] = 32'd0;
    dmem[7337] = 32'd0;
    dmem[7338] = 32'd0;
    dmem[7339] = 32'd0;
    dmem[7340] = 32'd0;
    dmem[7341] = 32'd0;
    dmem[7342] = 32'd0;
    dmem[7343] = 32'd0;
    dmem[7344] = 32'd0;
    dmem[7345] = 32'd0;
    dmem[7346] = 32'd0;
    dmem[7347] = 32'd0;
    dmem[7348] = 32'd0;
    dmem[7349] = 32'd0;
    dmem[7350] = 32'd0;
    dmem[7351] = 32'd0;
    dmem[7352] = 32'd0;
    dmem[7353] = 32'd0;
    dmem[7354] = 32'd0;
    dmem[7355] = 32'd0;
    dmem[7356] = 32'd0;
    dmem[7357] = 32'd0;
    dmem[7358] = 32'd0;
    dmem[7359] = 32'd0;
    dmem[7360] = 32'd0;
    dmem[7361] = 32'd0;
    dmem[7362] = 32'd0;
    dmem[7363] = 32'd0;
    dmem[7364] = 32'd0;
    dmem[7365] = 32'd0;
    dmem[7366] = 32'd0;
    dmem[7367] = 32'd0;
    dmem[7368] = 32'd0;
    dmem[7369] = 32'd0;
    dmem[7370] = 32'd0;
    dmem[7371] = 32'd0;
    dmem[7372] = 32'd0;
    dmem[7373] = 32'd0;
    dmem[7374] = 32'd0;
    dmem[7375] = 32'd0;
    dmem[7376] = 32'd0;
    dmem[7377] = 32'd0;
    dmem[7378] = 32'd0;
    dmem[7379] = 32'd0;
    dmem[7380] = 32'd0;
    dmem[7381] = 32'd0;
    dmem[7382] = 32'd0;
    dmem[7383] = 32'd0;
    dmem[7384] = 32'd0;
    dmem[7385] = 32'd0;
    dmem[7386] = 32'd0;
    dmem[7387] = 32'd0;
    dmem[7388] = 32'd0;
    dmem[7389] = 32'd0;
    dmem[7390] = 32'd0;
    dmem[7391] = 32'd0;
    dmem[7392] = 32'd0;
    dmem[7393] = 32'd0;
    dmem[7394] = 32'd0;
    dmem[7395] = 32'd0;
    dmem[7396] = 32'd0;
    dmem[7397] = 32'd0;
    dmem[7398] = 32'd0;
    dmem[7399] = 32'd0;
    dmem[7400] = 32'd0;
    dmem[7401] = 32'd0;
    dmem[7402] = 32'd0;
    dmem[7403] = 32'd0;
    dmem[7404] = 32'd0;
    dmem[7405] = 32'd0;
    dmem[7406] = 32'd0;
    dmem[7407] = 32'd0;
    dmem[7408] = 32'd0;
    dmem[7409] = 32'd0;
    dmem[7410] = 32'd0;
    dmem[7411] = 32'd0;
    dmem[7412] = 32'd0;
    dmem[7413] = 32'd0;
    dmem[7414] = 32'd0;
    dmem[7415] = 32'd0;
    dmem[7416] = 32'd0;
    dmem[7417] = 32'd0;
    dmem[7418] = 32'd0;
    dmem[7419] = 32'd0;
    dmem[7420] = 32'd0;
    dmem[7421] = 32'd0;
    dmem[7422] = 32'd0;
    dmem[7423] = 32'd0;
    dmem[7424] = 32'd0;
    dmem[7425] = 32'd0;
    dmem[7426] = 32'd0;
    dmem[7427] = 32'd0;
    dmem[7428] = 32'd0;
    dmem[7429] = 32'd0;
    dmem[7430] = 32'd0;
    dmem[7431] = 32'd0;
    dmem[7432] = 32'd0;
    dmem[7433] = 32'd0;
    dmem[7434] = 32'd0;
    dmem[7435] = 32'd0;
    dmem[7436] = 32'd0;
    dmem[7437] = 32'd0;
    dmem[7438] = 32'd0;
    dmem[7439] = 32'd0;
    dmem[7440] = 32'd0;
    dmem[7441] = 32'd0;
    dmem[7442] = 32'd0;
    dmem[7443] = 32'd0;
    dmem[7444] = 32'd0;
    dmem[7445] = 32'd0;
    dmem[7446] = 32'd0;
    dmem[7447] = 32'd0;
    dmem[7448] = 32'd0;
    dmem[7449] = 32'd0;
    dmem[7450] = 32'd0;
    dmem[7451] = 32'd0;
    dmem[7452] = 32'd0;
    dmem[7453] = 32'd0;
    dmem[7454] = 32'd0;
    dmem[7455] = 32'd0;
    dmem[7456] = 32'd0;
    dmem[7457] = 32'd0;
    dmem[7458] = 32'd0;
    dmem[7459] = 32'd0;
    dmem[7460] = 32'd0;
    dmem[7461] = 32'd0;
    dmem[7462] = 32'd0;
    dmem[7463] = 32'd0;
    dmem[7464] = 32'd0;
    dmem[7465] = 32'd0;
    dmem[7466] = 32'd0;
    dmem[7467] = 32'd0;
    dmem[7468] = 32'd0;
    dmem[7469] = 32'd0;
    dmem[7470] = 32'd0;
    dmem[7471] = 32'd0;
    dmem[7472] = 32'd0;
    dmem[7473] = 32'd0;
    dmem[7474] = 32'd0;
    dmem[7475] = 32'd0;
    dmem[7476] = 32'd0;
    dmem[7477] = 32'd0;
    dmem[7478] = 32'd0;
    dmem[7479] = 32'd0;
    dmem[7480] = 32'd0;
    dmem[7481] = 32'd0;
    dmem[7482] = 32'd0;
    dmem[7483] = 32'd0;
    dmem[7484] = 32'd0;
    dmem[7485] = 32'd0;
    dmem[7486] = 32'd0;
    dmem[7487] = 32'd0;
    dmem[7488] = 32'd0;
    dmem[7489] = 32'd0;
    dmem[7490] = 32'd0;
    dmem[7491] = 32'd0;
    dmem[7492] = 32'd0;
    dmem[7493] = 32'd0;
    dmem[7494] = 32'd0;
    dmem[7495] = 32'd0;
    dmem[7496] = 32'd0;
    dmem[7497] = 32'd0;
    dmem[7498] = 32'd0;
    dmem[7499] = 32'd0;
    dmem[7500] = 32'd0;
    dmem[7501] = 32'd0;
    dmem[7502] = 32'd0;
    dmem[7503] = 32'd0;
    dmem[7504] = 32'd0;
    dmem[7505] = 32'd0;
    dmem[7506] = 32'd0;
    dmem[7507] = 32'd0;
    dmem[7508] = 32'd0;
    dmem[7509] = 32'd0;
    dmem[7510] = 32'd0;
    dmem[7511] = 32'd0;
    dmem[7512] = 32'd0;
    dmem[7513] = 32'd0;
    dmem[7514] = 32'd0;
    dmem[7515] = 32'd0;
    dmem[7516] = 32'd0;
    dmem[7517] = 32'd0;
    dmem[7518] = 32'd0;
    dmem[7519] = 32'd0;
    dmem[7520] = 32'd0;
    dmem[7521] = 32'd0;
    dmem[7522] = 32'd0;
    dmem[7523] = 32'd0;
    dmem[7524] = 32'd0;
    dmem[7525] = 32'd0;
    dmem[7526] = 32'd0;
    dmem[7527] = 32'd0;
    dmem[7528] = 32'd0;
    dmem[7529] = 32'd0;
    dmem[7530] = 32'd0;
    dmem[7531] = 32'd0;
    dmem[7532] = 32'd0;
    dmem[7533] = 32'd0;
    dmem[7534] = 32'd0;
    dmem[7535] = 32'd0;
    dmem[7536] = 32'd0;
    dmem[7537] = 32'd0;
    dmem[7538] = 32'd0;
    dmem[7539] = 32'd0;
    dmem[7540] = 32'd0;
    dmem[7541] = 32'd0;
    dmem[7542] = 32'd0;
    dmem[7543] = 32'd0;
    dmem[7544] = 32'd0;
    dmem[7545] = 32'd0;
    dmem[7546] = 32'd0;
    dmem[7547] = 32'd0;
    dmem[7548] = 32'd0;
    dmem[7549] = 32'd0;
    dmem[7550] = 32'd0;
    dmem[7551] = 32'd0;
    dmem[7552] = 32'd0;
    dmem[7553] = 32'd0;
    dmem[7554] = 32'd0;
    dmem[7555] = 32'd0;
    dmem[7556] = 32'd0;
    dmem[7557] = 32'd0;
    dmem[7558] = 32'd0;
    dmem[7559] = 32'd0;
    dmem[7560] = 32'd0;
    dmem[7561] = 32'd0;
    dmem[7562] = 32'd0;
    dmem[7563] = 32'd0;
    dmem[7564] = 32'd0;
    dmem[7565] = 32'd0;
    dmem[7566] = 32'd0;
    dmem[7567] = 32'd0;
    dmem[7568] = 32'd0;
    dmem[7569] = 32'd0;
    dmem[7570] = 32'd0;
    dmem[7571] = 32'd0;
    dmem[7572] = 32'd0;
    dmem[7573] = 32'd0;
    dmem[7574] = 32'd0;
    dmem[7575] = 32'd0;
    dmem[7576] = 32'd0;
    dmem[7577] = 32'd0;
    dmem[7578] = 32'd0;
    dmem[7579] = 32'd0;
    dmem[7580] = 32'd0;
    dmem[7581] = 32'd0;
    dmem[7582] = 32'd0;
    dmem[7583] = 32'd0;
    dmem[7584] = 32'd0;
    dmem[7585] = 32'd0;
    dmem[7586] = 32'd0;
    dmem[7587] = 32'd0;
    dmem[7588] = 32'd0;
    dmem[7589] = 32'd0;
    dmem[7590] = 32'd0;
    dmem[7591] = 32'd0;
    dmem[7592] = 32'd0;
    dmem[7593] = 32'd0;
    dmem[7594] = 32'd0;
    dmem[7595] = 32'd0;
    dmem[7596] = 32'd0;
    dmem[7597] = 32'd0;
    dmem[7598] = 32'd0;
    dmem[7599] = 32'd0;
    dmem[7600] = 32'd0;
    dmem[7601] = 32'd0;
    dmem[7602] = 32'd0;
    dmem[7603] = 32'd0;
    dmem[7604] = 32'd0;
    dmem[7605] = 32'd0;
    dmem[7606] = 32'd0;
    dmem[7607] = 32'd0;
    dmem[7608] = 32'd0;
    dmem[7609] = 32'd0;
    dmem[7610] = 32'd0;
    dmem[7611] = 32'd0;
    dmem[7612] = 32'd0;
    dmem[7613] = 32'd0;
    dmem[7614] = 32'd0;
    dmem[7615] = 32'd0;
    dmem[7616] = 32'd0;
    dmem[7617] = 32'd0;
    dmem[7618] = 32'd0;
    dmem[7619] = 32'd0;
    dmem[7620] = 32'd0;
    dmem[7621] = 32'd0;
    dmem[7622] = 32'd0;
    dmem[7623] = 32'd0;
    dmem[7624] = 32'd0;
    dmem[7625] = 32'd0;
    dmem[7626] = 32'd0;
    dmem[7627] = 32'd0;
    dmem[7628] = 32'd0;
    dmem[7629] = 32'd0;
    dmem[7630] = 32'd0;
    dmem[7631] = 32'd0;
    dmem[7632] = 32'd0;
    dmem[7633] = 32'd0;
    dmem[7634] = 32'd0;
    dmem[7635] = 32'd0;
    dmem[7636] = 32'd0;
    dmem[7637] = 32'd0;
    dmem[7638] = 32'd0;
    dmem[7639] = 32'd0;
    dmem[7640] = 32'd0;
    dmem[7641] = 32'd0;
    dmem[7642] = 32'd0;
    dmem[7643] = 32'd0;
    dmem[7644] = 32'd0;
    dmem[7645] = 32'd0;
    dmem[7646] = 32'd0;
    dmem[7647] = 32'd0;
    dmem[7648] = 32'd0;
    dmem[7649] = 32'd0;
    dmem[7650] = 32'd0;
    dmem[7651] = 32'd0;
    dmem[7652] = 32'd0;
    dmem[7653] = 32'd0;
    dmem[7654] = 32'd0;
    dmem[7655] = 32'd0;
    dmem[7656] = 32'd0;
    dmem[7657] = 32'd0;
    dmem[7658] = 32'd0;
    dmem[7659] = 32'd0;
    dmem[7660] = 32'd0;
    dmem[7661] = 32'd0;
    dmem[7662] = 32'd0;
    dmem[7663] = 32'd0;
    dmem[7664] = 32'd0;
    dmem[7665] = 32'd0;
    dmem[7666] = 32'd0;
    dmem[7667] = 32'd0;
    dmem[7668] = 32'd0;
    dmem[7669] = 32'd0;
    dmem[7670] = 32'd0;
    dmem[7671] = 32'd0;
    dmem[7672] = 32'd0;
    dmem[7673] = 32'd0;
    dmem[7674] = 32'd0;
    dmem[7675] = 32'd0;
    dmem[7676] = 32'd0;
    dmem[7677] = 32'd0;
    dmem[7678] = 32'd0;
    dmem[7679] = 32'd0;
    dmem[7680] = 32'd0;
    dmem[7681] = 32'd0;
    dmem[7682] = 32'd0;
    dmem[7683] = 32'd0;
    dmem[7684] = 32'd0;
    dmem[7685] = 32'd0;
    dmem[7686] = 32'd0;
    dmem[7687] = 32'd0;
    dmem[7688] = 32'd0;
    dmem[7689] = 32'd0;
    dmem[7690] = 32'd0;
    dmem[7691] = 32'd0;
    dmem[7692] = 32'd0;
    dmem[7693] = 32'd0;
    dmem[7694] = 32'd0;
    dmem[7695] = 32'd0;
    dmem[7696] = 32'd0;
    dmem[7697] = 32'd0;
    dmem[7698] = 32'd0;
    dmem[7699] = 32'd0;
    dmem[7700] = 32'd0;
    dmem[7701] = 32'd0;
    dmem[7702] = 32'd0;
    dmem[7703] = 32'd0;
    dmem[7704] = 32'd0;
    dmem[7705] = 32'd0;
    dmem[7706] = 32'd0;
    dmem[7707] = 32'd0;
    dmem[7708] = 32'd0;
    dmem[7709] = 32'd0;
    dmem[7710] = 32'd0;
    dmem[7711] = 32'd0;
    dmem[7712] = 32'd0;
    dmem[7713] = 32'd0;
    dmem[7714] = 32'd0;
    dmem[7715] = 32'd0;
    dmem[7716] = 32'd0;
    dmem[7717] = 32'd0;
    dmem[7718] = 32'd0;
    dmem[7719] = 32'd0;
    dmem[7720] = 32'd0;
    dmem[7721] = 32'd0;
    dmem[7722] = 32'd0;
    dmem[7723] = 32'd0;
    dmem[7724] = 32'd0;
    dmem[7725] = 32'd0;
    dmem[7726] = 32'd0;
    dmem[7727] = 32'd0;
    dmem[7728] = 32'd0;
    dmem[7729] = 32'd0;
    dmem[7730] = 32'd0;
    dmem[7731] = 32'd0;
    dmem[7732] = 32'd0;
    dmem[7733] = 32'd0;
    dmem[7734] = 32'd0;
    dmem[7735] = 32'd0;
    dmem[7736] = 32'd0;
    dmem[7737] = 32'd0;
    dmem[7738] = 32'd0;
    dmem[7739] = 32'd0;
    dmem[7740] = 32'd0;
    dmem[7741] = 32'd0;
    dmem[7742] = 32'd0;
    dmem[7743] = 32'd0;
    dmem[7744] = 32'd0;
    dmem[7745] = 32'd0;
    dmem[7746] = 32'd0;
    dmem[7747] = 32'd0;
    dmem[7748] = 32'd0;
    dmem[7749] = 32'd0;
    dmem[7750] = 32'd0;
    dmem[7751] = 32'd0;
    dmem[7752] = 32'd0;
    dmem[7753] = 32'd0;
    dmem[7754] = 32'd0;
    dmem[7755] = 32'd0;
    dmem[7756] = 32'd0;
    dmem[7757] = 32'd0;
    dmem[7758] = 32'd0;
    dmem[7759] = 32'd0;
    dmem[7760] = 32'd0;
    dmem[7761] = 32'd0;
    dmem[7762] = 32'd0;
    dmem[7763] = 32'd0;
    dmem[7764] = 32'd0;
    dmem[7765] = 32'd0;
    dmem[7766] = 32'd0;
    dmem[7767] = 32'd0;
    dmem[7768] = 32'd0;
    dmem[7769] = 32'd0;
    dmem[7770] = 32'd0;
    dmem[7771] = 32'd0;
    dmem[7772] = 32'd0;
    dmem[7773] = 32'd0;
    dmem[7774] = 32'd0;
    dmem[7775] = 32'd0;
    dmem[7776] = 32'd0;
    dmem[7777] = 32'd0;
    dmem[7778] = 32'd0;
    dmem[7779] = 32'd0;
    dmem[7780] = 32'd0;
    dmem[7781] = 32'd0;
    dmem[7782] = 32'd0;
    dmem[7783] = 32'd0;
    dmem[7784] = 32'd0;
    dmem[7785] = 32'd0;
    dmem[7786] = 32'd0;
    dmem[7787] = 32'd0;
    dmem[7788] = 32'd0;
    dmem[7789] = 32'd0;
    dmem[7790] = 32'd0;
    dmem[7791] = 32'd0;
    dmem[7792] = 32'd0;
    dmem[7793] = 32'd0;
    dmem[7794] = 32'd0;
    dmem[7795] = 32'd0;
    dmem[7796] = 32'd0;
    dmem[7797] = 32'd0;
    dmem[7798] = 32'd0;
    dmem[7799] = 32'd0;
    dmem[7800] = 32'd0;
    dmem[7801] = 32'd0;
    dmem[7802] = 32'd0;
    dmem[7803] = 32'd0;
    dmem[7804] = 32'd0;
    dmem[7805] = 32'd0;
    dmem[7806] = 32'd0;
    dmem[7807] = 32'd0;
    dmem[7808] = 32'd0;
    dmem[7809] = 32'd0;
    dmem[7810] = 32'd0;
    dmem[7811] = 32'd0;
    dmem[7812] = 32'd0;
    dmem[7813] = 32'd0;
    dmem[7814] = 32'd0;
    dmem[7815] = 32'd0;
    dmem[7816] = 32'd0;
    dmem[7817] = 32'd0;
    dmem[7818] = 32'd0;
    dmem[7819] = 32'd0;
    dmem[7820] = 32'd0;
    dmem[7821] = 32'd0;
    dmem[7822] = 32'd0;
    dmem[7823] = 32'd0;
    dmem[7824] = 32'd0;
    dmem[7825] = 32'd0;
    dmem[7826] = 32'd0;
    dmem[7827] = 32'd0;
    dmem[7828] = 32'd0;
    dmem[7829] = 32'd0;
    dmem[7830] = 32'd0;
    dmem[7831] = 32'd0;
    dmem[7832] = 32'd0;
    dmem[7833] = 32'd0;
    dmem[7834] = 32'd0;
    dmem[7835] = 32'd0;
    dmem[7836] = 32'd0;
    dmem[7837] = 32'd0;
    dmem[7838] = 32'd0;
    dmem[7839] = 32'd0;
    dmem[7840] = 32'd0;
    dmem[7841] = 32'd0;
    dmem[7842] = 32'd0;
    dmem[7843] = 32'd0;
    dmem[7844] = 32'd0;
    dmem[7845] = 32'd0;
    dmem[7846] = 32'd0;
    dmem[7847] = 32'd0;
    dmem[7848] = 32'd0;
    dmem[7849] = 32'd0;
    dmem[7850] = 32'd0;
    dmem[7851] = 32'd0;
    dmem[7852] = 32'd0;
    dmem[7853] = 32'd0;
    dmem[7854] = 32'd0;
    dmem[7855] = 32'd0;
    dmem[7856] = 32'd0;
    dmem[7857] = 32'd0;
    dmem[7858] = 32'd0;
    dmem[7859] = 32'd0;
    dmem[7860] = 32'd0;
    dmem[7861] = 32'd0;
    dmem[7862] = 32'd0;
    dmem[7863] = 32'd0;
    dmem[7864] = 32'd0;
    dmem[7865] = 32'd0;
    dmem[7866] = 32'd0;
    dmem[7867] = 32'd0;
    dmem[7868] = 32'd0;
    dmem[7869] = 32'd0;
    dmem[7870] = 32'd0;
    dmem[7871] = 32'd0;
    dmem[7872] = 32'd0;
    dmem[7873] = 32'd0;
    dmem[7874] = 32'd0;
    dmem[7875] = 32'd0;
    dmem[7876] = 32'd0;
    dmem[7877] = 32'd0;
    dmem[7878] = 32'd0;
    dmem[7879] = 32'd0;
    dmem[7880] = 32'd0;
    dmem[7881] = 32'd0;
    dmem[7882] = 32'd0;
    dmem[7883] = 32'd0;
    dmem[7884] = 32'd0;
    dmem[7885] = 32'd0;
    dmem[7886] = 32'd0;
    dmem[7887] = 32'd0;
    dmem[7888] = 32'd0;
    dmem[7889] = 32'd0;
    dmem[7890] = 32'd0;
    dmem[7891] = 32'd0;
    dmem[7892] = 32'd0;
    dmem[7893] = 32'd0;
    dmem[7894] = 32'd0;
    dmem[7895] = 32'd0;
    dmem[7896] = 32'd0;
    dmem[7897] = 32'd0;
    dmem[7898] = 32'd0;
    dmem[7899] = 32'd0;
    dmem[7900] = 32'd0;
    dmem[7901] = 32'd0;
    dmem[7902] = 32'd0;
    dmem[7903] = 32'd0;
    dmem[7904] = 32'd0;
    dmem[7905] = 32'd0;
    dmem[7906] = 32'd0;
    dmem[7907] = 32'd0;
    dmem[7908] = 32'd0;
    dmem[7909] = 32'd0;
    dmem[7910] = 32'd0;
    dmem[7911] = 32'd0;
    dmem[7912] = 32'd0;
    dmem[7913] = 32'd0;
    dmem[7914] = 32'd0;
    dmem[7915] = 32'd0;
    dmem[7916] = 32'd0;
    dmem[7917] = 32'd0;
    dmem[7918] = 32'd0;
    dmem[7919] = 32'd0;
    dmem[7920] = 32'd0;
    dmem[7921] = 32'd0;
    dmem[7922] = 32'd0;
    dmem[7923] = 32'd0;
    dmem[7924] = 32'd0;
    dmem[7925] = 32'd0;
    dmem[7926] = 32'd0;
    dmem[7927] = 32'd0;
    dmem[7928] = 32'd0;
    dmem[7929] = 32'd0;
    dmem[7930] = 32'd0;
    dmem[7931] = 32'd0;
    dmem[7932] = 32'd0;
    dmem[7933] = 32'd0;
    dmem[7934] = 32'd0;
    dmem[7935] = 32'd0;
    dmem[7936] = 32'd0;
    dmem[7937] = 32'd0;
    dmem[7938] = 32'd0;
    dmem[7939] = 32'd0;
    dmem[7940] = 32'd0;
    dmem[7941] = 32'd0;
    dmem[7942] = 32'd0;
    dmem[7943] = 32'd0;
    dmem[7944] = 32'd0;
    dmem[7945] = 32'd0;
    dmem[7946] = 32'd0;
    dmem[7947] = 32'd0;
    dmem[7948] = 32'd0;
    dmem[7949] = 32'd0;
    dmem[7950] = 32'd0;
    dmem[7951] = 32'd0;
    dmem[7952] = 32'd0;
    dmem[7953] = 32'd0;
    dmem[7954] = 32'd0;
    dmem[7955] = 32'd0;
    dmem[7956] = 32'd0;
    dmem[7957] = 32'd0;
    dmem[7958] = 32'd0;
    dmem[7959] = 32'd0;
    dmem[7960] = 32'd0;
    dmem[7961] = 32'd0;
    dmem[7962] = 32'd0;
    dmem[7963] = 32'd0;
    dmem[7964] = 32'd0;
    dmem[7965] = 32'd0;
    dmem[7966] = 32'd0;
    dmem[7967] = 32'd0;
    dmem[7968] = 32'd0;
    dmem[7969] = 32'd0;
    dmem[7970] = 32'd0;
    dmem[7971] = 32'd0;
    dmem[7972] = 32'd0;
    dmem[7973] = 32'd0;
    dmem[7974] = 32'd0;
    dmem[7975] = 32'd0;
    dmem[7976] = 32'd0;
    dmem[7977] = 32'd0;
    dmem[7978] = 32'd0;
    dmem[7979] = 32'd0;
    dmem[7980] = 32'd0;
    dmem[7981] = 32'd0;
    dmem[7982] = 32'd0;
    dmem[7983] = 32'd0;
    dmem[7984] = 32'd0;
    dmem[7985] = 32'd0;
    dmem[7986] = 32'd0;
    dmem[7987] = 32'd0;
    dmem[7988] = 32'd0;
    dmem[7989] = 32'd0;
    dmem[7990] = 32'd0;
    dmem[7991] = 32'd0;
    dmem[7992] = 32'd0;
    dmem[7993] = 32'd0;
    dmem[7994] = 32'd0;
    dmem[7995] = 32'd0;
    dmem[7996] = 32'd0;
    dmem[7997] = 32'd0;
    dmem[7998] = 32'd0;
    dmem[7999] = 32'd0;
    dmem[8000] = 32'd0;
    dmem[8001] = 32'd0;
    dmem[8002] = 32'd0;
    dmem[8003] = 32'd0;
    dmem[8004] = 32'd0;
    dmem[8005] = 32'd0;
    dmem[8006] = 32'd0;
    dmem[8007] = 32'd0;
    dmem[8008] = 32'd0;
    dmem[8009] = 32'd0;
    dmem[8010] = 32'd0;
    dmem[8011] = 32'd0;
    dmem[8012] = 32'd0;
    dmem[8013] = 32'd0;
    dmem[8014] = 32'd0;
    dmem[8015] = 32'd0;
    dmem[8016] = 32'd0;
    dmem[8017] = 32'd0;
    dmem[8018] = 32'd0;
    dmem[8019] = 32'd0;
    dmem[8020] = 32'd0;
    dmem[8021] = 32'd0;
    dmem[8022] = 32'd0;
    dmem[8023] = 32'd0;
    dmem[8024] = 32'd0;
    dmem[8025] = 32'd0;
    dmem[8026] = 32'd0;
    dmem[8027] = 32'd0;
    dmem[8028] = 32'd0;
    dmem[8029] = 32'd0;
    dmem[8030] = 32'd0;
    dmem[8031] = 32'd0;
    dmem[8032] = 32'd0;
    dmem[8033] = 32'd0;
    dmem[8034] = 32'd0;
    dmem[8035] = 32'd0;
    dmem[8036] = 32'd0;
    dmem[8037] = 32'd0;
    dmem[8038] = 32'd0;
    dmem[8039] = 32'd0;
    dmem[8040] = 32'd0;
    dmem[8041] = 32'd0;
    dmem[8042] = 32'd0;
    dmem[8043] = 32'd0;
    dmem[8044] = 32'd0;
    dmem[8045] = 32'd0;
    dmem[8046] = 32'd0;
    dmem[8047] = 32'd0;
    dmem[8048] = 32'd0;
    dmem[8049] = 32'd0;
    dmem[8050] = 32'd0;
    dmem[8051] = 32'd0;
    dmem[8052] = 32'd0;
    dmem[8053] = 32'd0;
    dmem[8054] = 32'd0;
    dmem[8055] = 32'd0;
    dmem[8056] = 32'd0;
    dmem[8057] = 32'd0;
    dmem[8058] = 32'd0;
    dmem[8059] = 32'd0;
    dmem[8060] = 32'd0;
    dmem[8061] = 32'd0;
    dmem[8062] = 32'd0;
    dmem[8063] = 32'd0;
    dmem[8064] = 32'd0;
    dmem[8065] = 32'd0;
    dmem[8066] = 32'd0;
    dmem[8067] = 32'd0;
    dmem[8068] = 32'd0;
    dmem[8069] = 32'd0;
    dmem[8070] = 32'd0;
    dmem[8071] = 32'd0;
    dmem[8072] = 32'd0;
    dmem[8073] = 32'd0;
    dmem[8074] = 32'd0;
    dmem[8075] = 32'd0;
    dmem[8076] = 32'd0;
    dmem[8077] = 32'd0;
    dmem[8078] = 32'd0;
    dmem[8079] = 32'd0;
    dmem[8080] = 32'd0;
    dmem[8081] = 32'd0;
    dmem[8082] = 32'd0;
    dmem[8083] = 32'd0;
    dmem[8084] = 32'd0;
    dmem[8085] = 32'd0;
    dmem[8086] = 32'd0;
    dmem[8087] = 32'd0;
    dmem[8088] = 32'd0;
    dmem[8089] = 32'd0;
    dmem[8090] = 32'd0;
    dmem[8091] = 32'd0;
    dmem[8092] = 32'd0;
    dmem[8093] = 32'd0;
    dmem[8094] = 32'd0;
    dmem[8095] = 32'd0;
    dmem[8096] = 32'd0;
    dmem[8097] = 32'd0;
    dmem[8098] = 32'd0;
    dmem[8099] = 32'd0;
    dmem[8100] = 32'd0;
    dmem[8101] = 32'd0;
    dmem[8102] = 32'd0;
    dmem[8103] = 32'd0;
    dmem[8104] = 32'd0;
    dmem[8105] = 32'd0;
    dmem[8106] = 32'd0;
    dmem[8107] = 32'd0;
    dmem[8108] = 32'd0;
    dmem[8109] = 32'd0;
    dmem[8110] = 32'd0;
    dmem[8111] = 32'd0;
    dmem[8112] = 32'd0;
    dmem[8113] = 32'd0;
    dmem[8114] = 32'd0;
    dmem[8115] = 32'd0;
    dmem[8116] = 32'd0;
    dmem[8117] = 32'd0;
    dmem[8118] = 32'd0;
    dmem[8119] = 32'd0;
    dmem[8120] = 32'd0;
    dmem[8121] = 32'd0;
    dmem[8122] = 32'd0;
    dmem[8123] = 32'd0;
    dmem[8124] = 32'd0;
    dmem[8125] = 32'd0;
    dmem[8126] = 32'd0;
    dmem[8127] = 32'd0;
    dmem[8128] = 32'd0;
    dmem[8129] = 32'd0;
    dmem[8130] = 32'd0;
    dmem[8131] = 32'd0;
    dmem[8132] = 32'd0;
    dmem[8133] = 32'd0;
    dmem[8134] = 32'd0;
    dmem[8135] = 32'd0;
    dmem[8136] = 32'd0;
    dmem[8137] = 32'd0;
    dmem[8138] = 32'd0;
    dmem[8139] = 32'd0;
    dmem[8140] = 32'd0;
    dmem[8141] = 32'd0;
    dmem[8142] = 32'd0;
    dmem[8143] = 32'd0;
    dmem[8144] = 32'd0;
    dmem[8145] = 32'd0;
    dmem[8146] = 32'd0;
    dmem[8147] = 32'd0;
    dmem[8148] = 32'd0;
    dmem[8149] = 32'd0;
    dmem[8150] = 32'd0;
    dmem[8151] = 32'd0;
    dmem[8152] = 32'd0;
    dmem[8153] = 32'd0;
    dmem[8154] = 32'd0;
    dmem[8155] = 32'd0;
    dmem[8156] = 32'd0;
    dmem[8157] = 32'd0;
    dmem[8158] = 32'd0;
    dmem[8159] = 32'd0;
    dmem[8160] = 32'd0;
    dmem[8161] = 32'd0;
    dmem[8162] = 32'd0;
    dmem[8163] = 32'd0;
    dmem[8164] = 32'd0;
    dmem[8165] = 32'd0;
    dmem[8166] = 32'd0;
    dmem[8167] = 32'd0;
    dmem[8168] = 32'd0;
    dmem[8169] = 32'd0;
    dmem[8170] = 32'd0;
    dmem[8171] = 32'd0;
    dmem[8172] = 32'd0;
    dmem[8173] = 32'd0;
    dmem[8174] = 32'd0;
    dmem[8175] = 32'd0;
    dmem[8176] = 32'd0;
    dmem[8177] = 32'd0;
    dmem[8178] = 32'd0;
    dmem[8179] = 32'd0;
    dmem[8180] = 32'd0;
    dmem[8181] = 32'd0;
    dmem[8182] = 32'd0;
    dmem[8183] = 32'd0;
    dmem[8184] = 32'd0;
    dmem[8185] = 32'd0;
    dmem[8186] = 32'd0;
    dmem[8187] = 32'd0;
    dmem[8188] = 32'd0;
    dmem[8189] = 32'd0;
    dmem[8190] = 32'd0;
    dmem[8191] = 32'd0;
    dmem[8192] = 32'd0;
    dmem[8193] = 32'd0;
    dmem[8194] = 32'd0;
    dmem[8195] = 32'd0;
    dmem[8196] = 32'd0;
    dmem[8197] = 32'd0;
    dmem[8198] = 32'd0;
    dmem[8199] = 32'd0;
    dmem[8200] = 32'd0;
    dmem[8201] = 32'd0;
    dmem[8202] = 32'd0;
    dmem[8203] = 32'd0;
    dmem[8204] = 32'd0;
    dmem[8205] = 32'd0;
    dmem[8206] = 32'd0;
    dmem[8207] = 32'd0;
    dmem[8208] = 32'd0;
    dmem[8209] = 32'd0;
    dmem[8210] = 32'd0;
    dmem[8211] = 32'd0;
    dmem[8212] = 32'd0;
    dmem[8213] = 32'd0;
    dmem[8214] = 32'd0;
    dmem[8215] = 32'd0;
    dmem[8216] = 32'd0;
    dmem[8217] = 32'd0;
    dmem[8218] = 32'd0;
    dmem[8219] = 32'd0;
    dmem[8220] = 32'd0;
    dmem[8221] = 32'd0;
    dmem[8222] = 32'd0;
    dmem[8223] = 32'd0;
    dmem[8224] = 32'd0;
    dmem[8225] = 32'd0;
    dmem[8226] = 32'd0;
    dmem[8227] = 32'd0;
    dmem[8228] = 32'd0;
    dmem[8229] = 32'd0;
    dmem[8230] = 32'd0;
    dmem[8231] = 32'd0;
    dmem[8232] = 32'd0;
    dmem[8233] = 32'd0;
    dmem[8234] = 32'd0;
    dmem[8235] = 32'd0;
    dmem[8236] = 32'd0;
    dmem[8237] = 32'd0;
    dmem[8238] = 32'd0;
    dmem[8239] = 32'd0;
    dmem[8240] = 32'd0;
    dmem[8241] = 32'd0;
    dmem[8242] = 32'd0;
    dmem[8243] = 32'd0;
    dmem[8244] = 32'd0;
    dmem[8245] = 32'd0;
    dmem[8246] = 32'd0;
    dmem[8247] = 32'd0;
    dmem[8248] = 32'd0;
    dmem[8249] = 32'd0;
    dmem[8250] = 32'd0;
    dmem[8251] = 32'd0;
    dmem[8252] = 32'd0;
    dmem[8253] = 32'd0;
    dmem[8254] = 32'd0;
    dmem[8255] = 32'd0;
    dmem[8256] = 32'd0;
    dmem[8257] = 32'd0;
    dmem[8258] = 32'd0;
    dmem[8259] = 32'd0;
    dmem[8260] = 32'd0;
    dmem[8261] = 32'd0;
    dmem[8262] = 32'd0;
    dmem[8263] = 32'd0;
    dmem[8264] = 32'd0;
    dmem[8265] = 32'd0;
    dmem[8266] = 32'd0;
    dmem[8267] = 32'd0;
    dmem[8268] = 32'd0;
    dmem[8269] = 32'd0;
    dmem[8270] = 32'd0;
    dmem[8271] = 32'd0;
    dmem[8272] = 32'd0;
    dmem[8273] = 32'd0;
    dmem[8274] = 32'd0;
    dmem[8275] = 32'd0;
    dmem[8276] = 32'd0;
    dmem[8277] = 32'd0;
    dmem[8278] = 32'd0;
    dmem[8279] = 32'd0;
    dmem[8280] = 32'd0;
    dmem[8281] = 32'd0;
    dmem[8282] = 32'd0;
    dmem[8283] = 32'd0;
    dmem[8284] = 32'd0;
    dmem[8285] = 32'd0;
    dmem[8286] = 32'd0;
    dmem[8287] = 32'd0;
    dmem[8288] = 32'd0;
    dmem[8289] = 32'd0;
    dmem[8290] = 32'd0;
    dmem[8291] = 32'd0;
    dmem[8292] = 32'd0;
    dmem[8293] = 32'd0;
    dmem[8294] = 32'd0;
    dmem[8295] = 32'd0;
    dmem[8296] = 32'd0;
    dmem[8297] = 32'd0;
    dmem[8298] = 32'd0;
    dmem[8299] = 32'd0;
    dmem[8300] = 32'd0;
    dmem[8301] = 32'd0;
    dmem[8302] = 32'd0;
    dmem[8303] = 32'd0;
    dmem[8304] = 32'd0;
    dmem[8305] = 32'd0;
    dmem[8306] = 32'd0;
    dmem[8307] = 32'd0;
    dmem[8308] = 32'd0;
    dmem[8309] = 32'd0;
    dmem[8310] = 32'd0;
    dmem[8311] = 32'd0;
    dmem[8312] = 32'd0;
    dmem[8313] = 32'd0;
    dmem[8314] = 32'd0;
    dmem[8315] = 32'd0;
    dmem[8316] = 32'd0;
    dmem[8317] = 32'd0;
    dmem[8318] = 32'd0;
    dmem[8319] = 32'd0;
    dmem[8320] = 32'd0;
    dmem[8321] = 32'd0;
    dmem[8322] = 32'd0;
    dmem[8323] = 32'd0;
    dmem[8324] = 32'd0;
    dmem[8325] = 32'd0;
    dmem[8326] = 32'd0;
    dmem[8327] = 32'd0;
    dmem[8328] = 32'd0;
    dmem[8329] = 32'd0;
    dmem[8330] = 32'd0;
    dmem[8331] = 32'd0;
    dmem[8332] = 32'd0;
    dmem[8333] = 32'd0;
    dmem[8334] = 32'd0;
    dmem[8335] = 32'd0;
    dmem[8336] = 32'd0;
    dmem[8337] = 32'd0;
    dmem[8338] = 32'd0;
    dmem[8339] = 32'd0;
    dmem[8340] = 32'd0;
    dmem[8341] = 32'd0;
    dmem[8342] = 32'd0;
    dmem[8343] = 32'd0;
    dmem[8344] = 32'd0;
    dmem[8345] = 32'd0;
    dmem[8346] = 32'd0;
    dmem[8347] = 32'd0;
    dmem[8348] = 32'd0;
    dmem[8349] = 32'd0;
    dmem[8350] = 32'd0;
    dmem[8351] = 32'd0;
    dmem[8352] = 32'd0;
    dmem[8353] = 32'd0;
    dmem[8354] = 32'd0;
    dmem[8355] = 32'd0;
    dmem[8356] = 32'd0;
    dmem[8357] = 32'd0;
    dmem[8358] = 32'd0;
    dmem[8359] = 32'd0;
    dmem[8360] = 32'd0;
    dmem[8361] = 32'd0;
    dmem[8362] = 32'd0;
    dmem[8363] = 32'd0;
    dmem[8364] = 32'd0;
    dmem[8365] = 32'd0;
    dmem[8366] = 32'd0;
    dmem[8367] = 32'd0;
    dmem[8368] = 32'd0;
    dmem[8369] = 32'd0;
    dmem[8370] = 32'd0;
    dmem[8371] = 32'd0;
    dmem[8372] = 32'd0;
    dmem[8373] = 32'd0;
    dmem[8374] = 32'd0;
    dmem[8375] = 32'd0;
    dmem[8376] = 32'd0;
    dmem[8377] = 32'd0;
    dmem[8378] = 32'd0;
    dmem[8379] = 32'd0;
    dmem[8380] = 32'd0;
    dmem[8381] = 32'd0;
    dmem[8382] = 32'd0;
    dmem[8383] = 32'd0;
    dmem[8384] = 32'd0;
    dmem[8385] = 32'd0;
    dmem[8386] = 32'd0;
    dmem[8387] = 32'd0;
    dmem[8388] = 32'd0;
    dmem[8389] = 32'd0;
    dmem[8390] = 32'd0;
    dmem[8391] = 32'd0;
    dmem[8392] = 32'd0;
    dmem[8393] = 32'd0;
    dmem[8394] = 32'd0;
    dmem[8395] = 32'd0;
    dmem[8396] = 32'd0;
    dmem[8397] = 32'd0;
    dmem[8398] = 32'd0;
    dmem[8399] = 32'd0;
    dmem[8400] = 32'd0;
    dmem[8401] = 32'd0;
    dmem[8402] = 32'd0;
    dmem[8403] = 32'd0;
    dmem[8404] = 32'd0;
    dmem[8405] = 32'd0;
    dmem[8406] = 32'd0;
    dmem[8407] = 32'd0;
    dmem[8408] = 32'd0;
    dmem[8409] = 32'd0;
    dmem[8410] = 32'd0;
    dmem[8411] = 32'd0;
    dmem[8412] = 32'd0;
    dmem[8413] = 32'd0;
    dmem[8414] = 32'd0;
    dmem[8415] = 32'd0;
    dmem[8416] = 32'd0;
    dmem[8417] = 32'd0;
    dmem[8418] = 32'd0;
    dmem[8419] = 32'd0;
    dmem[8420] = 32'd0;
    dmem[8421] = 32'd0;
    dmem[8422] = 32'd0;
    dmem[8423] = 32'd0;
    dmem[8424] = 32'd0;
    dmem[8425] = 32'd0;
    dmem[8426] = 32'd0;
    dmem[8427] = 32'd0;
    dmem[8428] = 32'd0;
    dmem[8429] = 32'd0;
    dmem[8430] = 32'd0;
    dmem[8431] = 32'd0;
    dmem[8432] = 32'd0;
    dmem[8433] = 32'd0;
    dmem[8434] = 32'd0;
    dmem[8435] = 32'd0;
    dmem[8436] = 32'd0;
    dmem[8437] = 32'd0;
    dmem[8438] = 32'd0;
    dmem[8439] = 32'd0;
    dmem[8440] = 32'd0;
    dmem[8441] = 32'd0;
    dmem[8442] = 32'd0;
    dmem[8443] = 32'd0;
    dmem[8444] = 32'd0;
    dmem[8445] = 32'd0;
    dmem[8446] = 32'd0;
    dmem[8447] = 32'd0;
    dmem[8448] = 32'd0;
    dmem[8449] = 32'd0;
    dmem[8450] = 32'd0;
    dmem[8451] = 32'd0;
    dmem[8452] = 32'd0;
    dmem[8453] = 32'd0;
    dmem[8454] = 32'd0;
    dmem[8455] = 32'd0;
    dmem[8456] = 32'd0;
    dmem[8457] = 32'd0;
    dmem[8458] = 32'd0;
    dmem[8459] = 32'd0;
    dmem[8460] = 32'd0;
    dmem[8461] = 32'd0;
    dmem[8462] = 32'd0;
    dmem[8463] = 32'd0;
    dmem[8464] = 32'd0;
    dmem[8465] = 32'd0;
    dmem[8466] = 32'd0;
    dmem[8467] = 32'd0;
    dmem[8468] = 32'd0;
    dmem[8469] = 32'd0;
    dmem[8470] = 32'd0;
    dmem[8471] = 32'd0;
    dmem[8472] = 32'd0;
    dmem[8473] = 32'd0;
    dmem[8474] = 32'd0;
    dmem[8475] = 32'd0;
    dmem[8476] = 32'd0;
    dmem[8477] = 32'd0;
    dmem[8478] = 32'd0;
    dmem[8479] = 32'd0;
    dmem[8480] = 32'd0;
    dmem[8481] = 32'd0;
    dmem[8482] = 32'd0;
    dmem[8483] = 32'd0;
    dmem[8484] = 32'd0;
    dmem[8485] = 32'd0;
    dmem[8486] = 32'd0;
    dmem[8487] = 32'd0;
    dmem[8488] = 32'd0;
    dmem[8489] = 32'd0;
    dmem[8490] = 32'd0;
    dmem[8491] = 32'd0;
    dmem[8492] = 32'd0;
    dmem[8493] = 32'd0;
    dmem[8494] = 32'd0;
    dmem[8495] = 32'd0;
    dmem[8496] = 32'd0;
    dmem[8497] = 32'd0;
    dmem[8498] = 32'd0;
    dmem[8499] = 32'd0;
    dmem[8500] = 32'd0;
    dmem[8501] = 32'd0;
    dmem[8502] = 32'd0;
    dmem[8503] = 32'd0;
    dmem[8504] = 32'd0;
    dmem[8505] = 32'd0;
    dmem[8506] = 32'd0;
    dmem[8507] = 32'd0;
    dmem[8508] = 32'd0;
    dmem[8509] = 32'd0;
    dmem[8510] = 32'd0;
    dmem[8511] = 32'd0;
    dmem[8512] = 32'd0;
    dmem[8513] = 32'd0;
    dmem[8514] = 32'd0;
    dmem[8515] = 32'd0;
    dmem[8516] = 32'd0;
    dmem[8517] = 32'd0;
    dmem[8518] = 32'd0;
    dmem[8519] = 32'd0;
    dmem[8520] = 32'd0;
    dmem[8521] = 32'd0;
    dmem[8522] = 32'd0;
    dmem[8523] = 32'd0;
    dmem[8524] = 32'd0;
    dmem[8525] = 32'd0;
    dmem[8526] = 32'd0;
    dmem[8527] = 32'd0;
    dmem[8528] = 32'd0;
    dmem[8529] = 32'd0;
    dmem[8530] = 32'd0;
    dmem[8531] = 32'd0;
    dmem[8532] = 32'd0;
    dmem[8533] = 32'd0;
    dmem[8534] = 32'd0;
    dmem[8535] = 32'd0;
    dmem[8536] = 32'd0;
    dmem[8537] = 32'd0;
    dmem[8538] = 32'd0;
    dmem[8539] = 32'd0;
    dmem[8540] = 32'd0;
    dmem[8541] = 32'd0;
    dmem[8542] = 32'd0;
    dmem[8543] = 32'd0;
    dmem[8544] = 32'd0;
    dmem[8545] = 32'd0;
    dmem[8546] = 32'd0;
    dmem[8547] = 32'd0;
    dmem[8548] = 32'd0;
    dmem[8549] = 32'd0;
    dmem[8550] = 32'd0;
    dmem[8551] = 32'd0;
    dmem[8552] = 32'd0;
    dmem[8553] = 32'd0;
    dmem[8554] = 32'd0;
    dmem[8555] = 32'd0;
    dmem[8556] = 32'd0;
    dmem[8557] = 32'd0;
    dmem[8558] = 32'd0;
    dmem[8559] = 32'd0;
    dmem[8560] = 32'd0;
    dmem[8561] = 32'd0;
    dmem[8562] = 32'd0;
    dmem[8563] = 32'd0;
    dmem[8564] = 32'd0;
    dmem[8565] = 32'd0;
    dmem[8566] = 32'd0;
    dmem[8567] = 32'd0;
    dmem[8568] = 32'd0;
    dmem[8569] = 32'd0;
    dmem[8570] = 32'd0;
    dmem[8571] = 32'd0;
    dmem[8572] = 32'd0;
    dmem[8573] = 32'd0;
    dmem[8574] = 32'd0;
    dmem[8575] = 32'd0;
    dmem[8576] = 32'd0;
    dmem[8577] = 32'd0;
    dmem[8578] = 32'd0;
    dmem[8579] = 32'd0;
    dmem[8580] = 32'd0;
    dmem[8581] = 32'd0;
    dmem[8582] = 32'd0;
    dmem[8583] = 32'd0;
    dmem[8584] = 32'd0;
    dmem[8585] = 32'd0;
    dmem[8586] = 32'd0;
    dmem[8587] = 32'd0;
    dmem[8588] = 32'd0;
    dmem[8589] = 32'd0;
    dmem[8590] = 32'd0;
    dmem[8591] = 32'd0;
    dmem[8592] = 32'd0;
    dmem[8593] = 32'd0;
    dmem[8594] = 32'd0;
    dmem[8595] = 32'd0;
    dmem[8596] = 32'd0;
    dmem[8597] = 32'd0;
    dmem[8598] = 32'd0;
    dmem[8599] = 32'd0;
    dmem[8600] = 32'd0;
    dmem[8601] = 32'd0;
    dmem[8602] = 32'd0;
    dmem[8603] = 32'd0;
    dmem[8604] = 32'd0;
    dmem[8605] = 32'd0;
    dmem[8606] = 32'd0;
    dmem[8607] = 32'd0;
    dmem[8608] = 32'd0;
    dmem[8609] = 32'd0;
    dmem[8610] = 32'd0;
    dmem[8611] = 32'd0;
    dmem[8612] = 32'd0;
    dmem[8613] = 32'd0;
    dmem[8614] = 32'd0;
    dmem[8615] = 32'd0;
    dmem[8616] = 32'd0;
    dmem[8617] = 32'd0;
    dmem[8618] = 32'd0;
    dmem[8619] = 32'd0;
    dmem[8620] = 32'd0;
    dmem[8621] = 32'd0;
    dmem[8622] = 32'd0;
    dmem[8623] = 32'd0;
    dmem[8624] = 32'd0;
    dmem[8625] = 32'd0;
    dmem[8626] = 32'd0;
    dmem[8627] = 32'd0;
    dmem[8628] = 32'd0;
    dmem[8629] = 32'd0;
    dmem[8630] = 32'd0;
    dmem[8631] = 32'd0;
    dmem[8632] = 32'd0;
    dmem[8633] = 32'd0;
    dmem[8634] = 32'd0;
    dmem[8635] = 32'd0;
    dmem[8636] = 32'd0;
    dmem[8637] = 32'd0;
    dmem[8638] = 32'd0;
    dmem[8639] = 32'd0;
    dmem[8640] = 32'd0;
    dmem[8641] = 32'd0;
    dmem[8642] = 32'd0;
    dmem[8643] = 32'd0;
    dmem[8644] = 32'd0;
    dmem[8645] = 32'd0;
    dmem[8646] = 32'd0;
    dmem[8647] = 32'd0;
    dmem[8648] = 32'd0;
    dmem[8649] = 32'd0;
    dmem[8650] = 32'd0;
    dmem[8651] = 32'd0;
    dmem[8652] = 32'd0;
    dmem[8653] = 32'd0;
    dmem[8654] = 32'd0;
    dmem[8655] = 32'd0;
    dmem[8656] = 32'd0;
    dmem[8657] = 32'd0;
    dmem[8658] = 32'd0;
    dmem[8659] = 32'd0;
    dmem[8660] = 32'd0;
    dmem[8661] = 32'd0;
    dmem[8662] = 32'd0;
    dmem[8663] = 32'd0;
    dmem[8664] = 32'd0;
    dmem[8665] = 32'd0;
    dmem[8666] = 32'd0;
    dmem[8667] = 32'd0;
    dmem[8668] = 32'd0;
    dmem[8669] = 32'd0;
    dmem[8670] = 32'd0;
    dmem[8671] = 32'd0;
    dmem[8672] = 32'd0;
    dmem[8673] = 32'd0;
    dmem[8674] = 32'd0;
    dmem[8675] = 32'd0;
    dmem[8676] = 32'd0;
    dmem[8677] = 32'd0;
    dmem[8678] = 32'd0;
    dmem[8679] = 32'd0;
    dmem[8680] = 32'd0;
    dmem[8681] = 32'd0;
    dmem[8682] = 32'd0;
    dmem[8683] = 32'd0;
    dmem[8684] = 32'd0;
    dmem[8685] = 32'd0;
    dmem[8686] = 32'd0;
    dmem[8687] = 32'd0;
    dmem[8688] = 32'd0;
    dmem[8689] = 32'd0;
    dmem[8690] = 32'd0;
    dmem[8691] = 32'd0;
    dmem[8692] = 32'd0;
    dmem[8693] = 32'd0;
    dmem[8694] = 32'd0;
    dmem[8695] = 32'd0;
    dmem[8696] = 32'd0;
    dmem[8697] = 32'd0;
    dmem[8698] = 32'd0;
    dmem[8699] = 32'd0;
    dmem[8700] = 32'd0;
    dmem[8701] = 32'd0;
    dmem[8702] = 32'd0;
    dmem[8703] = 32'd0;
    dmem[8704] = 32'd0;
    dmem[8705] = 32'd0;
    dmem[8706] = 32'd0;
    dmem[8707] = 32'd0;
    dmem[8708] = 32'd0;
    dmem[8709] = 32'd0;
    dmem[8710] = 32'd0;
    dmem[8711] = 32'd0;
    dmem[8712] = 32'd0;
    dmem[8713] = 32'd0;
    dmem[8714] = 32'd0;
    dmem[8715] = 32'd0;
    dmem[8716] = 32'd0;
    dmem[8717] = 32'd0;
    dmem[8718] = 32'd0;
    dmem[8719] = 32'd0;
    dmem[8720] = 32'd0;
    dmem[8721] = 32'd0;
    dmem[8722] = 32'd0;
    dmem[8723] = 32'd0;
    dmem[8724] = 32'd0;
    dmem[8725] = 32'd0;
    dmem[8726] = 32'd0;
    dmem[8727] = 32'd0;
    dmem[8728] = 32'd0;
    dmem[8729] = 32'd0;
    dmem[8730] = 32'd0;
    dmem[8731] = 32'd0;
    dmem[8732] = 32'd0;
    dmem[8733] = 32'd0;
    dmem[8734] = 32'd0;
    dmem[8735] = 32'd0;
    dmem[8736] = 32'd0;
    dmem[8737] = 32'd0;
    dmem[8738] = 32'd0;
    dmem[8739] = 32'd0;
    dmem[8740] = 32'd0;
    dmem[8741] = 32'd0;
    dmem[8742] = 32'd0;
    dmem[8743] = 32'd0;
    dmem[8744] = 32'd0;
    dmem[8745] = 32'd0;
    dmem[8746] = 32'd0;
    dmem[8747] = 32'd0;
    dmem[8748] = 32'd0;
    dmem[8749] = 32'd0;
    dmem[8750] = 32'd0;
    dmem[8751] = 32'd0;
    dmem[8752] = 32'd0;
    dmem[8753] = 32'd0;
    dmem[8754] = 32'd0;
    dmem[8755] = 32'd0;
    dmem[8756] = 32'd0;
    dmem[8757] = 32'd0;
    dmem[8758] = 32'd0;
    dmem[8759] = 32'd0;
    dmem[8760] = 32'd0;
    dmem[8761] = 32'd0;
    dmem[8762] = 32'd0;
    dmem[8763] = 32'd0;
    dmem[8764] = 32'd0;
    dmem[8765] = 32'd0;
    dmem[8766] = 32'd0;
    dmem[8767] = 32'd0;
    dmem[8768] = 32'd0;
    dmem[8769] = 32'd0;
    dmem[8770] = 32'd0;
    dmem[8771] = 32'd0;
    dmem[8772] = 32'd0;
    dmem[8773] = 32'd0;
    dmem[8774] = 32'd0;
    dmem[8775] = 32'd0;
    dmem[8776] = 32'd0;
    dmem[8777] = 32'd0;
    dmem[8778] = 32'd0;
    dmem[8779] = 32'd0;
    dmem[8780] = 32'd0;
    dmem[8781] = 32'd0;
    dmem[8782] = 32'd0;
    dmem[8783] = 32'd0;
    dmem[8784] = 32'd0;
    dmem[8785] = 32'd0;
    dmem[8786] = 32'd0;
    dmem[8787] = 32'd0;
    dmem[8788] = 32'd0;
    dmem[8789] = 32'd0;
    dmem[8790] = 32'd0;
    dmem[8791] = 32'd0;
    dmem[8792] = 32'd0;
    dmem[8793] = 32'd0;
    dmem[8794] = 32'd0;
    dmem[8795] = 32'd0;
    dmem[8796] = 32'd0;
    dmem[8797] = 32'd0;
    dmem[8798] = 32'd0;
    dmem[8799] = 32'd0;
    dmem[8800] = 32'd0;
    dmem[8801] = 32'd0;
    dmem[8802] = 32'd0;
    dmem[8803] = 32'd0;
    dmem[8804] = 32'd0;
    dmem[8805] = 32'd0;
    dmem[8806] = 32'd0;
    dmem[8807] = 32'd0;
    dmem[8808] = 32'd0;
    dmem[8809] = 32'd0;
    dmem[8810] = 32'd0;
    dmem[8811] = 32'd0;
    dmem[8812] = 32'd0;
    dmem[8813] = 32'd0;
    dmem[8814] = 32'd0;
    dmem[8815] = 32'd0;
    dmem[8816] = 32'd0;
    dmem[8817] = 32'd0;
    dmem[8818] = 32'd0;
    dmem[8819] = 32'd0;
    dmem[8820] = 32'd0;
    dmem[8821] = 32'd0;
    dmem[8822] = 32'd0;
    dmem[8823] = 32'd0;
    dmem[8824] = 32'd0;
    dmem[8825] = 32'd0;
    dmem[8826] = 32'd0;
    dmem[8827] = 32'd0;
    dmem[8828] = 32'd0;
    dmem[8829] = 32'd0;
    dmem[8830] = 32'd0;
    dmem[8831] = 32'd0;
    dmem[8832] = 32'd0;
    dmem[8833] = 32'd0;
    dmem[8834] = 32'd0;
    dmem[8835] = 32'd0;
    dmem[8836] = 32'd0;
    dmem[8837] = 32'd0;
    dmem[8838] = 32'd0;
    dmem[8839] = 32'd0;
    dmem[8840] = 32'd0;
    dmem[8841] = 32'd0;
    dmem[8842] = 32'd0;
    dmem[8843] = 32'd0;
    dmem[8844] = 32'd0;
    dmem[8845] = 32'd0;
    dmem[8846] = 32'd0;
    dmem[8847] = 32'd0;
    dmem[8848] = 32'd0;
    dmem[8849] = 32'd0;
    dmem[8850] = 32'd0;
    dmem[8851] = 32'd0;
    dmem[8852] = 32'd0;
    dmem[8853] = 32'd0;
    dmem[8854] = 32'd0;
    dmem[8855] = 32'd0;
    dmem[8856] = 32'd0;
    dmem[8857] = 32'd0;
    dmem[8858] = 32'd0;
    dmem[8859] = 32'd0;
    dmem[8860] = 32'd0;
    dmem[8861] = 32'd0;
    dmem[8862] = 32'd0;
    dmem[8863] = 32'd0;
    dmem[8864] = 32'd0;
    dmem[8865] = 32'd0;
    dmem[8866] = 32'd0;
    dmem[8867] = 32'd0;
    dmem[8868] = 32'd0;
    dmem[8869] = 32'd0;
    dmem[8870] = 32'd0;
    dmem[8871] = 32'd0;
    dmem[8872] = 32'd0;
    dmem[8873] = 32'd0;
    dmem[8874] = 32'd0;
    dmem[8875] = 32'd0;
    dmem[8876] = 32'd0;
    dmem[8877] = 32'd0;
    dmem[8878] = 32'd0;
    dmem[8879] = 32'd0;
    dmem[8880] = 32'd0;
    dmem[8881] = 32'd0;
    dmem[8882] = 32'd0;
    dmem[8883] = 32'd0;
    dmem[8884] = 32'd0;
    dmem[8885] = 32'd0;
    dmem[8886] = 32'd0;
    dmem[8887] = 32'd0;
    dmem[8888] = 32'd0;
    dmem[8889] = 32'd0;
    dmem[8890] = 32'd0;
    dmem[8891] = 32'd0;
    dmem[8892] = 32'd0;
    dmem[8893] = 32'd0;
    dmem[8894] = 32'd0;
    dmem[8895] = 32'd0;
    dmem[8896] = 32'd0;
    dmem[8897] = 32'd0;
    dmem[8898] = 32'd0;
    dmem[8899] = 32'd0;
    dmem[8900] = 32'd0;
    dmem[8901] = 32'd0;
    dmem[8902] = 32'd0;
    dmem[8903] = 32'd0;
    dmem[8904] = 32'd0;
    dmem[8905] = 32'd0;
    dmem[8906] = 32'd0;
    dmem[8907] = 32'd0;
    dmem[8908] = 32'd0;
    dmem[8909] = 32'd0;
    dmem[8910] = 32'd0;
    dmem[8911] = 32'd0;
    dmem[8912] = 32'd0;
    dmem[8913] = 32'd0;
    dmem[8914] = 32'd0;
    dmem[8915] = 32'd0;
    dmem[8916] = 32'd0;
    dmem[8917] = 32'd0;
    dmem[8918] = 32'd0;
    dmem[8919] = 32'd0;
    dmem[8920] = 32'd0;
    dmem[8921] = 32'd0;
    dmem[8922] = 32'd0;
    dmem[8923] = 32'd0;
    dmem[8924] = 32'd0;
    dmem[8925] = 32'd0;
    dmem[8926] = 32'd0;
    dmem[8927] = 32'd0;
    dmem[8928] = 32'd0;
    dmem[8929] = 32'd0;
    dmem[8930] = 32'd0;
    dmem[8931] = 32'd0;
    dmem[8932] = 32'd0;
    dmem[8933] = 32'd0;
    dmem[8934] = 32'd0;
    dmem[8935] = 32'd0;
    dmem[8936] = 32'd0;
    dmem[8937] = 32'd0;
    dmem[8938] = 32'd0;
    dmem[8939] = 32'd0;
    dmem[8940] = 32'd0;
    dmem[8941] = 32'd0;
    dmem[8942] = 32'd0;
    dmem[8943] = 32'd0;
    dmem[8944] = 32'd0;
    dmem[8945] = 32'd0;
    dmem[8946] = 32'd0;
    dmem[8947] = 32'd0;
    dmem[8948] = 32'd0;
    dmem[8949] = 32'd0;
    dmem[8950] = 32'd0;
    dmem[8951] = 32'd0;
    dmem[8952] = 32'd0;
    dmem[8953] = 32'd0;
    dmem[8954] = 32'd0;
    dmem[8955] = 32'd0;
    dmem[8956] = 32'd0;
    dmem[8957] = 32'd0;
    dmem[8958] = 32'd0;
    dmem[8959] = 32'd0;
    dmem[8960] = 32'd0;
    dmem[8961] = 32'd0;
    dmem[8962] = 32'd0;
    dmem[8963] = 32'd0;
    dmem[8964] = 32'd0;
    dmem[8965] = 32'd0;
    dmem[8966] = 32'd0;
    dmem[8967] = 32'd0;
    dmem[8968] = 32'd0;
    dmem[8969] = 32'd0;
    dmem[8970] = 32'd0;
    dmem[8971] = 32'd0;
    dmem[8972] = 32'd0;
    dmem[8973] = 32'd0;
    dmem[8974] = 32'd0;
    dmem[8975] = 32'd0;
    dmem[8976] = 32'd0;
    dmem[8977] = 32'd0;
    dmem[8978] = 32'd0;
    dmem[8979] = 32'd0;
    dmem[8980] = 32'd0;
    dmem[8981] = 32'd0;
    dmem[8982] = 32'd0;
    dmem[8983] = 32'd0;
    dmem[8984] = 32'd0;
    dmem[8985] = 32'd0;
    dmem[8986] = 32'd0;
    dmem[8987] = 32'd0;
    dmem[8988] = 32'd0;
    dmem[8989] = 32'd0;
    dmem[8990] = 32'd0;
    dmem[8991] = 32'd0;
    dmem[8992] = 32'd0;
    dmem[8993] = 32'd0;
    dmem[8994] = 32'd0;
    dmem[8995] = 32'd0;
    dmem[8996] = 32'd0;
    dmem[8997] = 32'd0;
    dmem[8998] = 32'd0;
    dmem[8999] = 32'd0;
    dmem[9000] = 32'd0;
    dmem[9001] = 32'd0;
    dmem[9002] = 32'd0;
    dmem[9003] = 32'd0;
    dmem[9004] = 32'd0;
    dmem[9005] = 32'd0;
    dmem[9006] = 32'd0;
    dmem[9007] = 32'd0;
    dmem[9008] = 32'd0;
    dmem[9009] = 32'd0;
    dmem[9010] = 32'd0;
    dmem[9011] = 32'd0;
    dmem[9012] = 32'd0;
    dmem[9013] = 32'd0;
    dmem[9014] = 32'd0;
    dmem[9015] = 32'd0;
    dmem[9016] = 32'd0;
    dmem[9017] = 32'd0;
    dmem[9018] = 32'd0;
    dmem[9019] = 32'd0;
    dmem[9020] = 32'd0;
    dmem[9021] = 32'd0;
    dmem[9022] = 32'd0;
    dmem[9023] = 32'd0;
    dmem[9024] = 32'd0;
    dmem[9025] = 32'd0;
    dmem[9026] = 32'd0;
    dmem[9027] = 32'd0;
    dmem[9028] = 32'd0;
    dmem[9029] = 32'd0;
    dmem[9030] = 32'd0;
    dmem[9031] = 32'd0;
    dmem[9032] = 32'd0;
    dmem[9033] = 32'd0;
    dmem[9034] = 32'd0;
    dmem[9035] = 32'd0;
    dmem[9036] = 32'd0;
    dmem[9037] = 32'd0;
    dmem[9038] = 32'd0;
    dmem[9039] = 32'd0;
    dmem[9040] = 32'd0;
    dmem[9041] = 32'd0;
    dmem[9042] = 32'd0;
    dmem[9043] = 32'd0;
    dmem[9044] = 32'd0;
    dmem[9045] = 32'd0;
    dmem[9046] = 32'd0;
    dmem[9047] = 32'd0;
    dmem[9048] = 32'd0;
    dmem[9049] = 32'd0;
    dmem[9050] = 32'd0;
    dmem[9051] = 32'd0;
    dmem[9052] = 32'd0;
    dmem[9053] = 32'd0;
    dmem[9054] = 32'd0;
    dmem[9055] = 32'd0;
    dmem[9056] = 32'd0;
    dmem[9057] = 32'd0;
    dmem[9058] = 32'd0;
    dmem[9059] = 32'd0;
    dmem[9060] = 32'd0;
    dmem[9061] = 32'd0;
    dmem[9062] = 32'd0;
    dmem[9063] = 32'd0;
    dmem[9064] = 32'd0;
    dmem[9065] = 32'd0;
    dmem[9066] = 32'd0;
    dmem[9067] = 32'd0;
    dmem[9068] = 32'd0;
    dmem[9069] = 32'd0;
    dmem[9070] = 32'd0;
    dmem[9071] = 32'd0;
    dmem[9072] = 32'd0;
    dmem[9073] = 32'd0;
    dmem[9074] = 32'd0;
    dmem[9075] = 32'd0;
    dmem[9076] = 32'd0;
    dmem[9077] = 32'd0;
    dmem[9078] = 32'd0;
    dmem[9079] = 32'd0;
    dmem[9080] = 32'd0;
    dmem[9081] = 32'd0;
    dmem[9082] = 32'd0;
    dmem[9083] = 32'd0;
    dmem[9084] = 32'd0;
    dmem[9085] = 32'd0;
    dmem[9086] = 32'd0;
    dmem[9087] = 32'd0;
    dmem[9088] = 32'd0;
    dmem[9089] = 32'd0;
    dmem[9090] = 32'd0;
    dmem[9091] = 32'd0;
    dmem[9092] = 32'd0;
    dmem[9093] = 32'd0;
    dmem[9094] = 32'd0;
    dmem[9095] = 32'd0;
    dmem[9096] = 32'd0;
    dmem[9097] = 32'd0;
    dmem[9098] = 32'd0;
    dmem[9099] = 32'd0;
    dmem[9100] = 32'd0;
    dmem[9101] = 32'd0;
    dmem[9102] = 32'd0;
    dmem[9103] = 32'd0;
    dmem[9104] = 32'd0;
    dmem[9105] = 32'd0;
    dmem[9106] = 32'd0;
    dmem[9107] = 32'd0;
    dmem[9108] = 32'd0;
    dmem[9109] = 32'd0;
    dmem[9110] = 32'd0;
    dmem[9111] = 32'd0;
    dmem[9112] = 32'd0;
    dmem[9113] = 32'd0;
    dmem[9114] = 32'd0;
    dmem[9115] = 32'd0;
    dmem[9116] = 32'd0;
    dmem[9117] = 32'd0;
    dmem[9118] = 32'd0;
    dmem[9119] = 32'd0;
    dmem[9120] = 32'd0;
    dmem[9121] = 32'd0;
    dmem[9122] = 32'd0;
    dmem[9123] = 32'd0;
    dmem[9124] = 32'd0;
    dmem[9125] = 32'd0;
    dmem[9126] = 32'd0;
    dmem[9127] = 32'd0;
    dmem[9128] = 32'd0;
    dmem[9129] = 32'd0;
    dmem[9130] = 32'd0;
    dmem[9131] = 32'd0;
    dmem[9132] = 32'd0;
    dmem[9133] = 32'd0;
    dmem[9134] = 32'd0;
    dmem[9135] = 32'd0;
    dmem[9136] = 32'd0;
    dmem[9137] = 32'd0;
    dmem[9138] = 32'd0;
    dmem[9139] = 32'd0;
    dmem[9140] = 32'd0;
    dmem[9141] = 32'd0;
    dmem[9142] = 32'd0;
    dmem[9143] = 32'd0;
    dmem[9144] = 32'd0;
    dmem[9145] = 32'd0;
    dmem[9146] = 32'd0;
    dmem[9147] = 32'd0;
    dmem[9148] = 32'd0;
    dmem[9149] = 32'd0;
    dmem[9150] = 32'd0;
    dmem[9151] = 32'd0;
    dmem[9152] = 32'd0;
    dmem[9153] = 32'd0;
    dmem[9154] = 32'd0;
    dmem[9155] = 32'd0;
    dmem[9156] = 32'd0;
    dmem[9157] = 32'd0;
    dmem[9158] = 32'd0;
    dmem[9159] = 32'd0;
    dmem[9160] = 32'd0;
    dmem[9161] = 32'd0;
    dmem[9162] = 32'd0;
    dmem[9163] = 32'd0;
    dmem[9164] = 32'd0;
    dmem[9165] = 32'd0;
    dmem[9166] = 32'd0;
    dmem[9167] = 32'd0;
    dmem[9168] = 32'd0;
    dmem[9169] = 32'd0;
    dmem[9170] = 32'd0;
    dmem[9171] = 32'd0;
    dmem[9172] = 32'd0;
    dmem[9173] = 32'd0;
    dmem[9174] = 32'd0;
    dmem[9175] = 32'd0;
    dmem[9176] = 32'd0;
    dmem[9177] = 32'd0;
    dmem[9178] = 32'd0;
    dmem[9179] = 32'd0;
    dmem[9180] = 32'd0;
    dmem[9181] = 32'd0;
    dmem[9182] = 32'd0;
    dmem[9183] = 32'd0;
    dmem[9184] = 32'd0;
    dmem[9185] = 32'd0;
    dmem[9186] = 32'd0;
    dmem[9187] = 32'd0;
    dmem[9188] = 32'd0;
    dmem[9189] = 32'd0;
    dmem[9190] = 32'd0;
    dmem[9191] = 32'd0;
    dmem[9192] = 32'd0;
    dmem[9193] = 32'd0;
    dmem[9194] = 32'd0;
    dmem[9195] = 32'd0;
    dmem[9196] = 32'd0;
    dmem[9197] = 32'd0;
    dmem[9198] = 32'd0;
    dmem[9199] = 32'd0;
    dmem[9200] = 32'd0;
    dmem[9201] = 32'd0;
    dmem[9202] = 32'd0;
    dmem[9203] = 32'd0;
    dmem[9204] = 32'd0;
    dmem[9205] = 32'd0;
    dmem[9206] = 32'd0;
    dmem[9207] = 32'd0;
    dmem[9208] = 32'd0;
    dmem[9209] = 32'd0;
    dmem[9210] = 32'd0;
    dmem[9211] = 32'd0;
    dmem[9212] = 32'd0;
    dmem[9213] = 32'd0;
    dmem[9214] = 32'd0;
    dmem[9215] = 32'd0;
    dmem[9216] = 32'd0;
    dmem[9217] = 32'd0;
    dmem[9218] = 32'd0;
    dmem[9219] = 32'd0;
    dmem[9220] = 32'd0;
    dmem[9221] = 32'd0;
    dmem[9222] = 32'd0;
    dmem[9223] = 32'd0;
    dmem[9224] = 32'd0;
    dmem[9225] = 32'd0;
    dmem[9226] = 32'd0;
    dmem[9227] = 32'd0;
    dmem[9228] = 32'd0;
    dmem[9229] = 32'd0;
    dmem[9230] = 32'd0;
    dmem[9231] = 32'd0;
    dmem[9232] = 32'd0;
    dmem[9233] = 32'd0;
    dmem[9234] = 32'd0;
    dmem[9235] = 32'd0;
    dmem[9236] = 32'd0;
    dmem[9237] = 32'd0;
    dmem[9238] = 32'd0;
    dmem[9239] = 32'd0;
    dmem[9240] = 32'd0;
    dmem[9241] = 32'd0;
    dmem[9242] = 32'd0;
    dmem[9243] = 32'd0;
    dmem[9244] = 32'd0;
    dmem[9245] = 32'd0;
    dmem[9246] = 32'd0;
    dmem[9247] = 32'd0;
    dmem[9248] = 32'd0;
    dmem[9249] = 32'd0;
    dmem[9250] = 32'd0;
    dmem[9251] = 32'd0;
    dmem[9252] = 32'd0;
    dmem[9253] = 32'd0;
    dmem[9254] = 32'd0;
    dmem[9255] = 32'd0;
    dmem[9256] = 32'd0;
    dmem[9257] = 32'd0;
    dmem[9258] = 32'd0;
    dmem[9259] = 32'd0;
    dmem[9260] = 32'd0;
    dmem[9261] = 32'd0;
    dmem[9262] = 32'd0;
    dmem[9263] = 32'd0;
    dmem[9264] = 32'd0;
    dmem[9265] = 32'd0;
    dmem[9266] = 32'd0;
    dmem[9267] = 32'd0;
    dmem[9268] = 32'd0;
    dmem[9269] = 32'd0;
    dmem[9270] = 32'd0;
    dmem[9271] = 32'd0;
    dmem[9272] = 32'd0;
    dmem[9273] = 32'd0;
    dmem[9274] = 32'd0;
    dmem[9275] = 32'd0;
    dmem[9276] = 32'd0;
    dmem[9277] = 32'd0;
    dmem[9278] = 32'd0;
    dmem[9279] = 32'd0;
    dmem[9280] = 32'd0;
    dmem[9281] = 32'd0;
    dmem[9282] = 32'd0;
    dmem[9283] = 32'd0;
    dmem[9284] = 32'd0;
    dmem[9285] = 32'd0;
    dmem[9286] = 32'd0;
    dmem[9287] = 32'd0;
    dmem[9288] = 32'd0;
    dmem[9289] = 32'd0;
    dmem[9290] = 32'd0;
    dmem[9291] = 32'd0;
    dmem[9292] = 32'd0;
    dmem[9293] = 32'd0;
    dmem[9294] = 32'd0;
    dmem[9295] = 32'd0;
    dmem[9296] = 32'd0;
    dmem[9297] = 32'd0;
    dmem[9298] = 32'd0;
    dmem[9299] = 32'd0;
    dmem[9300] = 32'd0;
    dmem[9301] = 32'd0;
    dmem[9302] = 32'd0;
    dmem[9303] = 32'd0;
    dmem[9304] = 32'd0;
    dmem[9305] = 32'd0;
    dmem[9306] = 32'd0;
    dmem[9307] = 32'd0;
    dmem[9308] = 32'd0;
    dmem[9309] = 32'd0;
    dmem[9310] = 32'd0;
    dmem[9311] = 32'd0;
    dmem[9312] = 32'd0;
    dmem[9313] = 32'd0;
    dmem[9314] = 32'd0;
    dmem[9315] = 32'd0;
    dmem[9316] = 32'd0;
    dmem[9317] = 32'd0;
    dmem[9318] = 32'd0;
    dmem[9319] = 32'd0;
    dmem[9320] = 32'd0;
    dmem[9321] = 32'd0;
    dmem[9322] = 32'd0;
    dmem[9323] = 32'd0;
    dmem[9324] = 32'd0;
    dmem[9325] = 32'd0;
    dmem[9326] = 32'd0;
    dmem[9327] = 32'd0;
    dmem[9328] = 32'd0;
    dmem[9329] = 32'd0;
    dmem[9330] = 32'd0;
    dmem[9331] = 32'd0;
    dmem[9332] = 32'd0;
    dmem[9333] = 32'd0;
    dmem[9334] = 32'd0;
    dmem[9335] = 32'd0;
    dmem[9336] = 32'd0;
    dmem[9337] = 32'd0;
    dmem[9338] = 32'd0;
    dmem[9339] = 32'd0;
    dmem[9340] = 32'd0;
    dmem[9341] = 32'd0;
    dmem[9342] = 32'd0;
    dmem[9343] = 32'd0;
    dmem[9344] = 32'd0;
    dmem[9345] = 32'd0;
    dmem[9346] = 32'd0;
    dmem[9347] = 32'd0;
    dmem[9348] = 32'd0;
    dmem[9349] = 32'd0;
    dmem[9350] = 32'd0;
    dmem[9351] = 32'd0;
    dmem[9352] = 32'd0;
    dmem[9353] = 32'd0;
    dmem[9354] = 32'd0;
    dmem[9355] = 32'd0;
    dmem[9356] = 32'd0;
    dmem[9357] = 32'd0;
    dmem[9358] = 32'd0;
    dmem[9359] = 32'd0;
    dmem[9360] = 32'd0;
    dmem[9361] = 32'd0;
    dmem[9362] = 32'd0;
    dmem[9363] = 32'd0;
    dmem[9364] = 32'd0;
    dmem[9365] = 32'd0;
    dmem[9366] = 32'd0;
    dmem[9367] = 32'd0;
    dmem[9368] = 32'd0;
    dmem[9369] = 32'd0;
    dmem[9370] = 32'd0;
    dmem[9371] = 32'd0;
    dmem[9372] = 32'd0;
    dmem[9373] = 32'd0;
    dmem[9374] = 32'd0;
    dmem[9375] = 32'd0;
    dmem[9376] = 32'd0;
    dmem[9377] = 32'd0;
    dmem[9378] = 32'd0;
    dmem[9379] = 32'd0;
    dmem[9380] = 32'd0;
    dmem[9381] = 32'd0;
    dmem[9382] = 32'd0;
    dmem[9383] = 32'd0;
    dmem[9384] = 32'd0;
    dmem[9385] = 32'd0;
    dmem[9386] = 32'd0;
    dmem[9387] = 32'd0;
    dmem[9388] = 32'd0;
    dmem[9389] = 32'd0;
    dmem[9390] = 32'd0;
    dmem[9391] = 32'd0;
    dmem[9392] = 32'd0;
    dmem[9393] = 32'd0;
    dmem[9394] = 32'd0;
    dmem[9395] = 32'd0;
    dmem[9396] = 32'd0;
    dmem[9397] = 32'd0;
    dmem[9398] = 32'd0;
    dmem[9399] = 32'd0;
    dmem[9400] = 32'd0;
    dmem[9401] = 32'd0;
    dmem[9402] = 32'd0;
    dmem[9403] = 32'd0;
    dmem[9404] = 32'd0;
    dmem[9405] = 32'd0;
    dmem[9406] = 32'd0;
    dmem[9407] = 32'd0;
    dmem[9408] = 32'd0;
    dmem[9409] = 32'd0;
    dmem[9410] = 32'd0;
    dmem[9411] = 32'd0;
    dmem[9412] = 32'd0;
    dmem[9413] = 32'd0;
    dmem[9414] = 32'd0;
    dmem[9415] = 32'd0;
    dmem[9416] = 32'd0;
    dmem[9417] = 32'd0;
    dmem[9418] = 32'd0;
    dmem[9419] = 32'd0;
    dmem[9420] = 32'd0;
    dmem[9421] = 32'd0;
    dmem[9422] = 32'd0;
    dmem[9423] = 32'd0;
    dmem[9424] = 32'd0;
    dmem[9425] = 32'd0;
    dmem[9426] = 32'd0;
    dmem[9427] = 32'd0;
    dmem[9428] = 32'd0;
    dmem[9429] = 32'd0;
    dmem[9430] = 32'd0;
    dmem[9431] = 32'd0;
    dmem[9432] = 32'd0;
    dmem[9433] = 32'd0;
    dmem[9434] = 32'd0;
    dmem[9435] = 32'd0;
    dmem[9436] = 32'd0;
    dmem[9437] = 32'd0;
    dmem[9438] = 32'd0;
    dmem[9439] = 32'd0;
    dmem[9440] = 32'd0;
    dmem[9441] = 32'd0;
    dmem[9442] = 32'd0;
    dmem[9443] = 32'd0;
    dmem[9444] = 32'd0;
    dmem[9445] = 32'd0;
    dmem[9446] = 32'd0;
    dmem[9447] = 32'd0;
    dmem[9448] = 32'd0;
    dmem[9449] = 32'd0;
    dmem[9450] = 32'd0;
    dmem[9451] = 32'd0;
    dmem[9452] = 32'd0;
    dmem[9453] = 32'd0;
    dmem[9454] = 32'd0;
    dmem[9455] = 32'd0;
    dmem[9456] = 32'd0;
    dmem[9457] = 32'd0;
    dmem[9458] = 32'd0;
    dmem[9459] = 32'd0;
    dmem[9460] = 32'd0;
    dmem[9461] = 32'd0;
    dmem[9462] = 32'd0;
    dmem[9463] = 32'd0;
    dmem[9464] = 32'd0;
    dmem[9465] = 32'd0;
    dmem[9466] = 32'd0;
    dmem[9467] = 32'd0;
    dmem[9468] = 32'd0;
    dmem[9469] = 32'd0;
    dmem[9470] = 32'd0;
    dmem[9471] = 32'd0;
    dmem[9472] = 32'd0;
    dmem[9473] = 32'd0;
    dmem[9474] = 32'd0;
    dmem[9475] = 32'd0;
    dmem[9476] = 32'd0;
    dmem[9477] = 32'd0;
    dmem[9478] = 32'd0;
    dmem[9479] = 32'd0;
    dmem[9480] = 32'd0;
    dmem[9481] = 32'd0;
    dmem[9482] = 32'd0;
    dmem[9483] = 32'd0;
    dmem[9484] = 32'd0;
    dmem[9485] = 32'd0;
    dmem[9486] = 32'd0;
    dmem[9487] = 32'd0;
    dmem[9488] = 32'd0;
    dmem[9489] = 32'd0;
    dmem[9490] = 32'd0;
    dmem[9491] = 32'd0;
    dmem[9492] = 32'd0;
    dmem[9493] = 32'd0;
    dmem[9494] = 32'd0;
    dmem[9495] = 32'd0;
    dmem[9496] = 32'd0;
    dmem[9497] = 32'd0;
    dmem[9498] = 32'd0;
    dmem[9499] = 32'd0;
    dmem[9500] = 32'd0;
    dmem[9501] = 32'd0;
    dmem[9502] = 32'd0;
    dmem[9503] = 32'd0;
    dmem[9504] = 32'd0;
    dmem[9505] = 32'd0;
    dmem[9506] = 32'd0;
    dmem[9507] = 32'd0;
    dmem[9508] = 32'd0;
    dmem[9509] = 32'd0;
    dmem[9510] = 32'd0;
    dmem[9511] = 32'd0;
    dmem[9512] = 32'd0;
    dmem[9513] = 32'd0;
    dmem[9514] = 32'd0;
    dmem[9515] = 32'd0;
    dmem[9516] = 32'd0;
    dmem[9517] = 32'd0;
    dmem[9518] = 32'd0;
    dmem[9519] = 32'd0;
    dmem[9520] = 32'd0;
    dmem[9521] = 32'd0;
    dmem[9522] = 32'd0;
    dmem[9523] = 32'd0;
    dmem[9524] = 32'd0;
    dmem[9525] = 32'd0;
    dmem[9526] = 32'd0;
    dmem[9527] = 32'd0;
    dmem[9528] = 32'd0;
    dmem[9529] = 32'd0;
    dmem[9530] = 32'd0;
    dmem[9531] = 32'd0;
    dmem[9532] = 32'd0;
    dmem[9533] = 32'd0;
    dmem[9534] = 32'd0;
    dmem[9535] = 32'd0;
    dmem[9536] = 32'd0;
    dmem[9537] = 32'd0;
    dmem[9538] = 32'd0;
    dmem[9539] = 32'd0;
    dmem[9540] = 32'd0;
    dmem[9541] = 32'd0;
    dmem[9542] = 32'd0;
    dmem[9543] = 32'd0;
    dmem[9544] = 32'd0;
    dmem[9545] = 32'd0;
    dmem[9546] = 32'd0;
    dmem[9547] = 32'd0;
    dmem[9548] = 32'd0;
    dmem[9549] = 32'd0;
    dmem[9550] = 32'd0;
    dmem[9551] = 32'd0;
    dmem[9552] = 32'd0;
    dmem[9553] = 32'd0;
    dmem[9554] = 32'd0;
    dmem[9555] = 32'd0;
    dmem[9556] = 32'd0;
    dmem[9557] = 32'd0;
    dmem[9558] = 32'd0;
    dmem[9559] = 32'd0;
    dmem[9560] = 32'd0;
    dmem[9561] = 32'd0;
    dmem[9562] = 32'd0;
    dmem[9563] = 32'd0;
    dmem[9564] = 32'd0;
    dmem[9565] = 32'd0;
    dmem[9566] = 32'd0;
    dmem[9567] = 32'd0;
    dmem[9568] = 32'd0;
    dmem[9569] = 32'd0;
    dmem[9570] = 32'd0;
    dmem[9571] = 32'd0;
    dmem[9572] = 32'd0;
    dmem[9573] = 32'd0;
    dmem[9574] = 32'd0;
    dmem[9575] = 32'd0;
    dmem[9576] = 32'd0;
    dmem[9577] = 32'd0;
    dmem[9578] = 32'd0;
    dmem[9579] = 32'd0;
    dmem[9580] = 32'd0;
    dmem[9581] = 32'd0;
    dmem[9582] = 32'd0;
    dmem[9583] = 32'd0;
    dmem[9584] = 32'd0;
    dmem[9585] = 32'd0;
    dmem[9586] = 32'd0;
    dmem[9587] = 32'd0;
    dmem[9588] = 32'd0;
    dmem[9589] = 32'd0;
    dmem[9590] = 32'd0;
    dmem[9591] = 32'd0;
    dmem[9592] = 32'd0;
    dmem[9593] = 32'd0;
    dmem[9594] = 32'd0;
    dmem[9595] = 32'd0;
    dmem[9596] = 32'd0;
    dmem[9597] = 32'd0;
    dmem[9598] = 32'd0;
    dmem[9599] = 32'd0;
    dmem[9600] = 32'd0;
    dmem[9601] = 32'd0;
    dmem[9602] = 32'd0;
    dmem[9603] = 32'd0;
    dmem[9604] = 32'd0;
    dmem[9605] = 32'd0;
    dmem[9606] = 32'd0;
    dmem[9607] = 32'd0;
    dmem[9608] = 32'd0;
    dmem[9609] = 32'd0;
    dmem[9610] = 32'd0;
    dmem[9611] = 32'd0;
    dmem[9612] = 32'd0;
    dmem[9613] = 32'd0;
    dmem[9614] = 32'd0;
    dmem[9615] = 32'd0;
    dmem[9616] = 32'd0;
    dmem[9617] = 32'd0;
    dmem[9618] = 32'd0;
    dmem[9619] = 32'd0;
    dmem[9620] = 32'd0;
    dmem[9621] = 32'd0;
    dmem[9622] = 32'd0;
    dmem[9623] = 32'd0;
    dmem[9624] = 32'd0;
    dmem[9625] = 32'd0;
    dmem[9626] = 32'd0;
    dmem[9627] = 32'd0;
    dmem[9628] = 32'd0;
    dmem[9629] = 32'd0;
    dmem[9630] = 32'd0;
    dmem[9631] = 32'd0;
    dmem[9632] = 32'd0;
    dmem[9633] = 32'd0;
    dmem[9634] = 32'd0;
    dmem[9635] = 32'd0;
    dmem[9636] = 32'd0;
    dmem[9637] = 32'd0;
    dmem[9638] = 32'd0;
    dmem[9639] = 32'd0;
    dmem[9640] = 32'd0;
    dmem[9641] = 32'd0;
    dmem[9642] = 32'd0;
    dmem[9643] = 32'd0;
    dmem[9644] = 32'd0;
    dmem[9645] = 32'd0;
    dmem[9646] = 32'd0;
    dmem[9647] = 32'd0;
    dmem[9648] = 32'd0;
    dmem[9649] = 32'd0;
    dmem[9650] = 32'd0;
    dmem[9651] = 32'd0;
    dmem[9652] = 32'd0;
    dmem[9653] = 32'd0;
    dmem[9654] = 32'd0;
    dmem[9655] = 32'd0;
    dmem[9656] = 32'd0;
    dmem[9657] = 32'd0;
    dmem[9658] = 32'd0;
    dmem[9659] = 32'd0;
    dmem[9660] = 32'd0;
    dmem[9661] = 32'd0;
    dmem[9662] = 32'd0;
    dmem[9663] = 32'd0;
    dmem[9664] = 32'd0;
    dmem[9665] = 32'd0;
    dmem[9666] = 32'd0;
    dmem[9667] = 32'd0;
    dmem[9668] = 32'd0;
    dmem[9669] = 32'd0;
    dmem[9670] = 32'd0;
    dmem[9671] = 32'd0;
    dmem[9672] = 32'd0;
    dmem[9673] = 32'd0;
    dmem[9674] = 32'd0;
    dmem[9675] = 32'd0;
    dmem[9676] = 32'd0;
    dmem[9677] = 32'd0;
    dmem[9678] = 32'd0;
    dmem[9679] = 32'd0;
    dmem[9680] = 32'd0;
    dmem[9681] = 32'd0;
    dmem[9682] = 32'd0;
    dmem[9683] = 32'd0;
    dmem[9684] = 32'd0;
    dmem[9685] = 32'd0;
    dmem[9686] = 32'd0;
    dmem[9687] = 32'd0;
    dmem[9688] = 32'd0;
    dmem[9689] = 32'd0;
    dmem[9690] = 32'd0;
    dmem[9691] = 32'd0;
    dmem[9692] = 32'd0;
    dmem[9693] = 32'd0;
    dmem[9694] = 32'd0;
    dmem[9695] = 32'd0;
    dmem[9696] = 32'd0;
    dmem[9697] = 32'd0;
    dmem[9698] = 32'd0;
    dmem[9699] = 32'd0;
    dmem[9700] = 32'd0;
    dmem[9701] = 32'd0;
    dmem[9702] = 32'd0;
    dmem[9703] = 32'd0;
    dmem[9704] = 32'd0;
    dmem[9705] = 32'd0;
    dmem[9706] = 32'd0;
    dmem[9707] = 32'd0;
    dmem[9708] = 32'd0;
    dmem[9709] = 32'd0;
    dmem[9710] = 32'd0;
    dmem[9711] = 32'd0;
    dmem[9712] = 32'd0;
    dmem[9713] = 32'd0;
    dmem[9714] = 32'd0;
    dmem[9715] = 32'd0;
    dmem[9716] = 32'd0;
    dmem[9717] = 32'd0;
    dmem[9718] = 32'd0;
    dmem[9719] = 32'd0;
    dmem[9720] = 32'd0;
    dmem[9721] = 32'd0;
    dmem[9722] = 32'd0;
    dmem[9723] = 32'd0;
    dmem[9724] = 32'd0;
    dmem[9725] = 32'd0;
    dmem[9726] = 32'd0;
    dmem[9727] = 32'd0;
    dmem[9728] = 32'd0;
    dmem[9729] = 32'd0;
    dmem[9730] = 32'd0;
    dmem[9731] = 32'd0;
    dmem[9732] = 32'd0;
    dmem[9733] = 32'd0;
    dmem[9734] = 32'd0;
    dmem[9735] = 32'd0;
    dmem[9736] = 32'd0;
    dmem[9737] = 32'd0;
    dmem[9738] = 32'd0;
    dmem[9739] = 32'd0;
    dmem[9740] = 32'd0;
    dmem[9741] = 32'd0;
    dmem[9742] = 32'd0;
    dmem[9743] = 32'd0;
    dmem[9744] = 32'd0;
    dmem[9745] = 32'd0;
    dmem[9746] = 32'd0;
    dmem[9747] = 32'd0;
    dmem[9748] = 32'd0;
    dmem[9749] = 32'd0;
    dmem[9750] = 32'd0;
    dmem[9751] = 32'd0;
    dmem[9752] = 32'd0;
    dmem[9753] = 32'd0;
    dmem[9754] = 32'd0;
    dmem[9755] = 32'd0;
    dmem[9756] = 32'd0;
    dmem[9757] = 32'd0;
    dmem[9758] = 32'd0;
    dmem[9759] = 32'd0;
    dmem[9760] = 32'd0;
    dmem[9761] = 32'd0;
    dmem[9762] = 32'd0;
    dmem[9763] = 32'd0;
    dmem[9764] = 32'd0;
    dmem[9765] = 32'd0;
    dmem[9766] = 32'd0;
    dmem[9767] = 32'd0;
    dmem[9768] = 32'd0;
    dmem[9769] = 32'd0;
    dmem[9770] = 32'd0;
    dmem[9771] = 32'd0;
    dmem[9772] = 32'd0;
    dmem[9773] = 32'd0;
    dmem[9774] = 32'd0;
    dmem[9775] = 32'd0;
    dmem[9776] = 32'd0;
    dmem[9777] = 32'd0;
    dmem[9778] = 32'd0;
    dmem[9779] = 32'd0;
    dmem[9780] = 32'd0;
    dmem[9781] = 32'd0;
    dmem[9782] = 32'd0;
    dmem[9783] = 32'd0;
    dmem[9784] = 32'd0;
    dmem[9785] = 32'd0;
    dmem[9786] = 32'd0;
    dmem[9787] = 32'd0;
    dmem[9788] = 32'd0;
    dmem[9789] = 32'd0;
    dmem[9790] = 32'd0;
    dmem[9791] = 32'd0;
    dmem[9792] = 32'd0;
    dmem[9793] = 32'd0;
    dmem[9794] = 32'd0;
    dmem[9795] = 32'd0;
    dmem[9796] = 32'd0;
    dmem[9797] = 32'd0;
    dmem[9798] = 32'd0;
    dmem[9799] = 32'd0;
    dmem[9800] = 32'd0;
    dmem[9801] = 32'd0;
    dmem[9802] = 32'd0;
    dmem[9803] = 32'd0;
    dmem[9804] = 32'd0;
    dmem[9805] = 32'd0;
    dmem[9806] = 32'd0;
    dmem[9807] = 32'd0;
    dmem[9808] = 32'd0;
    dmem[9809] = 32'd0;
    dmem[9810] = 32'd0;
    dmem[9811] = 32'd0;
    dmem[9812] = 32'd0;
    dmem[9813] = 32'd0;
    dmem[9814] = 32'd0;
    dmem[9815] = 32'd0;
    dmem[9816] = 32'd0;
    dmem[9817] = 32'd0;
    dmem[9818] = 32'd0;
    dmem[9819] = 32'd0;
    dmem[9820] = 32'd0;
    dmem[9821] = 32'd0;
    dmem[9822] = 32'd0;
    dmem[9823] = 32'd0;
    dmem[9824] = 32'd0;
    dmem[9825] = 32'd0;
    dmem[9826] = 32'd0;
    dmem[9827] = 32'd0;
    dmem[9828] = 32'd0;
    dmem[9829] = 32'd0;
    dmem[9830] = 32'd0;
    dmem[9831] = 32'd0;
    dmem[9832] = 32'd0;
    dmem[9833] = 32'd0;
    dmem[9834] = 32'd0;
    dmem[9835] = 32'd0;
    dmem[9836] = 32'd0;
    dmem[9837] = 32'd0;
    dmem[9838] = 32'd0;
    dmem[9839] = 32'd0;
    dmem[9840] = 32'd0;
    dmem[9841] = 32'd0;
    dmem[9842] = 32'd0;
    dmem[9843] = 32'd0;
    dmem[9844] = 32'd0;
    dmem[9845] = 32'd0;
    dmem[9846] = 32'd0;
    dmem[9847] = 32'd0;
    dmem[9848] = 32'd0;
    dmem[9849] = 32'd0;
    dmem[9850] = 32'd0;
    dmem[9851] = 32'd0;
    dmem[9852] = 32'd0;
    dmem[9853] = 32'd0;
    dmem[9854] = 32'd0;
    dmem[9855] = 32'd0;
    dmem[9856] = 32'd0;
    dmem[9857] = 32'd0;
    dmem[9858] = 32'd0;
    dmem[9859] = 32'd0;
    dmem[9860] = 32'd0;
    dmem[9861] = 32'd0;
    dmem[9862] = 32'd0;
    dmem[9863] = 32'd0;
    dmem[9864] = 32'd0;
    dmem[9865] = 32'd0;
    dmem[9866] = 32'd0;
    dmem[9867] = 32'd0;
    dmem[9868] = 32'd0;
    dmem[9869] = 32'd0;
    dmem[9870] = 32'd0;
    dmem[9871] = 32'd0;
    dmem[9872] = 32'd0;
    dmem[9873] = 32'd0;
    dmem[9874] = 32'd0;
    dmem[9875] = 32'd0;
    dmem[9876] = 32'd0;
    dmem[9877] = 32'd0;
    dmem[9878] = 32'd0;
    dmem[9879] = 32'd0;
    dmem[9880] = 32'd0;
    dmem[9881] = 32'd0;
    dmem[9882] = 32'd0;
    dmem[9883] = 32'd0;
    dmem[9884] = 32'd0;
    dmem[9885] = 32'd0;
    dmem[9886] = 32'd0;
    dmem[9887] = 32'd0;
    dmem[9888] = 32'd0;
    dmem[9889] = 32'd0;
    dmem[9890] = 32'd0;
    dmem[9891] = 32'd0;
    dmem[9892] = 32'd0;
    dmem[9893] = 32'd0;
    dmem[9894] = 32'd0;
    dmem[9895] = 32'd0;
    dmem[9896] = 32'd0;
    dmem[9897] = 32'd0;
    dmem[9898] = 32'd0;
    dmem[9899] = 32'd0;
    dmem[9900] = 32'd0;
    dmem[9901] = 32'd0;
    dmem[9902] = 32'd0;
    dmem[9903] = 32'd0;
    dmem[9904] = 32'd0;
    dmem[9905] = 32'd0;
    dmem[9906] = 32'd0;
    dmem[9907] = 32'd0;
    dmem[9908] = 32'd0;
    dmem[9909] = 32'd0;
    dmem[9910] = 32'd0;
    dmem[9911] = 32'd0;
    dmem[9912] = 32'd0;
    dmem[9913] = 32'd0;
    dmem[9914] = 32'd0;
    dmem[9915] = 32'd0;
    dmem[9916] = 32'd0;
    dmem[9917] = 32'd0;
    dmem[9918] = 32'd0;
    dmem[9919] = 32'd0;
    dmem[9920] = 32'd0;
    dmem[9921] = 32'd0;
    dmem[9922] = 32'd0;
    dmem[9923] = 32'd0;
    dmem[9924] = 32'd0;
    dmem[9925] = 32'd0;
    dmem[9926] = 32'd0;
    dmem[9927] = 32'd0;
    dmem[9928] = 32'd0;
    dmem[9929] = 32'd0;
    dmem[9930] = 32'd0;
    dmem[9931] = 32'd0;
    dmem[9932] = 32'd0;
    dmem[9933] = 32'd0;
    dmem[9934] = 32'd0;
    dmem[9935] = 32'd0;
    dmem[9936] = 32'd0;
    dmem[9937] = 32'd0;
    dmem[9938] = 32'd0;
    dmem[9939] = 32'd0;
    dmem[9940] = 32'd0;
    dmem[9941] = 32'd0;
    dmem[9942] = 32'd0;
    dmem[9943] = 32'd0;
    dmem[9944] = 32'd0;
    dmem[9945] = 32'd0;
    dmem[9946] = 32'd0;
    dmem[9947] = 32'd0;
    dmem[9948] = 32'd0;
    dmem[9949] = 32'd0;
    dmem[9950] = 32'd0;
    dmem[9951] = 32'd0;
    dmem[9952] = 32'd0;
    dmem[9953] = 32'd0;
    dmem[9954] = 32'd0;
    dmem[9955] = 32'd0;
    dmem[9956] = 32'd0;
    dmem[9957] = 32'd0;
    dmem[9958] = 32'd0;
    dmem[9959] = 32'd0;
    dmem[9960] = 32'd0;
    dmem[9961] = 32'd0;
    dmem[9962] = 32'd0;
    dmem[9963] = 32'd0;
    dmem[9964] = 32'd0;
    dmem[9965] = 32'd0;
    dmem[9966] = 32'd0;
    dmem[9967] = 32'd0;
    dmem[9968] = 32'd0;
    dmem[9969] = 32'd0;
    dmem[9970] = 32'd0;
    dmem[9971] = 32'd0;
    dmem[9972] = 32'd0;
    dmem[9973] = 32'd0;
    dmem[9974] = 32'd0;
    dmem[9975] = 32'd0;
    dmem[9976] = 32'd0;
    dmem[9977] = 32'd0;
    dmem[9978] = 32'd0;
    dmem[9979] = 32'd0;
    dmem[9980] = 32'd0;
    dmem[9981] = 32'd0;
    dmem[9982] = 32'd0;
    dmem[9983] = 32'd0;
    dmem[9984] = 32'd0;
    dmem[9985] = 32'd0;
    dmem[9986] = 32'd0;
    dmem[9987] = 32'd0;
    dmem[9988] = 32'd0;
    dmem[9989] = 32'd0;
    dmem[9990] = 32'd0;
    dmem[9991] = 32'd0;
    dmem[9992] = 32'd0;
    dmem[9993] = 32'd0;
    dmem[9994] = 32'd0;
    dmem[9995] = 32'd0;
    dmem[9996] = 32'd0;
    dmem[9997] = 32'd0;
    dmem[9998] = 32'd0;
    dmem[9999] = 32'd0;
    dmem[10000] = 32'd0;
    dmem[10001] = 32'd0;
    dmem[10002] = 32'd0;
    dmem[10003] = 32'd0;
    dmem[10004] = 32'd0;
    dmem[10005] = 32'd0;
    dmem[10006] = 32'd0;
    dmem[10007] = 32'd0;
    dmem[10008] = 32'd0;
    dmem[10009] = 32'd0;
    dmem[10010] = 32'd0;
    dmem[10011] = 32'd0;
    dmem[10012] = 32'd0;
    dmem[10013] = 32'd0;
    dmem[10014] = 32'd0;
    dmem[10015] = 32'd0;
    dmem[10016] = 32'd0;
    dmem[10017] = 32'd0;
    dmem[10018] = 32'd0;
    dmem[10019] = 32'd0;
    dmem[10020] = 32'd0;
    dmem[10021] = 32'd0;
    dmem[10022] = 32'd0;
    dmem[10023] = 32'd0;
    dmem[10024] = 32'd0;
    dmem[10025] = 32'd0;
    dmem[10026] = 32'd0;
    dmem[10027] = 32'd0;
    dmem[10028] = 32'd0;
    dmem[10029] = 32'd0;
    dmem[10030] = 32'd0;
    dmem[10031] = 32'd0;
    dmem[10032] = 32'd0;
    dmem[10033] = 32'd0;
    dmem[10034] = 32'd0;
    dmem[10035] = 32'd0;
    dmem[10036] = 32'd0;
    dmem[10037] = 32'd0;
    dmem[10038] = 32'd0;
    dmem[10039] = 32'd0;
    dmem[10040] = 32'd0;
    dmem[10041] = 32'd0;
    dmem[10042] = 32'd0;
    dmem[10043] = 32'd0;
    dmem[10044] = 32'd0;
    dmem[10045] = 32'd0;
    dmem[10046] = 32'd0;
    dmem[10047] = 32'd0;
    dmem[10048] = 32'd0;
    dmem[10049] = 32'd0;
    dmem[10050] = 32'd0;
    dmem[10051] = 32'd0;
    dmem[10052] = 32'd0;
    dmem[10053] = 32'd0;
    dmem[10054] = 32'd0;
    dmem[10055] = 32'd0;
    dmem[10056] = 32'd0;
    dmem[10057] = 32'd0;
    dmem[10058] = 32'd0;
    dmem[10059] = 32'd0;
    dmem[10060] = 32'd0;
    dmem[10061] = 32'd0;
    dmem[10062] = 32'd0;
    dmem[10063] = 32'd0;
    dmem[10064] = 32'd0;
    dmem[10065] = 32'd0;
    dmem[10066] = 32'd0;
    dmem[10067] = 32'd0;
    dmem[10068] = 32'd0;
    dmem[10069] = 32'd0;
    dmem[10070] = 32'd0;
    dmem[10071] = 32'd0;
    dmem[10072] = 32'd0;
    dmem[10073] = 32'd0;
    dmem[10074] = 32'd0;
    dmem[10075] = 32'd0;
    dmem[10076] = 32'd0;
    dmem[10077] = 32'd0;
    dmem[10078] = 32'd0;
    dmem[10079] = 32'd0;
    dmem[10080] = 32'd0;
    dmem[10081] = 32'd0;
    dmem[10082] = 32'd0;
    dmem[10083] = 32'd0;
    dmem[10084] = 32'd0;
    dmem[10085] = 32'd0;
    dmem[10086] = 32'd0;
    dmem[10087] = 32'd0;
    dmem[10088] = 32'd0;
    dmem[10089] = 32'd0;
    dmem[10090] = 32'd0;
    dmem[10091] = 32'd0;
    dmem[10092] = 32'd0;
    dmem[10093] = 32'd0;
    dmem[10094] = 32'd0;
    dmem[10095] = 32'd0;
    dmem[10096] = 32'd0;
    dmem[10097] = 32'd0;
    dmem[10098] = 32'd0;
    dmem[10099] = 32'd0;
    dmem[10100] = 32'd0;
    dmem[10101] = 32'd0;
    dmem[10102] = 32'd0;
    dmem[10103] = 32'd0;
    dmem[10104] = 32'd0;
    dmem[10105] = 32'd0;
    dmem[10106] = 32'd0;
    dmem[10107] = 32'd0;
    dmem[10108] = 32'd0;
    dmem[10109] = 32'd0;
    dmem[10110] = 32'd0;
    dmem[10111] = 32'd0;
    dmem[10112] = 32'd0;
    dmem[10113] = 32'd0;
    dmem[10114] = 32'd0;
    dmem[10115] = 32'd0;
    dmem[10116] = 32'd0;
    dmem[10117] = 32'd0;
    dmem[10118] = 32'd0;
    dmem[10119] = 32'd0;
    dmem[10120] = 32'd0;
    dmem[10121] = 32'd0;
    dmem[10122] = 32'd0;
    dmem[10123] = 32'd0;
    dmem[10124] = 32'd0;
    dmem[10125] = 32'd0;
    dmem[10126] = 32'd0;
    dmem[10127] = 32'd0;
    dmem[10128] = 32'd0;
    dmem[10129] = 32'd0;
    dmem[10130] = 32'd0;
    dmem[10131] = 32'd0;
    dmem[10132] = 32'd0;
    dmem[10133] = 32'd0;
    dmem[10134] = 32'd0;
    dmem[10135] = 32'd0;
    dmem[10136] = 32'd0;
    dmem[10137] = 32'd0;
    dmem[10138] = 32'd0;
    dmem[10139] = 32'd0;
    dmem[10140] = 32'd0;
    dmem[10141] = 32'd0;
    dmem[10142] = 32'd0;
    dmem[10143] = 32'd0;
    dmem[10144] = 32'd0;
    dmem[10145] = 32'd0;
    dmem[10146] = 32'd0;
    dmem[10147] = 32'd0;
    dmem[10148] = 32'd0;
    dmem[10149] = 32'd0;
    dmem[10150] = 32'd0;
    dmem[10151] = 32'd0;
    dmem[10152] = 32'd0;
    dmem[10153] = 32'd0;
    dmem[10154] = 32'd0;
    dmem[10155] = 32'd0;
    dmem[10156] = 32'd0;
    dmem[10157] = 32'd0;
    dmem[10158] = 32'd0;
    dmem[10159] = 32'd0;
    dmem[10160] = 32'd0;
    dmem[10161] = 32'd0;
    dmem[10162] = 32'd0;
    dmem[10163] = 32'd0;
    dmem[10164] = 32'd0;
    dmem[10165] = 32'd0;
    dmem[10166] = 32'd0;
    dmem[10167] = 32'd0;
    dmem[10168] = 32'd0;
    dmem[10169] = 32'd0;
    dmem[10170] = 32'd0;
    dmem[10171] = 32'd0;
    dmem[10172] = 32'd0;
    dmem[10173] = 32'd0;
    dmem[10174] = 32'd0;
    dmem[10175] = 32'd0;
    dmem[10176] = 32'd0;
    dmem[10177] = 32'd0;
    dmem[10178] = 32'd0;
    dmem[10179] = 32'd0;
    dmem[10180] = 32'd0;
    dmem[10181] = 32'd0;
    dmem[10182] = 32'd0;
    dmem[10183] = 32'd0;
    dmem[10184] = 32'd0;
    dmem[10185] = 32'd0;
    dmem[10186] = 32'd0;
    dmem[10187] = 32'd0;
    dmem[10188] = 32'd0;
    dmem[10189] = 32'd0;
    dmem[10190] = 32'd0;
    dmem[10191] = 32'd0;
    dmem[10192] = 32'd0;
    dmem[10193] = 32'd0;
    dmem[10194] = 32'd0;
    dmem[10195] = 32'd0;
    dmem[10196] = 32'd0;
    dmem[10197] = 32'd0;
    dmem[10198] = 32'd0;
    dmem[10199] = 32'd0;
    dmem[10200] = 32'd0;
    dmem[10201] = 32'd0;
    dmem[10202] = 32'd0;
    dmem[10203] = 32'd0;
    dmem[10204] = 32'd0;
    dmem[10205] = 32'd0;
    dmem[10206] = 32'd0;
    dmem[10207] = 32'd0;
    dmem[10208] = 32'd0;
    dmem[10209] = 32'd0;
    dmem[10210] = 32'd0;
    dmem[10211] = 32'd0;
    dmem[10212] = 32'd0;
    dmem[10213] = 32'd0;
    dmem[10214] = 32'd0;
    dmem[10215] = 32'd0;
    dmem[10216] = 32'd0;
    dmem[10217] = 32'd0;
    dmem[10218] = 32'd0;
    dmem[10219] = 32'd0;
    dmem[10220] = 32'd0;
    dmem[10221] = 32'd0;
    dmem[10222] = 32'd0;
    dmem[10223] = 32'd0;
    dmem[10224] = 32'd0;
    dmem[10225] = 32'd0;
    dmem[10226] = 32'd0;
    dmem[10227] = 32'd0;
    dmem[10228] = 32'd0;
    dmem[10229] = 32'd0;
    dmem[10230] = 32'd0;
    dmem[10231] = 32'd0;
    dmem[10232] = 32'd0;
    dmem[10233] = 32'd0;
    dmem[10234] = 32'd0;
    dmem[10235] = 32'd0;
    dmem[10236] = 32'd0;
    dmem[10237] = 32'd0;
    dmem[10238] = 32'd0;
    dmem[10239] = 32'd0;
    dmem[10240] = 32'd0;
    dmem[10241] = 32'd0;
    dmem[10242] = 32'd0;
    dmem[10243] = 32'd0;
    dmem[10244] = 32'd0;
    dmem[10245] = 32'd0;
    dmem[10246] = 32'd0;
    dmem[10247] = 32'd0;
    dmem[10248] = 32'd0;
    dmem[10249] = 32'd0;
    dmem[10250] = 32'd0;
    dmem[10251] = 32'd0;
    dmem[10252] = 32'd0;
    dmem[10253] = 32'd0;
    dmem[10254] = 32'd0;
    dmem[10255] = 32'd0;
    dmem[10256] = 32'd0;
    dmem[10257] = 32'd0;
    dmem[10258] = 32'd0;
    dmem[10259] = 32'd0;
    dmem[10260] = 32'd0;
    dmem[10261] = 32'd0;
    dmem[10262] = 32'd0;
    dmem[10263] = 32'd0;
    dmem[10264] = 32'd0;
    dmem[10265] = 32'd0;
    dmem[10266] = 32'd0;
    dmem[10267] = 32'd0;
    dmem[10268] = 32'd0;
    dmem[10269] = 32'd0;
    dmem[10270] = 32'd0;
    dmem[10271] = 32'd0;
    dmem[10272] = 32'd0;
    dmem[10273] = 32'd0;
    dmem[10274] = 32'd0;
    dmem[10275] = 32'd0;
    dmem[10276] = 32'd0;
    dmem[10277] = 32'd0;
    dmem[10278] = 32'd0;
    dmem[10279] = 32'd0;
    dmem[10280] = 32'd0;
    dmem[10281] = 32'd0;
    dmem[10282] = 32'd0;
    dmem[10283] = 32'd0;
    dmem[10284] = 32'd0;
    dmem[10285] = 32'd0;
    dmem[10286] = 32'd0;
    dmem[10287] = 32'd0;
    dmem[10288] = 32'd0;
    dmem[10289] = 32'd0;
    dmem[10290] = 32'd0;
    dmem[10291] = 32'd0;
    dmem[10292] = 32'd0;
    dmem[10293] = 32'd0;
    dmem[10294] = 32'd0;
    dmem[10295] = 32'd0;
    dmem[10296] = 32'd0;
    dmem[10297] = 32'd0;
    dmem[10298] = 32'd0;
    dmem[10299] = 32'd0;
    dmem[10300] = 32'd0;
    dmem[10301] = 32'd0;
    dmem[10302] = 32'd0;
    dmem[10303] = 32'd0;
    dmem[10304] = 32'd0;
    dmem[10305] = 32'd0;
    dmem[10306] = 32'd0;
    dmem[10307] = 32'd0;
    dmem[10308] = 32'd0;
    dmem[10309] = 32'd0;
    dmem[10310] = 32'd0;
    dmem[10311] = 32'd0;
    dmem[10312] = 32'd0;
    dmem[10313] = 32'd0;
    dmem[10314] = 32'd0;
    dmem[10315] = 32'd0;
    dmem[10316] = 32'd0;
    dmem[10317] = 32'd0;
    dmem[10318] = 32'd0;
    dmem[10319] = 32'd0;
    dmem[10320] = 32'd0;
    dmem[10321] = 32'd0;
    dmem[10322] = 32'd0;
    dmem[10323] = 32'd0;
    dmem[10324] = 32'd0;
    dmem[10325] = 32'd0;
    dmem[10326] = 32'd0;
    dmem[10327] = 32'd0;
    dmem[10328] = 32'd0;
    dmem[10329] = 32'd0;
    dmem[10330] = 32'd0;
    dmem[10331] = 32'd0;
    dmem[10332] = 32'd0;
    dmem[10333] = 32'd0;
    dmem[10334] = 32'd0;
    dmem[10335] = 32'd0;
    dmem[10336] = 32'd0;
    dmem[10337] = 32'd0;
    dmem[10338] = 32'd0;
    dmem[10339] = 32'd0;
    dmem[10340] = 32'd0;
    dmem[10341] = 32'd0;
    dmem[10342] = 32'd0;
    dmem[10343] = 32'd0;
    dmem[10344] = 32'd0;
    dmem[10345] = 32'd0;
    dmem[10346] = 32'd0;
    dmem[10347] = 32'd0;
    dmem[10348] = 32'd0;
    dmem[10349] = 32'd0;
    dmem[10350] = 32'd0;
    dmem[10351] = 32'd0;
    dmem[10352] = 32'd0;
    dmem[10353] = 32'd0;
    dmem[10354] = 32'd0;
    dmem[10355] = 32'd0;
    dmem[10356] = 32'd0;
    dmem[10357] = 32'd0;
    dmem[10358] = 32'd0;
    dmem[10359] = 32'd0;
    dmem[10360] = 32'd0;
    dmem[10361] = 32'd0;
    dmem[10362] = 32'd0;
    dmem[10363] = 32'd0;
    dmem[10364] = 32'd0;
    dmem[10365] = 32'd0;
    dmem[10366] = 32'd0;
    dmem[10367] = 32'd0;
    dmem[10368] = 32'd0;
    dmem[10369] = 32'd0;
    dmem[10370] = 32'd0;
    dmem[10371] = 32'd0;
    dmem[10372] = 32'd0;
    dmem[10373] = 32'd0;
    dmem[10374] = 32'd0;
    dmem[10375] = 32'd0;
    dmem[10376] = 32'd0;
    dmem[10377] = 32'd0;
    dmem[10378] = 32'd0;
    dmem[10379] = 32'd0;
    dmem[10380] = 32'd0;
    dmem[10381] = 32'd0;
    dmem[10382] = 32'd0;
    dmem[10383] = 32'd0;
    dmem[10384] = 32'd0;
    dmem[10385] = 32'd0;
    dmem[10386] = 32'd0;
    dmem[10387] = 32'd0;
    dmem[10388] = 32'd0;
    dmem[10389] = 32'd0;
    dmem[10390] = 32'd0;
    dmem[10391] = 32'd0;
    dmem[10392] = 32'd0;
    dmem[10393] = 32'd0;
    dmem[10394] = 32'd0;
    dmem[10395] = 32'd0;
    dmem[10396] = 32'd0;
    dmem[10397] = 32'd0;
    dmem[10398] = 32'd0;
    dmem[10399] = 32'd0;
    dmem[10400] = 32'd0;
    dmem[10401] = 32'd0;
    dmem[10402] = 32'd0;
    dmem[10403] = 32'd0;
    dmem[10404] = 32'd0;
    dmem[10405] = 32'd0;
    dmem[10406] = 32'd0;
    dmem[10407] = 32'd0;
    dmem[10408] = 32'd0;
    dmem[10409] = 32'd0;
    dmem[10410] = 32'd0;
    dmem[10411] = 32'd0;
    dmem[10412] = 32'd0;
    dmem[10413] = 32'd0;
    dmem[10414] = 32'd0;
    dmem[10415] = 32'd0;
    dmem[10416] = 32'd0;
    dmem[10417] = 32'd0;
    dmem[10418] = 32'd0;
    dmem[10419] = 32'd0;
    dmem[10420] = 32'd0;
    dmem[10421] = 32'd0;
    dmem[10422] = 32'd0;
    dmem[10423] = 32'd0;
    dmem[10424] = 32'd0;
    dmem[10425] = 32'd0;
    dmem[10426] = 32'd0;
    dmem[10427] = 32'd0;
    dmem[10428] = 32'd0;
    dmem[10429] = 32'd0;
    dmem[10430] = 32'd0;
    dmem[10431] = 32'd0;
    dmem[10432] = 32'd0;
    dmem[10433] = 32'd0;
    dmem[10434] = 32'd0;
    dmem[10435] = 32'd0;
    dmem[10436] = 32'd0;
    dmem[10437] = 32'd0;
    dmem[10438] = 32'd0;
    dmem[10439] = 32'd0;
    dmem[10440] = 32'd0;
    dmem[10441] = 32'd0;
    dmem[10442] = 32'd0;
    dmem[10443] = 32'd0;
    dmem[10444] = 32'd0;
    dmem[10445] = 32'd0;
    dmem[10446] = 32'd0;
    dmem[10447] = 32'd0;
    dmem[10448] = 32'd0;
    dmem[10449] = 32'd0;
    dmem[10450] = 32'd0;
    dmem[10451] = 32'd0;
    dmem[10452] = 32'd0;
    dmem[10453] = 32'd0;
    dmem[10454] = 32'd0;
    dmem[10455] = 32'd0;
    dmem[10456] = 32'd0;
    dmem[10457] = 32'd0;
    dmem[10458] = 32'd0;
    dmem[10459] = 32'd0;
    dmem[10460] = 32'd0;
    dmem[10461] = 32'd0;
    dmem[10462] = 32'd0;
    dmem[10463] = 32'd0;
    dmem[10464] = 32'd0;
    dmem[10465] = 32'd0;
    dmem[10466] = 32'd0;
    dmem[10467] = 32'd0;
    dmem[10468] = 32'd0;
    dmem[10469] = 32'd0;
    dmem[10470] = 32'd0;
    dmem[10471] = 32'd0;
    dmem[10472] = 32'd0;
    dmem[10473] = 32'd0;
    dmem[10474] = 32'd0;
    dmem[10475] = 32'd0;
    dmem[10476] = 32'd0;
    dmem[10477] = 32'd0;
    dmem[10478] = 32'd0;
    dmem[10479] = 32'd0;
    dmem[10480] = 32'd0;
    dmem[10481] = 32'd0;
    dmem[10482] = 32'd0;
    dmem[10483] = 32'd0;
    dmem[10484] = 32'd0;
    dmem[10485] = 32'd0;
    dmem[10486] = 32'd0;
    dmem[10487] = 32'd0;
    dmem[10488] = 32'd0;
    dmem[10489] = 32'd0;
    dmem[10490] = 32'd0;
    dmem[10491] = 32'd0;
    dmem[10492] = 32'd0;
    dmem[10493] = 32'd0;
    dmem[10494] = 32'd0;
    dmem[10495] = 32'd0;
    dmem[10496] = 32'd0;
    dmem[10497] = 32'd0;
    dmem[10498] = 32'd0;
    dmem[10499] = 32'd0;
    dmem[10500] = 32'd0;
    dmem[10501] = 32'd0;
    dmem[10502] = 32'd0;
    dmem[10503] = 32'd0;
    dmem[10504] = 32'd0;
    dmem[10505] = 32'd0;
    dmem[10506] = 32'd0;
    dmem[10507] = 32'd0;
    dmem[10508] = 32'd0;
    dmem[10509] = 32'd0;
    dmem[10510] = 32'd0;
    dmem[10511] = 32'd0;
    dmem[10512] = 32'd0;
    dmem[10513] = 32'd0;
    dmem[10514] = 32'd0;
    dmem[10515] = 32'd0;
    dmem[10516] = 32'd0;
    dmem[10517] = 32'd0;
    dmem[10518] = 32'd0;
    dmem[10519] = 32'd0;
    dmem[10520] = 32'd0;
    dmem[10521] = 32'd0;
    dmem[10522] = 32'd0;
    dmem[10523] = 32'd0;
    dmem[10524] = 32'd0;
    dmem[10525] = 32'd0;
    dmem[10526] = 32'd0;
    dmem[10527] = 32'd0;
    dmem[10528] = 32'd0;
    dmem[10529] = 32'd0;
    dmem[10530] = 32'd0;
    dmem[10531] = 32'd0;
    dmem[10532] = 32'd0;
    dmem[10533] = 32'd0;
    dmem[10534] = 32'd0;
    dmem[10535] = 32'd0;
    dmem[10536] = 32'd0;
    dmem[10537] = 32'd0;
    dmem[10538] = 32'd0;
    dmem[10539] = 32'd0;
    dmem[10540] = 32'd0;
    dmem[10541] = 32'd0;
    dmem[10542] = 32'd0;
    dmem[10543] = 32'd0;
    dmem[10544] = 32'd0;
    dmem[10545] = 32'd0;
    dmem[10546] = 32'd0;
    dmem[10547] = 32'd0;
    dmem[10548] = 32'd0;
    dmem[10549] = 32'd0;
    dmem[10550] = 32'd0;
    dmem[10551] = 32'd0;
    dmem[10552] = 32'd0;
    dmem[10553] = 32'd0;
    dmem[10554] = 32'd0;
    dmem[10555] = 32'd0;
    dmem[10556] = 32'd0;
    dmem[10557] = 32'd0;
    dmem[10558] = 32'd0;
    dmem[10559] = 32'd0;
    dmem[10560] = 32'd0;
    dmem[10561] = 32'd0;
    dmem[10562] = 32'd0;
    dmem[10563] = 32'd0;
    dmem[10564] = 32'd0;
    dmem[10565] = 32'd0;
    dmem[10566] = 32'd0;
    dmem[10567] = 32'd0;
    dmem[10568] = 32'd0;
    dmem[10569] = 32'd0;
    dmem[10570] = 32'd0;
    dmem[10571] = 32'd0;
    dmem[10572] = 32'd0;
    dmem[10573] = 32'd0;
    dmem[10574] = 32'd0;
    dmem[10575] = 32'd0;
    dmem[10576] = 32'd0;
    dmem[10577] = 32'd0;
    dmem[10578] = 32'd0;
    dmem[10579] = 32'd0;
    dmem[10580] = 32'd0;
    dmem[10581] = 32'd0;
    dmem[10582] = 32'd0;
    dmem[10583] = 32'd0;
    dmem[10584] = 32'd0;
    dmem[10585] = 32'd0;
    dmem[10586] = 32'd0;
    dmem[10587] = 32'd0;
    dmem[10588] = 32'd0;
    dmem[10589] = 32'd0;
    dmem[10590] = 32'd0;
    dmem[10591] = 32'd0;
    dmem[10592] = 32'd0;
    dmem[10593] = 32'd0;
    dmem[10594] = 32'd0;
    dmem[10595] = 32'd0;
    dmem[10596] = 32'd0;
    dmem[10597] = 32'd0;
    dmem[10598] = 32'd0;
    dmem[10599] = 32'd0;
    dmem[10600] = 32'd0;
    dmem[10601] = 32'd0;
    dmem[10602] = 32'd0;
    dmem[10603] = 32'd0;
    dmem[10604] = 32'd0;
    dmem[10605] = 32'd0;
    dmem[10606] = 32'd0;
    dmem[10607] = 32'd0;
    dmem[10608] = 32'd0;
    dmem[10609] = 32'd0;
    dmem[10610] = 32'd0;
    dmem[10611] = 32'd0;
    dmem[10612] = 32'd0;
    dmem[10613] = 32'd0;
    dmem[10614] = 32'd0;
    dmem[10615] = 32'd0;
    dmem[10616] = 32'd0;
    dmem[10617] = 32'd0;
    dmem[10618] = 32'd0;
    dmem[10619] = 32'd0;
    dmem[10620] = 32'd0;
    dmem[10621] = 32'd0;
    dmem[10622] = 32'd0;
    dmem[10623] = 32'd0;
    dmem[10624] = 32'd0;
    dmem[10625] = 32'd0;
    dmem[10626] = 32'd0;
    dmem[10627] = 32'd0;
    dmem[10628] = 32'd0;
    dmem[10629] = 32'd0;
    dmem[10630] = 32'd0;
    dmem[10631] = 32'd0;
    dmem[10632] = 32'd0;
    dmem[10633] = 32'd0;
    dmem[10634] = 32'd0;
    dmem[10635] = 32'd0;
    dmem[10636] = 32'd0;
    dmem[10637] = 32'd0;
    dmem[10638] = 32'd0;
    dmem[10639] = 32'd0;
    dmem[10640] = 32'd0;
    dmem[10641] = 32'd0;
    dmem[10642] = 32'd0;
    dmem[10643] = 32'd0;
    dmem[10644] = 32'd0;
    dmem[10645] = 32'd0;
    dmem[10646] = 32'd0;
    dmem[10647] = 32'd0;
    dmem[10648] = 32'd0;
    dmem[10649] = 32'd0;
    dmem[10650] = 32'd0;
    dmem[10651] = 32'd0;
    dmem[10652] = 32'd0;
    dmem[10653] = 32'd0;
    dmem[10654] = 32'd0;
    dmem[10655] = 32'd0;
    dmem[10656] = 32'd0;
    dmem[10657] = 32'd0;
    dmem[10658] = 32'd0;
    dmem[10659] = 32'd0;
    dmem[10660] = 32'd0;
    dmem[10661] = 32'd0;
    dmem[10662] = 32'd0;
    dmem[10663] = 32'd0;
    dmem[10664] = 32'd0;
    dmem[10665] = 32'd0;
    dmem[10666] = 32'd0;
    dmem[10667] = 32'd0;
    dmem[10668] = 32'd0;
    dmem[10669] = 32'd0;
    dmem[10670] = 32'd0;
    dmem[10671] = 32'd0;
    dmem[10672] = 32'd0;
    dmem[10673] = 32'd0;
    dmem[10674] = 32'd0;
    dmem[10675] = 32'd0;
    dmem[10676] = 32'd0;
    dmem[10677] = 32'd0;
    dmem[10678] = 32'd0;
    dmem[10679] = 32'd0;
    dmem[10680] = 32'd0;
    dmem[10681] = 32'd0;
    dmem[10682] = 32'd0;
    dmem[10683] = 32'd0;
    dmem[10684] = 32'd0;
    dmem[10685] = 32'd0;
    dmem[10686] = 32'd0;
    dmem[10687] = 32'd0;
    dmem[10688] = 32'd0;
    dmem[10689] = 32'd0;
    dmem[10690] = 32'd0;
    dmem[10691] = 32'd0;
    dmem[10692] = 32'd0;
    dmem[10693] = 32'd0;
    dmem[10694] = 32'd0;
    dmem[10695] = 32'd0;
    dmem[10696] = 32'd0;
    dmem[10697] = 32'd0;
    dmem[10698] = 32'd0;
    dmem[10699] = 32'd0;
    dmem[10700] = 32'd0;
    dmem[10701] = 32'd0;
    dmem[10702] = 32'd0;
    dmem[10703] = 32'd0;
    dmem[10704] = 32'd0;
    dmem[10705] = 32'd0;
    dmem[10706] = 32'd0;
    dmem[10707] = 32'd0;
    dmem[10708] = 32'd0;
    dmem[10709] = 32'd0;
    dmem[10710] = 32'd0;
    dmem[10711] = 32'd0;
    dmem[10712] = 32'd0;
    dmem[10713] = 32'd0;
    dmem[10714] = 32'd0;
    dmem[10715] = 32'd0;
    dmem[10716] = 32'd0;
    dmem[10717] = 32'd0;
    dmem[10718] = 32'd0;
    dmem[10719] = 32'd0;
    dmem[10720] = 32'd0;
    dmem[10721] = 32'd0;
    dmem[10722] = 32'd0;
    dmem[10723] = 32'd0;
    dmem[10724] = 32'd0;
    dmem[10725] = 32'd0;
    dmem[10726] = 32'd0;
    dmem[10727] = 32'd0;
    dmem[10728] = 32'd0;
    dmem[10729] = 32'd0;
    dmem[10730] = 32'd0;
    dmem[10731] = 32'd0;
    dmem[10732] = 32'd0;
    dmem[10733] = 32'd0;
    dmem[10734] = 32'd0;
    dmem[10735] = 32'd0;
    dmem[10736] = 32'd0;
    dmem[10737] = 32'd0;
    dmem[10738] = 32'd0;
    dmem[10739] = 32'd0;
    dmem[10740] = 32'd0;
    dmem[10741] = 32'd0;
    dmem[10742] = 32'd0;
    dmem[10743] = 32'd0;
    dmem[10744] = 32'd0;
    dmem[10745] = 32'd0;
    dmem[10746] = 32'd0;
    dmem[10747] = 32'd0;
    dmem[10748] = 32'd0;
    dmem[10749] = 32'd0;
    dmem[10750] = 32'd0;
    dmem[10751] = 32'd0;
    dmem[10752] = 32'd0;
    dmem[10753] = 32'd0;
    dmem[10754] = 32'd0;
    dmem[10755] = 32'd0;
    dmem[10756] = 32'd0;
    dmem[10757] = 32'd0;
    dmem[10758] = 32'd0;
    dmem[10759] = 32'd0;
    dmem[10760] = 32'd0;
    dmem[10761] = 32'd0;
    dmem[10762] = 32'd0;
    dmem[10763] = 32'd0;
    dmem[10764] = 32'd0;
    dmem[10765] = 32'd0;
    dmem[10766] = 32'd0;
    dmem[10767] = 32'd0;
    dmem[10768] = 32'd0;
    dmem[10769] = 32'd0;
    dmem[10770] = 32'd0;
    dmem[10771] = 32'd0;
    dmem[10772] = 32'd0;
    dmem[10773] = 32'd0;
    dmem[10774] = 32'd0;
    dmem[10775] = 32'd0;
    dmem[10776] = 32'd0;
    dmem[10777] = 32'd0;
    dmem[10778] = 32'd0;
    dmem[10779] = 32'd0;
    dmem[10780] = 32'd0;
    dmem[10781] = 32'd0;
    dmem[10782] = 32'd0;
    dmem[10783] = 32'd0;
    dmem[10784] = 32'd0;
    dmem[10785] = 32'd0;
    dmem[10786] = 32'd0;
    dmem[10787] = 32'd0;
    dmem[10788] = 32'd0;
    dmem[10789] = 32'd0;
    dmem[10790] = 32'd0;
    dmem[10791] = 32'd0;
    dmem[10792] = 32'd0;
    dmem[10793] = 32'd0;
    dmem[10794] = 32'd0;
    dmem[10795] = 32'd0;
    dmem[10796] = 32'd0;
    dmem[10797] = 32'd0;
    dmem[10798] = 32'd0;
    dmem[10799] = 32'd0;
    dmem[10800] = 32'd0;
    dmem[10801] = 32'd0;
    dmem[10802] = 32'd0;
    dmem[10803] = 32'd0;
    dmem[10804] = 32'd0;
    dmem[10805] = 32'd0;
    dmem[10806] = 32'd0;
    dmem[10807] = 32'd0;
    dmem[10808] = 32'd0;
    dmem[10809] = 32'd0;
    dmem[10810] = 32'd0;
    dmem[10811] = 32'd0;
    dmem[10812] = 32'd0;
    dmem[10813] = 32'd0;
    dmem[10814] = 32'd0;
    dmem[10815] = 32'd0;
    dmem[10816] = 32'd0;
    dmem[10817] = 32'd0;
    dmem[10818] = 32'd0;
    dmem[10819] = 32'd0;
    dmem[10820] = 32'd0;
    dmem[10821] = 32'd0;
    dmem[10822] = 32'd0;
    dmem[10823] = 32'd0;
    dmem[10824] = 32'd0;
    dmem[10825] = 32'd0;
    dmem[10826] = 32'd0;
    dmem[10827] = 32'd0;
    dmem[10828] = 32'd0;
    dmem[10829] = 32'd0;
    dmem[10830] = 32'd0;
    dmem[10831] = 32'd0;
    dmem[10832] = 32'd0;
    dmem[10833] = 32'd0;
    dmem[10834] = 32'd0;
    dmem[10835] = 32'd0;
    dmem[10836] = 32'd0;
    dmem[10837] = 32'd0;
    dmem[10838] = 32'd0;
    dmem[10839] = 32'd0;
    dmem[10840] = 32'd0;
    dmem[10841] = 32'd0;
    dmem[10842] = 32'd0;
    dmem[10843] = 32'd0;
    dmem[10844] = 32'd0;
    dmem[10845] = 32'd0;
    dmem[10846] = 32'd0;
    dmem[10847] = 32'd0;
    dmem[10848] = 32'd0;
    dmem[10849] = 32'd0;
    dmem[10850] = 32'd0;
    dmem[10851] = 32'd0;
    dmem[10852] = 32'd0;
    dmem[10853] = 32'd0;
    dmem[10854] = 32'd0;
    dmem[10855] = 32'd0;
    dmem[10856] = 32'd0;
    dmem[10857] = 32'd0;
    dmem[10858] = 32'd0;
    dmem[10859] = 32'd0;
    dmem[10860] = 32'd0;
    dmem[10861] = 32'd0;
    dmem[10862] = 32'd0;
    dmem[10863] = 32'd0;
    dmem[10864] = 32'd0;
    dmem[10865] = 32'd0;
    dmem[10866] = 32'd0;
    dmem[10867] = 32'd0;
    dmem[10868] = 32'd0;
    dmem[10869] = 32'd0;
    dmem[10870] = 32'd0;
    dmem[10871] = 32'd0;
    dmem[10872] = 32'd0;
    dmem[10873] = 32'd0;
    dmem[10874] = 32'd0;
    dmem[10875] = 32'd0;
    dmem[10876] = 32'd0;
    dmem[10877] = 32'd0;
    dmem[10878] = 32'd0;
    dmem[10879] = 32'd0;
    dmem[10880] = 32'd0;
    dmem[10881] = 32'd0;
    dmem[10882] = 32'd0;
    dmem[10883] = 32'd0;
    dmem[10884] = 32'd0;
    dmem[10885] = 32'd0;
    dmem[10886] = 32'd0;
    dmem[10887] = 32'd0;
    dmem[10888] = 32'd0;
    dmem[10889] = 32'd0;
    dmem[10890] = 32'd0;
    dmem[10891] = 32'd0;
    dmem[10892] = 32'd0;
    dmem[10893] = 32'd0;
    dmem[10894] = 32'd0;
    dmem[10895] = 32'd0;
    dmem[10896] = 32'd0;
    dmem[10897] = 32'd0;
    dmem[10898] = 32'd0;
    dmem[10899] = 32'd0;
    dmem[10900] = 32'd0;
    dmem[10901] = 32'd0;
    dmem[10902] = 32'd0;
    dmem[10903] = 32'd0;
    dmem[10904] = 32'd0;
    dmem[10905] = 32'd0;
    dmem[10906] = 32'd0;
    dmem[10907] = 32'd0;
    dmem[10908] = 32'd0;
    dmem[10909] = 32'd0;
    dmem[10910] = 32'd0;
    dmem[10911] = 32'd0;
    dmem[10912] = 32'd0;
    dmem[10913] = 32'd0;
    dmem[10914] = 32'd0;
    dmem[10915] = 32'd0;
    dmem[10916] = 32'd0;
    dmem[10917] = 32'd0;
    dmem[10918] = 32'd0;
    dmem[10919] = 32'd0;
    dmem[10920] = 32'd0;
    dmem[10921] = 32'd0;
    dmem[10922] = 32'd0;
    dmem[10923] = 32'd0;
    dmem[10924] = 32'd0;
    dmem[10925] = 32'd0;
    dmem[10926] = 32'd0;
    dmem[10927] = 32'd0;
    dmem[10928] = 32'd0;
    dmem[10929] = 32'd0;
    dmem[10930] = 32'd0;
    dmem[10931] = 32'd0;
    dmem[10932] = 32'd0;
    dmem[10933] = 32'd0;
    dmem[10934] = 32'd0;
    dmem[10935] = 32'd0;
    dmem[10936] = 32'd0;
    dmem[10937] = 32'd0;
    dmem[10938] = 32'd0;
    dmem[10939] = 32'd0;
    dmem[10940] = 32'd0;
    dmem[10941] = 32'd0;
    dmem[10942] = 32'd0;
    dmem[10943] = 32'd0;
    dmem[10944] = 32'd0;
    dmem[10945] = 32'd0;
    dmem[10946] = 32'd0;
    dmem[10947] = 32'd0;
    dmem[10948] = 32'd0;
    dmem[10949] = 32'd0;
    dmem[10950] = 32'd0;
    dmem[10951] = 32'd0;
    dmem[10952] = 32'd0;
    dmem[10953] = 32'd0;
    dmem[10954] = 32'd0;
    dmem[10955] = 32'd0;
    dmem[10956] = 32'd0;
    dmem[10957] = 32'd0;
    dmem[10958] = 32'd0;
    dmem[10959] = 32'd0;
    dmem[10960] = 32'd0;
    dmem[10961] = 32'd0;
    dmem[10962] = 32'd0;
    dmem[10963] = 32'd0;
    dmem[10964] = 32'd0;
    dmem[10965] = 32'd0;
    dmem[10966] = 32'd0;
    dmem[10967] = 32'd0;
    dmem[10968] = 32'd0;
    dmem[10969] = 32'd0;
    dmem[10970] = 32'd0;
    dmem[10971] = 32'd0;
    dmem[10972] = 32'd0;
    dmem[10973] = 32'd0;
    dmem[10974] = 32'd0;
    dmem[10975] = 32'd0;
    dmem[10976] = 32'd0;
    dmem[10977] = 32'd0;
    dmem[10978] = 32'd0;
    dmem[10979] = 32'd0;
    dmem[10980] = 32'd0;
    dmem[10981] = 32'd0;
    dmem[10982] = 32'd0;
    dmem[10983] = 32'd0;
    dmem[10984] = 32'd0;
    dmem[10985] = 32'd0;
    dmem[10986] = 32'd0;
    dmem[10987] = 32'd0;
    dmem[10988] = 32'd0;
    dmem[10989] = 32'd0;
    dmem[10990] = 32'd0;
    dmem[10991] = 32'd0;
    dmem[10992] = 32'd0;
    dmem[10993] = 32'd0;
    dmem[10994] = 32'd0;
    dmem[10995] = 32'd0;
    dmem[10996] = 32'd0;
    dmem[10997] = 32'd0;
    dmem[10998] = 32'd0;
    dmem[10999] = 32'd0;
    dmem[11000] = 32'd0;
    dmem[11001] = 32'd0;
    dmem[11002] = 32'd0;
    dmem[11003] = 32'd0;
    dmem[11004] = 32'd0;
    dmem[11005] = 32'd0;
    dmem[11006] = 32'd0;
    dmem[11007] = 32'd0;
    dmem[11008] = 32'd0;
    dmem[11009] = 32'd0;
    dmem[11010] = 32'd0;
    dmem[11011] = 32'd0;
    dmem[11012] = 32'd0;
    dmem[11013] = 32'd0;
    dmem[11014] = 32'd0;
    dmem[11015] = 32'd0;
    dmem[11016] = 32'd0;
    dmem[11017] = 32'd0;
    dmem[11018] = 32'd0;
    dmem[11019] = 32'd0;
    dmem[11020] = 32'd0;
    dmem[11021] = 32'd0;
    dmem[11022] = 32'd0;
    dmem[11023] = 32'd0;
    dmem[11024] = 32'd0;
    dmem[11025] = 32'd0;
    dmem[11026] = 32'd0;
    dmem[11027] = 32'd0;
    dmem[11028] = 32'd0;
    dmem[11029] = 32'd0;
    dmem[11030] = 32'd0;
    dmem[11031] = 32'd0;
    dmem[11032] = 32'd0;
    dmem[11033] = 32'd0;
    dmem[11034] = 32'd0;
    dmem[11035] = 32'd0;
    dmem[11036] = 32'd0;
    dmem[11037] = 32'd0;
    dmem[11038] = 32'd0;
    dmem[11039] = 32'd0;
    dmem[11040] = 32'd0;
    dmem[11041] = 32'd0;
    dmem[11042] = 32'd0;
    dmem[11043] = 32'd0;
    dmem[11044] = 32'd0;
    dmem[11045] = 32'd0;
    dmem[11046] = 32'd0;
    dmem[11047] = 32'd0;
    dmem[11048] = 32'd0;
    dmem[11049] = 32'd0;
    dmem[11050] = 32'd0;
    dmem[11051] = 32'd0;
    dmem[11052] = 32'd0;
    dmem[11053] = 32'd0;
    dmem[11054] = 32'd0;
    dmem[11055] = 32'd0;
    dmem[11056] = 32'd0;
    dmem[11057] = 32'd0;
    dmem[11058] = 32'd0;
    dmem[11059] = 32'd0;
    dmem[11060] = 32'd0;
    dmem[11061] = 32'd0;
    dmem[11062] = 32'd0;
    dmem[11063] = 32'd0;
    dmem[11064] = 32'd0;
    dmem[11065] = 32'd0;
    dmem[11066] = 32'd0;
    dmem[11067] = 32'd0;
    dmem[11068] = 32'd0;
    dmem[11069] = 32'd0;
    dmem[11070] = 32'd0;
    dmem[11071] = 32'd0;
    dmem[11072] = 32'd0;
    dmem[11073] = 32'd0;
    dmem[11074] = 32'd0;
    dmem[11075] = 32'd0;
    dmem[11076] = 32'd0;
    dmem[11077] = 32'd0;
    dmem[11078] = 32'd0;
    dmem[11079] = 32'd0;
    dmem[11080] = 32'd0;
    dmem[11081] = 32'd0;
    dmem[11082] = 32'd0;
    dmem[11083] = 32'd0;
    dmem[11084] = 32'd0;
    dmem[11085] = 32'd0;
    dmem[11086] = 32'd0;
    dmem[11087] = 32'd0;
    dmem[11088] = 32'd0;
    dmem[11089] = 32'd0;
    dmem[11090] = 32'd0;
    dmem[11091] = 32'd0;
    dmem[11092] = 32'd0;
    dmem[11093] = 32'd0;
    dmem[11094] = 32'd0;
    dmem[11095] = 32'd0;
    dmem[11096] = 32'd0;
    dmem[11097] = 32'd0;
    dmem[11098] = 32'd0;
    dmem[11099] = 32'd0;
    dmem[11100] = 32'd0;
    dmem[11101] = 32'd0;
    dmem[11102] = 32'd0;
    dmem[11103] = 32'd0;
    dmem[11104] = 32'd0;
    dmem[11105] = 32'd0;
    dmem[11106] = 32'd0;
    dmem[11107] = 32'd0;
    dmem[11108] = 32'd0;
    dmem[11109] = 32'd0;
    dmem[11110] = 32'd0;
    dmem[11111] = 32'd0;
    dmem[11112] = 32'd0;
    dmem[11113] = 32'd0;
    dmem[11114] = 32'd0;
    dmem[11115] = 32'd0;
    dmem[11116] = 32'd0;
    dmem[11117] = 32'd0;
    dmem[11118] = 32'd0;
    dmem[11119] = 32'd0;
    dmem[11120] = 32'd0;
    dmem[11121] = 32'd0;
    dmem[11122] = 32'd0;
    dmem[11123] = 32'd0;
    dmem[11124] = 32'd0;
    dmem[11125] = 32'd0;
    dmem[11126] = 32'd0;
    dmem[11127] = 32'd0;
    dmem[11128] = 32'd0;
    dmem[11129] = 32'd0;
    dmem[11130] = 32'd0;
    dmem[11131] = 32'd0;
    dmem[11132] = 32'd0;
    dmem[11133] = 32'd0;
    dmem[11134] = 32'd0;
    dmem[11135] = 32'd0;
    dmem[11136] = 32'd0;
    dmem[11137] = 32'd0;
    dmem[11138] = 32'd0;
    dmem[11139] = 32'd0;
    dmem[11140] = 32'd0;
    dmem[11141] = 32'd0;
    dmem[11142] = 32'd0;
    dmem[11143] = 32'd0;
    dmem[11144] = 32'd0;
    dmem[11145] = 32'd0;
    dmem[11146] = 32'd0;
    dmem[11147] = 32'd0;
    dmem[11148] = 32'd0;
    dmem[11149] = 32'd0;
    dmem[11150] = 32'd0;
    dmem[11151] = 32'd0;
    dmem[11152] = 32'd0;
    dmem[11153] = 32'd0;
    dmem[11154] = 32'd0;
    dmem[11155] = 32'd0;
    dmem[11156] = 32'd0;
    dmem[11157] = 32'd0;
    dmem[11158] = 32'd0;
    dmem[11159] = 32'd0;
    dmem[11160] = 32'd0;
    dmem[11161] = 32'd0;
    dmem[11162] = 32'd0;
    dmem[11163] = 32'd0;
    dmem[11164] = 32'd0;
    dmem[11165] = 32'd0;
    dmem[11166] = 32'd0;
    dmem[11167] = 32'd0;
    dmem[11168] = 32'd0;
    dmem[11169] = 32'd0;
    dmem[11170] = 32'd0;
    dmem[11171] = 32'd0;
    dmem[11172] = 32'd0;
    dmem[11173] = 32'd0;
    dmem[11174] = 32'd0;
    dmem[11175] = 32'd0;
    dmem[11176] = 32'd0;
    dmem[11177] = 32'd0;
    dmem[11178] = 32'd0;
    dmem[11179] = 32'd0;
    dmem[11180] = 32'd0;
    dmem[11181] = 32'd0;
    dmem[11182] = 32'd0;
    dmem[11183] = 32'd0;
    dmem[11184] = 32'd0;
    dmem[11185] = 32'd0;
    dmem[11186] = 32'd0;
    dmem[11187] = 32'd0;
    dmem[11188] = 32'd0;
    dmem[11189] = 32'd0;
    dmem[11190] = 32'd0;
    dmem[11191] = 32'd0;
    dmem[11192] = 32'd0;
    dmem[11193] = 32'd0;
    dmem[11194] = 32'd0;
    dmem[11195] = 32'd0;
    dmem[11196] = 32'd0;
    dmem[11197] = 32'd0;
    dmem[11198] = 32'd0;
    dmem[11199] = 32'd0;
    dmem[11200] = 32'd0;
    dmem[11201] = 32'd0;
    dmem[11202] = 32'd0;
    dmem[11203] = 32'd0;
    dmem[11204] = 32'd0;
    dmem[11205] = 32'd0;
    dmem[11206] = 32'd0;
    dmem[11207] = 32'd0;
    dmem[11208] = 32'd0;
    dmem[11209] = 32'd0;
    dmem[11210] = 32'd0;
    dmem[11211] = 32'd0;
    dmem[11212] = 32'd0;
    dmem[11213] = 32'd0;
    dmem[11214] = 32'd0;
    dmem[11215] = 32'd0;
    dmem[11216] = 32'd0;
    dmem[11217] = 32'd0;
    dmem[11218] = 32'd0;
    dmem[11219] = 32'd0;
    dmem[11220] = 32'd0;
    dmem[11221] = 32'd0;
    dmem[11222] = 32'd0;
    dmem[11223] = 32'd0;
    dmem[11224] = 32'd0;
    dmem[11225] = 32'd0;
    dmem[11226] = 32'd0;
    dmem[11227] = 32'd0;
    dmem[11228] = 32'd0;
    dmem[11229] = 32'd0;
    dmem[11230] = 32'd0;
    dmem[11231] = 32'd0;
    dmem[11232] = 32'd0;
    dmem[11233] = 32'd0;
    dmem[11234] = 32'd0;
    dmem[11235] = 32'd0;
    dmem[11236] = 32'd0;
    dmem[11237] = 32'd0;
    dmem[11238] = 32'd0;
    dmem[11239] = 32'd0;
    dmem[11240] = 32'd0;
    dmem[11241] = 32'd0;
    dmem[11242] = 32'd0;
    dmem[11243] = 32'd0;
    dmem[11244] = 32'd0;
    dmem[11245] = 32'd0;
    dmem[11246] = 32'd0;
    dmem[11247] = 32'd0;
    dmem[11248] = 32'd0;
    dmem[11249] = 32'd0;
    dmem[11250] = 32'd0;
    dmem[11251] = 32'd0;
    dmem[11252] = 32'd0;
    dmem[11253] = 32'd0;
    dmem[11254] = 32'd0;
    dmem[11255] = 32'd0;
    dmem[11256] = 32'd0;
    dmem[11257] = 32'd0;
    dmem[11258] = 32'd0;
    dmem[11259] = 32'd0;
    dmem[11260] = 32'd0;
    dmem[11261] = 32'd0;
    dmem[11262] = 32'd0;
    dmem[11263] = 32'd0;
    dmem[11264] = 32'd0;
    dmem[11265] = 32'd0;
    dmem[11266] = 32'd0;
    dmem[11267] = 32'd0;
    dmem[11268] = 32'd0;
    dmem[11269] = 32'd0;
    dmem[11270] = 32'd0;
    dmem[11271] = 32'd0;
    dmem[11272] = 32'd0;
    dmem[11273] = 32'd0;
    dmem[11274] = 32'd0;
    dmem[11275] = 32'd0;
    dmem[11276] = 32'd0;
    dmem[11277] = 32'd0;
    dmem[11278] = 32'd0;
    dmem[11279] = 32'd0;
    dmem[11280] = 32'd0;
    dmem[11281] = 32'd0;
    dmem[11282] = 32'd0;
    dmem[11283] = 32'd0;
    dmem[11284] = 32'd0;
    dmem[11285] = 32'd0;
    dmem[11286] = 32'd0;
    dmem[11287] = 32'd0;
    dmem[11288] = 32'd0;
    dmem[11289] = 32'd0;
    dmem[11290] = 32'd0;
    dmem[11291] = 32'd0;
    dmem[11292] = 32'd0;
    dmem[11293] = 32'd0;
    dmem[11294] = 32'd0;
    dmem[11295] = 32'd0;
    dmem[11296] = 32'd0;
    dmem[11297] = 32'd0;
    dmem[11298] = 32'd0;
    dmem[11299] = 32'd0;
    dmem[11300] = 32'd0;
    dmem[11301] = 32'd0;
    dmem[11302] = 32'd0;
    dmem[11303] = 32'd0;
    dmem[11304] = 32'd0;
    dmem[11305] = 32'd0;
    dmem[11306] = 32'd0;
    dmem[11307] = 32'd0;
    dmem[11308] = 32'd0;
    dmem[11309] = 32'd0;
    dmem[11310] = 32'd0;
    dmem[11311] = 32'd0;
    dmem[11312] = 32'd0;
    dmem[11313] = 32'd0;
    dmem[11314] = 32'd0;
    dmem[11315] = 32'd0;
    dmem[11316] = 32'd0;
    dmem[11317] = 32'd0;
    dmem[11318] = 32'd0;
    dmem[11319] = 32'd0;
    dmem[11320] = 32'd0;
    dmem[11321] = 32'd0;
    dmem[11322] = 32'd0;
    dmem[11323] = 32'd0;
    dmem[11324] = 32'd0;
    dmem[11325] = 32'd0;
    dmem[11326] = 32'd0;
    dmem[11327] = 32'd0;
    dmem[11328] = 32'd0;
    dmem[11329] = 32'd0;
    dmem[11330] = 32'd0;
    dmem[11331] = 32'd0;
    dmem[11332] = 32'd0;
    dmem[11333] = 32'd0;
    dmem[11334] = 32'd0;
    dmem[11335] = 32'd0;
    dmem[11336] = 32'd0;
    dmem[11337] = 32'd0;
    dmem[11338] = 32'd0;
    dmem[11339] = 32'd0;
    dmem[11340] = 32'd0;
    dmem[11341] = 32'd0;
    dmem[11342] = 32'd0;
    dmem[11343] = 32'd0;
    dmem[11344] = 32'd0;
    dmem[11345] = 32'd0;
    dmem[11346] = 32'd0;
    dmem[11347] = 32'd0;
    dmem[11348] = 32'd0;
    dmem[11349] = 32'd0;
    dmem[11350] = 32'd0;
    dmem[11351] = 32'd0;
    dmem[11352] = 32'd0;
    dmem[11353] = 32'd0;
    dmem[11354] = 32'd0;
    dmem[11355] = 32'd0;
    dmem[11356] = 32'd0;
    dmem[11357] = 32'd0;
    dmem[11358] = 32'd0;
    dmem[11359] = 32'd0;
    dmem[11360] = 32'd0;
    dmem[11361] = 32'd0;
    dmem[11362] = 32'd0;
    dmem[11363] = 32'd0;
    dmem[11364] = 32'd0;
    dmem[11365] = 32'd0;
    dmem[11366] = 32'd0;
    dmem[11367] = 32'd0;
    dmem[11368] = 32'd0;
    dmem[11369] = 32'd0;
    dmem[11370] = 32'd0;
    dmem[11371] = 32'd0;
    dmem[11372] = 32'd0;
    dmem[11373] = 32'd0;
    dmem[11374] = 32'd0;
    dmem[11375] = 32'd0;
    dmem[11376] = 32'd0;
    dmem[11377] = 32'd0;
    dmem[11378] = 32'd0;
    dmem[11379] = 32'd0;
    dmem[11380] = 32'd0;
    dmem[11381] = 32'd0;
    dmem[11382] = 32'd0;
    dmem[11383] = 32'd0;
    dmem[11384] = 32'd0;
    dmem[11385] = 32'd0;
    dmem[11386] = 32'd0;
    dmem[11387] = 32'd0;
    dmem[11388] = 32'd0;
    dmem[11389] = 32'd0;
    dmem[11390] = 32'd0;
    dmem[11391] = 32'd0;
    dmem[11392] = 32'd0;
    dmem[11393] = 32'd0;
    dmem[11394] = 32'd0;
    dmem[11395] = 32'd0;
    dmem[11396] = 32'd0;
    dmem[11397] = 32'd0;
    dmem[11398] = 32'd0;
    dmem[11399] = 32'd0;
    dmem[11400] = 32'd0;
    dmem[11401] = 32'd0;
    dmem[11402] = 32'd0;
    dmem[11403] = 32'd0;
    dmem[11404] = 32'd0;
    dmem[11405] = 32'd0;
    dmem[11406] = 32'd0;
    dmem[11407] = 32'd0;
    dmem[11408] = 32'd0;
    dmem[11409] = 32'd0;
    dmem[11410] = 32'd0;
    dmem[11411] = 32'd0;
    dmem[11412] = 32'd0;
    dmem[11413] = 32'd0;
    dmem[11414] = 32'd0;
    dmem[11415] = 32'd0;
    dmem[11416] = 32'd0;
    dmem[11417] = 32'd0;
    dmem[11418] = 32'd0;
    dmem[11419] = 32'd0;
    dmem[11420] = 32'd0;
    dmem[11421] = 32'd0;
    dmem[11422] = 32'd0;
    dmem[11423] = 32'd0;
    dmem[11424] = 32'd0;
    dmem[11425] = 32'd0;
    dmem[11426] = 32'd0;
    dmem[11427] = 32'd0;
    dmem[11428] = 32'd0;
    dmem[11429] = 32'd0;
    dmem[11430] = 32'd0;
    dmem[11431] = 32'd0;
    dmem[11432] = 32'd0;
    dmem[11433] = 32'd0;
    dmem[11434] = 32'd0;
    dmem[11435] = 32'd0;
    dmem[11436] = 32'd0;
    dmem[11437] = 32'd0;
    dmem[11438] = 32'd0;
    dmem[11439] = 32'd0;
    dmem[11440] = 32'd0;
    dmem[11441] = 32'd0;
    dmem[11442] = 32'd0;
    dmem[11443] = 32'd0;
    dmem[11444] = 32'd0;
    dmem[11445] = 32'd0;
    dmem[11446] = 32'd0;
    dmem[11447] = 32'd0;
    dmem[11448] = 32'd0;
    dmem[11449] = 32'd0;
    dmem[11450] = 32'd0;
    dmem[11451] = 32'd0;
    dmem[11452] = 32'd0;
    dmem[11453] = 32'd0;
    dmem[11454] = 32'd0;
    dmem[11455] = 32'd0;
    dmem[11456] = 32'd0;
    dmem[11457] = 32'd0;
    dmem[11458] = 32'd0;
    dmem[11459] = 32'd0;
    dmem[11460] = 32'd0;
    dmem[11461] = 32'd0;
    dmem[11462] = 32'd0;
    dmem[11463] = 32'd0;
    dmem[11464] = 32'd0;
    dmem[11465] = 32'd0;
    dmem[11466] = 32'd0;
    dmem[11467] = 32'd0;
    dmem[11468] = 32'd0;
    dmem[11469] = 32'd0;
    dmem[11470] = 32'd0;
    dmem[11471] = 32'd0;
    dmem[11472] = 32'd0;
    dmem[11473] = 32'd0;
    dmem[11474] = 32'd0;
    dmem[11475] = 32'd0;
    dmem[11476] = 32'd0;
    dmem[11477] = 32'd0;
    dmem[11478] = 32'd0;
    dmem[11479] = 32'd0;
    dmem[11480] = 32'd0;
    dmem[11481] = 32'd0;
    dmem[11482] = 32'd0;
    dmem[11483] = 32'd0;
    dmem[11484] = 32'd0;
    dmem[11485] = 32'd0;
    dmem[11486] = 32'd0;
    dmem[11487] = 32'd0;
    dmem[11488] = 32'd0;
    dmem[11489] = 32'd0;
    dmem[11490] = 32'd0;
    dmem[11491] = 32'd0;
    dmem[11492] = 32'd0;
    dmem[11493] = 32'd0;
    dmem[11494] = 32'd0;
    dmem[11495] = 32'd0;
    dmem[11496] = 32'd0;
    dmem[11497] = 32'd0;
    dmem[11498] = 32'd0;
    dmem[11499] = 32'd0;
    dmem[11500] = 32'd0;
    dmem[11501] = 32'd0;
    dmem[11502] = 32'd0;
    dmem[11503] = 32'd0;
    dmem[11504] = 32'd0;
    dmem[11505] = 32'd0;
    dmem[11506] = 32'd0;
    dmem[11507] = 32'd0;
    dmem[11508] = 32'd0;
    dmem[11509] = 32'd0;
    dmem[11510] = 32'd0;
    dmem[11511] = 32'd0;
    dmem[11512] = 32'd0;
    dmem[11513] = 32'd0;
    dmem[11514] = 32'd0;
    dmem[11515] = 32'd0;
    dmem[11516] = 32'd0;
    dmem[11517] = 32'd0;
    dmem[11518] = 32'd0;
    dmem[11519] = 32'd0;
    dmem[11520] = 32'd0;
    dmem[11521] = 32'd0;
    dmem[11522] = 32'd0;
    dmem[11523] = 32'd0;
    dmem[11524] = 32'd0;
    dmem[11525] = 32'd0;
    dmem[11526] = 32'd0;
    dmem[11527] = 32'd0;
    dmem[11528] = 32'd0;
    dmem[11529] = 32'd0;
    dmem[11530] = 32'd0;
    dmem[11531] = 32'd0;
    dmem[11532] = 32'd0;
    dmem[11533] = 32'd0;
    dmem[11534] = 32'd0;
    dmem[11535] = 32'd0;
    dmem[11536] = 32'd0;
    dmem[11537] = 32'd0;
    dmem[11538] = 32'd0;
    dmem[11539] = 32'd0;
    dmem[11540] = 32'd0;
    dmem[11541] = 32'd0;
    dmem[11542] = 32'd0;
    dmem[11543] = 32'd0;
    dmem[11544] = 32'd0;
    dmem[11545] = 32'd0;
    dmem[11546] = 32'd0;
    dmem[11547] = 32'd0;
    dmem[11548] = 32'd0;
    dmem[11549] = 32'd0;
    dmem[11550] = 32'd0;
    dmem[11551] = 32'd0;
    dmem[11552] = 32'd0;
    dmem[11553] = 32'd0;
    dmem[11554] = 32'd0;
    dmem[11555] = 32'd0;
    dmem[11556] = 32'd0;
    dmem[11557] = 32'd0;
    dmem[11558] = 32'd0;
    dmem[11559] = 32'd0;
    dmem[11560] = 32'd0;
    dmem[11561] = 32'd0;
    dmem[11562] = 32'd0;
    dmem[11563] = 32'd0;
    dmem[11564] = 32'd0;
    dmem[11565] = 32'd0;
    dmem[11566] = 32'd0;
    dmem[11567] = 32'd0;
    dmem[11568] = 32'd0;
    dmem[11569] = 32'd0;
    dmem[11570] = 32'd0;
    dmem[11571] = 32'd0;
    dmem[11572] = 32'd0;
    dmem[11573] = 32'd0;
    dmem[11574] = 32'd0;
    dmem[11575] = 32'd0;
    dmem[11576] = 32'd0;
    dmem[11577] = 32'd0;
    dmem[11578] = 32'd0;
    dmem[11579] = 32'd0;
    dmem[11580] = 32'd0;
    dmem[11581] = 32'd0;
    dmem[11582] = 32'd0;
    dmem[11583] = 32'd0;
    dmem[11584] = 32'd0;
    dmem[11585] = 32'd0;
    dmem[11586] = 32'd0;
    dmem[11587] = 32'd0;
    dmem[11588] = 32'd0;
    dmem[11589] = 32'd0;
    dmem[11590] = 32'd0;
    dmem[11591] = 32'd0;
    dmem[11592] = 32'd0;
    dmem[11593] = 32'd0;
    dmem[11594] = 32'd0;
    dmem[11595] = 32'd0;
    dmem[11596] = 32'd0;
    dmem[11597] = 32'd0;
    dmem[11598] = 32'd0;
    dmem[11599] = 32'd0;
    dmem[11600] = 32'd0;
    dmem[11601] = 32'd0;
    dmem[11602] = 32'd0;
    dmem[11603] = 32'd0;
    dmem[11604] = 32'd0;
    dmem[11605] = 32'd0;
    dmem[11606] = 32'd0;
    dmem[11607] = 32'd0;
    dmem[11608] = 32'd0;
    dmem[11609] = 32'd0;
    dmem[11610] = 32'd0;
    dmem[11611] = 32'd0;
    dmem[11612] = 32'd0;
    dmem[11613] = 32'd0;
    dmem[11614] = 32'd0;
    dmem[11615] = 32'd0;
    dmem[11616] = 32'd0;
    dmem[11617] = 32'd0;
    dmem[11618] = 32'd0;
    dmem[11619] = 32'd0;
    dmem[11620] = 32'd0;
    dmem[11621] = 32'd0;
    dmem[11622] = 32'd0;
    dmem[11623] = 32'd0;
    dmem[11624] = 32'd0;
    dmem[11625] = 32'd0;
    dmem[11626] = 32'd0;
    dmem[11627] = 32'd0;
    dmem[11628] = 32'd0;
    dmem[11629] = 32'd0;
    dmem[11630] = 32'd0;
    dmem[11631] = 32'd0;
    dmem[11632] = 32'd0;
    dmem[11633] = 32'd0;
    dmem[11634] = 32'd0;
    dmem[11635] = 32'd0;
    dmem[11636] = 32'd0;
    dmem[11637] = 32'd0;
    dmem[11638] = 32'd0;
    dmem[11639] = 32'd0;
    dmem[11640] = 32'd0;
    dmem[11641] = 32'd0;
    dmem[11642] = 32'd0;
    dmem[11643] = 32'd0;
    dmem[11644] = 32'd0;
    dmem[11645] = 32'd0;
    dmem[11646] = 32'd0;
    dmem[11647] = 32'd0;
    dmem[11648] = 32'd0;
    dmem[11649] = 32'd0;
    dmem[11650] = 32'd0;
    dmem[11651] = 32'd0;
    dmem[11652] = 32'd0;
    dmem[11653] = 32'd0;
    dmem[11654] = 32'd0;
    dmem[11655] = 32'd0;
    dmem[11656] = 32'd0;
    dmem[11657] = 32'd0;
    dmem[11658] = 32'd0;
    dmem[11659] = 32'd0;
    dmem[11660] = 32'd0;
    dmem[11661] = 32'd0;
    dmem[11662] = 32'd0;
    dmem[11663] = 32'd0;
    dmem[11664] = 32'd0;
    dmem[11665] = 32'd0;
    dmem[11666] = 32'd0;
    dmem[11667] = 32'd0;
    dmem[11668] = 32'd0;
    dmem[11669] = 32'd0;
    dmem[11670] = 32'd0;
    dmem[11671] = 32'd0;
    dmem[11672] = 32'd0;
    dmem[11673] = 32'd0;
    dmem[11674] = 32'd0;
    dmem[11675] = 32'd0;
    dmem[11676] = 32'd0;
    dmem[11677] = 32'd0;
    dmem[11678] = 32'd0;
    dmem[11679] = 32'd0;
    dmem[11680] = 32'd0;
    dmem[11681] = 32'd0;
    dmem[11682] = 32'd0;
    dmem[11683] = 32'd0;
    dmem[11684] = 32'd0;
    dmem[11685] = 32'd0;
    dmem[11686] = 32'd0;
    dmem[11687] = 32'd0;
    dmem[11688] = 32'd0;
    dmem[11689] = 32'd0;
    dmem[11690] = 32'd0;
    dmem[11691] = 32'd0;
    dmem[11692] = 32'd0;
    dmem[11693] = 32'd0;
    dmem[11694] = 32'd0;
    dmem[11695] = 32'd0;
    dmem[11696] = 32'd0;
    dmem[11697] = 32'd0;
    dmem[11698] = 32'd0;
    dmem[11699] = 32'd0;
    dmem[11700] = 32'd0;
    dmem[11701] = 32'd0;
    dmem[11702] = 32'd0;
    dmem[11703] = 32'd0;
    dmem[11704] = 32'd0;
    dmem[11705] = 32'd0;
    dmem[11706] = 32'd0;
    dmem[11707] = 32'd0;
    dmem[11708] = 32'd0;
    dmem[11709] = 32'd0;
    dmem[11710] = 32'd0;
    dmem[11711] = 32'd0;
    dmem[11712] = 32'd0;
    dmem[11713] = 32'd0;
    dmem[11714] = 32'd0;
    dmem[11715] = 32'd0;
    dmem[11716] = 32'd0;
    dmem[11717] = 32'd0;
    dmem[11718] = 32'd0;
    dmem[11719] = 32'd0;
    dmem[11720] = 32'd0;
    dmem[11721] = 32'd0;
    dmem[11722] = 32'd0;
    dmem[11723] = 32'd0;
    dmem[11724] = 32'd0;
    dmem[11725] = 32'd0;
    dmem[11726] = 32'd0;
    dmem[11727] = 32'd0;
    dmem[11728] = 32'd0;
    dmem[11729] = 32'd0;
    dmem[11730] = 32'd0;
    dmem[11731] = 32'd0;
    dmem[11732] = 32'd0;
    dmem[11733] = 32'd0;
    dmem[11734] = 32'd0;
    dmem[11735] = 32'd0;
    dmem[11736] = 32'd0;
    dmem[11737] = 32'd0;
    dmem[11738] = 32'd0;
    dmem[11739] = 32'd0;
    dmem[11740] = 32'd0;
    dmem[11741] = 32'd0;
    dmem[11742] = 32'd0;
    dmem[11743] = 32'd0;
    dmem[11744] = 32'd0;
    dmem[11745] = 32'd0;
    dmem[11746] = 32'd0;
    dmem[11747] = 32'd0;
    dmem[11748] = 32'd0;
    dmem[11749] = 32'd0;
    dmem[11750] = 32'd0;
    dmem[11751] = 32'd0;
    dmem[11752] = 32'd0;
    dmem[11753] = 32'd0;
    dmem[11754] = 32'd0;
    dmem[11755] = 32'd0;
    dmem[11756] = 32'd0;
    dmem[11757] = 32'd0;
    dmem[11758] = 32'd0;
    dmem[11759] = 32'd0;
    dmem[11760] = 32'd0;
    dmem[11761] = 32'd0;
    dmem[11762] = 32'd0;
    dmem[11763] = 32'd0;
    dmem[11764] = 32'd0;
    dmem[11765] = 32'd0;
    dmem[11766] = 32'd0;
    dmem[11767] = 32'd0;
    dmem[11768] = 32'd0;
    dmem[11769] = 32'd0;
    dmem[11770] = 32'd0;
    dmem[11771] = 32'd0;
    dmem[11772] = 32'd0;
    dmem[11773] = 32'd0;
    dmem[11774] = 32'd0;
    dmem[11775] = 32'd0;
    dmem[11776] = 32'd0;
    dmem[11777] = 32'd0;
    dmem[11778] = 32'd0;
    dmem[11779] = 32'd0;
    dmem[11780] = 32'd0;
    dmem[11781] = 32'd0;
    dmem[11782] = 32'd0;
    dmem[11783] = 32'd0;
    dmem[11784] = 32'd0;
    dmem[11785] = 32'd0;
    dmem[11786] = 32'd0;
    dmem[11787] = 32'd0;
    dmem[11788] = 32'd0;
    dmem[11789] = 32'd0;
    dmem[11790] = 32'd0;
    dmem[11791] = 32'd0;
    dmem[11792] = 32'd0;
    dmem[11793] = 32'd0;
    dmem[11794] = 32'd0;
    dmem[11795] = 32'd0;
    dmem[11796] = 32'd0;
    dmem[11797] = 32'd0;
    dmem[11798] = 32'd0;
    dmem[11799] = 32'd0;
    dmem[11800] = 32'd0;
    dmem[11801] = 32'd0;
    dmem[11802] = 32'd0;
    dmem[11803] = 32'd0;
    dmem[11804] = 32'd0;
    dmem[11805] = 32'd0;
    dmem[11806] = 32'd0;
    dmem[11807] = 32'd0;
    dmem[11808] = 32'd0;
    dmem[11809] = 32'd0;
    dmem[11810] = 32'd0;
    dmem[11811] = 32'd0;
    dmem[11812] = 32'd0;
    dmem[11813] = 32'd0;
    dmem[11814] = 32'd0;
    dmem[11815] = 32'd0;
    dmem[11816] = 32'd0;
    dmem[11817] = 32'd0;
    dmem[11818] = 32'd0;
    dmem[11819] = 32'd0;
    dmem[11820] = 32'd0;
    dmem[11821] = 32'd0;
    dmem[11822] = 32'd0;
    dmem[11823] = 32'd0;
    dmem[11824] = 32'd0;
    dmem[11825] = 32'd0;
    dmem[11826] = 32'd0;
    dmem[11827] = 32'd0;
    dmem[11828] = 32'd0;
    dmem[11829] = 32'd0;
    dmem[11830] = 32'd0;
    dmem[11831] = 32'd0;
    dmem[11832] = 32'd0;
    dmem[11833] = 32'd0;
    dmem[11834] = 32'd0;
    dmem[11835] = 32'd0;
    dmem[11836] = 32'd0;
    dmem[11837] = 32'd0;
    dmem[11838] = 32'd0;
    dmem[11839] = 32'd0;
    dmem[11840] = 32'd0;
    dmem[11841] = 32'd0;
    dmem[11842] = 32'd0;
    dmem[11843] = 32'd0;
    dmem[11844] = 32'd0;
    dmem[11845] = 32'd0;
    dmem[11846] = 32'd0;
    dmem[11847] = 32'd0;
    dmem[11848] = 32'd0;
    dmem[11849] = 32'd0;
    dmem[11850] = 32'd0;
    dmem[11851] = 32'd0;
    dmem[11852] = 32'd0;
    dmem[11853] = 32'd0;
    dmem[11854] = 32'd0;
    dmem[11855] = 32'd0;
    dmem[11856] = 32'd0;
    dmem[11857] = 32'd0;
    dmem[11858] = 32'd0;
    dmem[11859] = 32'd0;
    dmem[11860] = 32'd0;
    dmem[11861] = 32'd0;
    dmem[11862] = 32'd0;
    dmem[11863] = 32'd0;
    dmem[11864] = 32'd0;
    dmem[11865] = 32'd0;
    dmem[11866] = 32'd0;
    dmem[11867] = 32'd0;
    dmem[11868] = 32'd0;
    dmem[11869] = 32'd0;
    dmem[11870] = 32'd0;
    dmem[11871] = 32'd0;
    dmem[11872] = 32'd0;
    dmem[11873] = 32'd0;
    dmem[11874] = 32'd0;
    dmem[11875] = 32'd0;
    dmem[11876] = 32'd0;
    dmem[11877] = 32'd0;
    dmem[11878] = 32'd0;
    dmem[11879] = 32'd0;
    dmem[11880] = 32'd0;
    dmem[11881] = 32'd0;
    dmem[11882] = 32'd0;
    dmem[11883] = 32'd0;
    dmem[11884] = 32'd0;
    dmem[11885] = 32'd0;
    dmem[11886] = 32'd0;
    dmem[11887] = 32'd0;
    dmem[11888] = 32'd0;
    dmem[11889] = 32'd0;
    dmem[11890] = 32'd0;
    dmem[11891] = 32'd0;
    dmem[11892] = 32'd0;
    dmem[11893] = 32'd0;
    dmem[11894] = 32'd0;
    dmem[11895] = 32'd0;
    dmem[11896] = 32'd0;
    dmem[11897] = 32'd0;
    dmem[11898] = 32'd0;
    dmem[11899] = 32'd0;
    dmem[11900] = 32'd0;
    dmem[11901] = 32'd0;
    dmem[11902] = 32'd0;
    dmem[11903] = 32'd0;
    dmem[11904] = 32'd0;
    dmem[11905] = 32'd0;
    dmem[11906] = 32'd0;
    dmem[11907] = 32'd0;
    dmem[11908] = 32'd0;
    dmem[11909] = 32'd0;
    dmem[11910] = 32'd0;
    dmem[11911] = 32'd0;
    dmem[11912] = 32'd0;
    dmem[11913] = 32'd0;
    dmem[11914] = 32'd0;
    dmem[11915] = 32'd0;
    dmem[11916] = 32'd0;
    dmem[11917] = 32'd0;
    dmem[11918] = 32'd0;
    dmem[11919] = 32'd0;
    dmem[11920] = 32'd0;
    dmem[11921] = 32'd0;
    dmem[11922] = 32'd0;
    dmem[11923] = 32'd0;
    dmem[11924] = 32'd0;
    dmem[11925] = 32'd0;
    dmem[11926] = 32'd0;
    dmem[11927] = 32'd0;
    dmem[11928] = 32'd0;
    dmem[11929] = 32'd0;
    dmem[11930] = 32'd0;
    dmem[11931] = 32'd0;
    dmem[11932] = 32'd0;
    dmem[11933] = 32'd0;
    dmem[11934] = 32'd0;
    dmem[11935] = 32'd0;
    dmem[11936] = 32'd0;
    dmem[11937] = 32'd0;
    dmem[11938] = 32'd0;
    dmem[11939] = 32'd0;
    dmem[11940] = 32'd0;
    dmem[11941] = 32'd0;
    dmem[11942] = 32'd0;
    dmem[11943] = 32'd0;
    dmem[11944] = 32'd0;
    dmem[11945] = 32'd0;
    dmem[11946] = 32'd0;
    dmem[11947] = 32'd0;
    dmem[11948] = 32'd0;
    dmem[11949] = 32'd0;
    dmem[11950] = 32'd0;
    dmem[11951] = 32'd0;
    dmem[11952] = 32'd0;
    dmem[11953] = 32'd0;
    dmem[11954] = 32'd0;
    dmem[11955] = 32'd0;
    dmem[11956] = 32'd0;
    dmem[11957] = 32'd0;
    dmem[11958] = 32'd0;
    dmem[11959] = 32'd0;
    dmem[11960] = 32'd0;
    dmem[11961] = 32'd0;
    dmem[11962] = 32'd0;
    dmem[11963] = 32'd0;
    dmem[11964] = 32'd0;
    dmem[11965] = 32'd0;
    dmem[11966] = 32'd0;
    dmem[11967] = 32'd0;
    dmem[11968] = 32'd0;
    dmem[11969] = 32'd0;
    dmem[11970] = 32'd0;
    dmem[11971] = 32'd0;
    dmem[11972] = 32'd0;
    dmem[11973] = 32'd0;
    dmem[11974] = 32'd0;
    dmem[11975] = 32'd0;
    dmem[11976] = 32'd0;
    dmem[11977] = 32'd0;
    dmem[11978] = 32'd0;
    dmem[11979] = 32'd0;
    dmem[11980] = 32'd0;
    dmem[11981] = 32'd0;
    dmem[11982] = 32'd0;
    dmem[11983] = 32'd0;
    dmem[11984] = 32'd0;
    dmem[11985] = 32'd0;
    dmem[11986] = 32'd0;
    dmem[11987] = 32'd0;
    dmem[11988] = 32'd0;
    dmem[11989] = 32'd0;
    dmem[11990] = 32'd0;
    dmem[11991] = 32'd0;
    dmem[11992] = 32'd0;
    dmem[11993] = 32'd0;
    dmem[11994] = 32'd0;
    dmem[11995] = 32'd0;
    dmem[11996] = 32'd0;
    dmem[11997] = 32'd0;
    dmem[11998] = 32'd0;
    dmem[11999] = 32'd0;
    dmem[12000] = 32'd0;
    dmem[12001] = 32'd0;
    dmem[12002] = 32'd0;
    dmem[12003] = 32'd0;
    dmem[12004] = 32'd0;
    dmem[12005] = 32'd0;
    dmem[12006] = 32'd0;
    dmem[12007] = 32'd0;
    dmem[12008] = 32'd0;
    dmem[12009] = 32'd0;
    dmem[12010] = 32'd0;
    dmem[12011] = 32'd0;
    dmem[12012] = 32'd0;
    dmem[12013] = 32'd0;
    dmem[12014] = 32'd0;
    dmem[12015] = 32'd0;
    dmem[12016] = 32'd0;
    dmem[12017] = 32'd0;
    dmem[12018] = 32'd0;
    dmem[12019] = 32'd0;
    dmem[12020] = 32'd0;
    dmem[12021] = 32'd0;
    dmem[12022] = 32'd0;
    dmem[12023] = 32'd0;
    dmem[12024] = 32'd0;
    dmem[12025] = 32'd0;
    dmem[12026] = 32'd0;
    dmem[12027] = 32'd0;
    dmem[12028] = 32'd0;
    dmem[12029] = 32'd0;
    dmem[12030] = 32'd0;
    dmem[12031] = 32'd0;
    dmem[12032] = 32'd0;
    dmem[12033] = 32'd0;
    dmem[12034] = 32'd0;
    dmem[12035] = 32'd0;
    dmem[12036] = 32'd0;
    dmem[12037] = 32'd0;
    dmem[12038] = 32'd0;
    dmem[12039] = 32'd0;
    dmem[12040] = 32'd0;
    dmem[12041] = 32'd0;
    dmem[12042] = 32'd0;
    dmem[12043] = 32'd0;
    dmem[12044] = 32'd0;
    dmem[12045] = 32'd0;
    dmem[12046] = 32'd0;
    dmem[12047] = 32'd0;
    dmem[12048] = 32'd0;
    dmem[12049] = 32'd0;
    dmem[12050] = 32'd0;
    dmem[12051] = 32'd0;
    dmem[12052] = 32'd0;
    dmem[12053] = 32'd0;
    dmem[12054] = 32'd0;
    dmem[12055] = 32'd0;
    dmem[12056] = 32'd0;
    dmem[12057] = 32'd0;
    dmem[12058] = 32'd0;
    dmem[12059] = 32'd0;
    dmem[12060] = 32'd0;
    dmem[12061] = 32'd0;
    dmem[12062] = 32'd0;
    dmem[12063] = 32'd0;
    dmem[12064] = 32'd0;
    dmem[12065] = 32'd0;
    dmem[12066] = 32'd0;
    dmem[12067] = 32'd0;
    dmem[12068] = 32'd0;
    dmem[12069] = 32'd0;
    dmem[12070] = 32'd0;
    dmem[12071] = 32'd0;
    dmem[12072] = 32'd0;
    dmem[12073] = 32'd0;
    dmem[12074] = 32'd0;
    dmem[12075] = 32'd0;
    dmem[12076] = 32'd0;
    dmem[12077] = 32'd0;
    dmem[12078] = 32'd0;
    dmem[12079] = 32'd0;
    dmem[12080] = 32'd0;
    dmem[12081] = 32'd0;
    dmem[12082] = 32'd0;
    dmem[12083] = 32'd0;
    dmem[12084] = 32'd0;
    dmem[12085] = 32'd0;
    dmem[12086] = 32'd0;
    dmem[12087] = 32'd0;
    dmem[12088] = 32'd0;
    dmem[12089] = 32'd0;
    dmem[12090] = 32'd0;
    dmem[12091] = 32'd0;
    dmem[12092] = 32'd0;
    dmem[12093] = 32'd0;
    dmem[12094] = 32'd0;
    dmem[12095] = 32'd0;
    dmem[12096] = 32'd0;
    dmem[12097] = 32'd0;
    dmem[12098] = 32'd0;
    dmem[12099] = 32'd0;
    dmem[12100] = 32'd0;
    dmem[12101] = 32'd0;
    dmem[12102] = 32'd0;
    dmem[12103] = 32'd0;
    dmem[12104] = 32'd0;
    dmem[12105] = 32'd0;
    dmem[12106] = 32'd0;
    dmem[12107] = 32'd0;
    dmem[12108] = 32'd0;
    dmem[12109] = 32'd0;
    dmem[12110] = 32'd0;
    dmem[12111] = 32'd0;
    dmem[12112] = 32'd0;
    dmem[12113] = 32'd0;
    dmem[12114] = 32'd0;
    dmem[12115] = 32'd0;
    dmem[12116] = 32'd0;
    dmem[12117] = 32'd0;
    dmem[12118] = 32'd0;
    dmem[12119] = 32'd0;
    dmem[12120] = 32'd0;
    dmem[12121] = 32'd0;
    dmem[12122] = 32'd0;
    dmem[12123] = 32'd0;
    dmem[12124] = 32'd0;
    dmem[12125] = 32'd0;
    dmem[12126] = 32'd0;
    dmem[12127] = 32'd0;
    dmem[12128] = 32'd0;
    dmem[12129] = 32'd0;
    dmem[12130] = 32'd0;
    dmem[12131] = 32'd0;
    dmem[12132] = 32'd0;
    dmem[12133] = 32'd0;
    dmem[12134] = 32'd0;
    dmem[12135] = 32'd0;
    dmem[12136] = 32'd0;
    dmem[12137] = 32'd0;
    dmem[12138] = 32'd0;
    dmem[12139] = 32'd0;
    dmem[12140] = 32'd0;
    dmem[12141] = 32'd0;
    dmem[12142] = 32'd0;
    dmem[12143] = 32'd0;
    dmem[12144] = 32'd0;
    dmem[12145] = 32'd0;
    dmem[12146] = 32'd0;
    dmem[12147] = 32'd0;
    dmem[12148] = 32'd0;
    dmem[12149] = 32'd0;
    dmem[12150] = 32'd0;
    dmem[12151] = 32'd0;
    dmem[12152] = 32'd0;
    dmem[12153] = 32'd0;
    dmem[12154] = 32'd0;
    dmem[12155] = 32'd0;
    dmem[12156] = 32'd0;
    dmem[12157] = 32'd0;
    dmem[12158] = 32'd0;
    dmem[12159] = 32'd0;
    dmem[12160] = 32'd0;
    dmem[12161] = 32'd0;
    dmem[12162] = 32'd0;
    dmem[12163] = 32'd0;
    dmem[12164] = 32'd0;
    dmem[12165] = 32'd0;
    dmem[12166] = 32'd0;
    dmem[12167] = 32'd0;
    dmem[12168] = 32'd0;
    dmem[12169] = 32'd0;
    dmem[12170] = 32'd0;
    dmem[12171] = 32'd0;
    dmem[12172] = 32'd0;
    dmem[12173] = 32'd0;
    dmem[12174] = 32'd0;
    dmem[12175] = 32'd0;
    dmem[12176] = 32'd0;
    dmem[12177] = 32'd0;
    dmem[12178] = 32'd0;
    dmem[12179] = 32'd0;
    dmem[12180] = 32'd0;
    dmem[12181] = 32'd0;
    dmem[12182] = 32'd0;
    dmem[12183] = 32'd0;
    dmem[12184] = 32'd0;
    dmem[12185] = 32'd0;
    dmem[12186] = 32'd0;
    dmem[12187] = 32'd0;
    dmem[12188] = 32'd0;
    dmem[12189] = 32'd0;
    dmem[12190] = 32'd0;
    dmem[12191] = 32'd0;
    dmem[12192] = 32'd0;
    dmem[12193] = 32'd0;
    dmem[12194] = 32'd0;
    dmem[12195] = 32'd0;
    dmem[12196] = 32'd0;
    dmem[12197] = 32'd0;
    dmem[12198] = 32'd0;
    dmem[12199] = 32'd0;
    dmem[12200] = 32'd0;
    dmem[12201] = 32'd0;
    dmem[12202] = 32'd0;
    dmem[12203] = 32'd0;
    dmem[12204] = 32'd0;
    dmem[12205] = 32'd0;
    dmem[12206] = 32'd0;
    dmem[12207] = 32'd0;
    dmem[12208] = 32'd0;
    dmem[12209] = 32'd0;
    dmem[12210] = 32'd0;
    dmem[12211] = 32'd0;
    dmem[12212] = 32'd0;
    dmem[12213] = 32'd0;
    dmem[12214] = 32'd0;
    dmem[12215] = 32'd0;
    dmem[12216] = 32'd0;
    dmem[12217] = 32'd0;
    dmem[12218] = 32'd0;
    dmem[12219] = 32'd0;
    dmem[12220] = 32'd0;
    dmem[12221] = 32'd0;
    dmem[12222] = 32'd0;
    dmem[12223] = 32'd0;
    dmem[12224] = 32'd0;
    dmem[12225] = 32'd0;
    dmem[12226] = 32'd0;
    dmem[12227] = 32'd0;
    dmem[12228] = 32'd0;
    dmem[12229] = 32'd0;
    dmem[12230] = 32'd0;
    dmem[12231] = 32'd0;
    dmem[12232] = 32'd0;
    dmem[12233] = 32'd0;
    dmem[12234] = 32'd0;
    dmem[12235] = 32'd0;
    dmem[12236] = 32'd0;
    dmem[12237] = 32'd0;
    dmem[12238] = 32'd0;
    dmem[12239] = 32'd0;
    dmem[12240] = 32'd0;
    dmem[12241] = 32'd0;
    dmem[12242] = 32'd0;
    dmem[12243] = 32'd0;
    dmem[12244] = 32'd0;
    dmem[12245] = 32'd0;
    dmem[12246] = 32'd0;
    dmem[12247] = 32'd0;
    dmem[12248] = 32'd0;
    dmem[12249] = 32'd0;
    dmem[12250] = 32'd0;
    dmem[12251] = 32'd0;
    dmem[12252] = 32'd0;
    dmem[12253] = 32'd0;
    dmem[12254] = 32'd0;
    dmem[12255] = 32'd0;
    dmem[12256] = 32'd0;
    dmem[12257] = 32'd0;
    dmem[12258] = 32'd0;
    dmem[12259] = 32'd0;
    dmem[12260] = 32'd0;
    dmem[12261] = 32'd0;
    dmem[12262] = 32'd0;
    dmem[12263] = 32'd0;
    dmem[12264] = 32'd0;
    dmem[12265] = 32'd0;
    dmem[12266] = 32'd0;
    dmem[12267] = 32'd0;
    dmem[12268] = 32'd0;
    dmem[12269] = 32'd0;
    dmem[12270] = 32'd0;
    dmem[12271] = 32'd0;
    dmem[12272] = 32'd0;
    dmem[12273] = 32'd0;
    dmem[12274] = 32'd0;
    dmem[12275] = 32'd0;
    dmem[12276] = 32'd0;
    dmem[12277] = 32'd0;
    dmem[12278] = 32'd0;
    dmem[12279] = 32'd0;
    dmem[12280] = 32'd0;
    dmem[12281] = 32'd0;
    dmem[12282] = 32'd0;
    dmem[12283] = 32'd0;
    dmem[12284] = 32'd0;
    dmem[12285] = 32'd0;
    dmem[12286] = 32'd0;
    dmem[12287] = 32'd0;
    dmem[12288] = 32'd0;
    dmem[12289] = 32'd0;
    dmem[12290] = 32'd0;
    dmem[12291] = 32'd0;
    dmem[12292] = 32'd0;
    dmem[12293] = 32'd0;
    dmem[12294] = 32'd0;
    dmem[12295] = 32'd0;
    dmem[12296] = 32'd0;
    dmem[12297] = 32'd0;
    dmem[12298] = 32'd0;
    dmem[12299] = 32'd0;
    dmem[12300] = 32'd0;
    dmem[12301] = 32'd0;
    dmem[12302] = 32'd0;
    dmem[12303] = 32'd0;
    dmem[12304] = 32'd0;
    dmem[12305] = 32'd0;
    dmem[12306] = 32'd0;
    dmem[12307] = 32'd0;
    dmem[12308] = 32'd0;
    dmem[12309] = 32'd0;
    dmem[12310] = 32'd0;
    dmem[12311] = 32'd0;
    dmem[12312] = 32'd0;
    dmem[12313] = 32'd0;
    dmem[12314] = 32'd0;
    dmem[12315] = 32'd0;
    dmem[12316] = 32'd0;
    dmem[12317] = 32'd0;
    dmem[12318] = 32'd0;
    dmem[12319] = 32'd0;
    dmem[12320] = 32'd0;
    dmem[12321] = 32'd0;
    dmem[12322] = 32'd0;
    dmem[12323] = 32'd0;
    dmem[12324] = 32'd0;
    dmem[12325] = 32'd0;
    dmem[12326] = 32'd0;
    dmem[12327] = 32'd0;
    dmem[12328] = 32'd0;
    dmem[12329] = 32'd0;
    dmem[12330] = 32'd0;
    dmem[12331] = 32'd0;
    dmem[12332] = 32'd0;
    dmem[12333] = 32'd0;
    dmem[12334] = 32'd0;
    dmem[12335] = 32'd0;
    dmem[12336] = 32'd0;
    dmem[12337] = 32'd0;
    dmem[12338] = 32'd0;
    dmem[12339] = 32'd0;
    dmem[12340] = 32'd0;
    dmem[12341] = 32'd0;
    dmem[12342] = 32'd0;
    dmem[12343] = 32'd0;
    dmem[12344] = 32'd0;
    dmem[12345] = 32'd0;
    dmem[12346] = 32'd0;
    dmem[12347] = 32'd0;
    dmem[12348] = 32'd0;
    dmem[12349] = 32'd0;
    dmem[12350] = 32'd0;
    dmem[12351] = 32'd0;
    dmem[12352] = 32'd0;
    dmem[12353] = 32'd0;
    dmem[12354] = 32'd0;
    dmem[12355] = 32'd0;
    dmem[12356] = 32'd0;
    dmem[12357] = 32'd0;
    dmem[12358] = 32'd0;
    dmem[12359] = 32'd0;
    dmem[12360] = 32'd0;
    dmem[12361] = 32'd0;
    dmem[12362] = 32'd0;
    dmem[12363] = 32'd0;
    dmem[12364] = 32'd0;
    dmem[12365] = 32'd0;
    dmem[12366] = 32'd0;
    dmem[12367] = 32'd0;
    dmem[12368] = 32'd0;
    dmem[12369] = 32'd0;
    dmem[12370] = 32'd0;
    dmem[12371] = 32'd0;
    dmem[12372] = 32'd0;
    dmem[12373] = 32'd0;
    dmem[12374] = 32'd0;
    dmem[12375] = 32'd0;
    dmem[12376] = 32'd0;
    dmem[12377] = 32'd0;
    dmem[12378] = 32'd0;
    dmem[12379] = 32'd0;
    dmem[12380] = 32'd0;
    dmem[12381] = 32'd0;
    dmem[12382] = 32'd0;
    dmem[12383] = 32'd0;
    dmem[12384] = 32'd0;
    dmem[12385] = 32'd0;
    dmem[12386] = 32'd0;
    dmem[12387] = 32'd0;
    dmem[12388] = 32'd0;
    dmem[12389] = 32'd0;
    dmem[12390] = 32'd0;
    dmem[12391] = 32'd0;
    dmem[12392] = 32'd0;
    dmem[12393] = 32'd0;
    dmem[12394] = 32'd0;
    dmem[12395] = 32'd0;
    dmem[12396] = 32'd0;
    dmem[12397] = 32'd0;
    dmem[12398] = 32'd0;
    dmem[12399] = 32'd0;
    dmem[12400] = 32'd0;
    dmem[12401] = 32'd0;
    dmem[12402] = 32'd0;
    dmem[12403] = 32'd0;
    dmem[12404] = 32'd0;
    dmem[12405] = 32'd0;
    dmem[12406] = 32'd0;
    dmem[12407] = 32'd0;
    dmem[12408] = 32'd0;
    dmem[12409] = 32'd0;
    dmem[12410] = 32'd0;
    dmem[12411] = 32'd0;
    dmem[12412] = 32'd0;
    dmem[12413] = 32'd0;
    dmem[12414] = 32'd0;
    dmem[12415] = 32'd0;
    dmem[12416] = 32'd0;
    dmem[12417] = 32'd0;
    dmem[12418] = 32'd0;
    dmem[12419] = 32'd0;
    dmem[12420] = 32'd0;
    dmem[12421] = 32'd0;
    dmem[12422] = 32'd0;
    dmem[12423] = 32'd0;
    dmem[12424] = 32'd0;
    dmem[12425] = 32'd0;
    dmem[12426] = 32'd0;
    dmem[12427] = 32'd0;
    dmem[12428] = 32'd0;
    dmem[12429] = 32'd0;
    dmem[12430] = 32'd0;
    dmem[12431] = 32'd0;
    dmem[12432] = 32'd0;
    dmem[12433] = 32'd0;
    dmem[12434] = 32'd0;
    dmem[12435] = 32'd0;
    dmem[12436] = 32'd0;
    dmem[12437] = 32'd0;
    dmem[12438] = 32'd0;
    dmem[12439] = 32'd0;
    dmem[12440] = 32'd0;
    dmem[12441] = 32'd0;
    dmem[12442] = 32'd0;
    dmem[12443] = 32'd0;
    dmem[12444] = 32'd0;
    dmem[12445] = 32'd0;
    dmem[12446] = 32'd0;
    dmem[12447] = 32'd0;
    dmem[12448] = 32'd0;
    dmem[12449] = 32'd0;
    dmem[12450] = 32'd0;
    dmem[12451] = 32'd0;
    dmem[12452] = 32'd0;
    dmem[12453] = 32'd0;
    dmem[12454] = 32'd0;
    dmem[12455] = 32'd0;
    dmem[12456] = 32'd0;
    dmem[12457] = 32'd0;
    dmem[12458] = 32'd0;
    dmem[12459] = 32'd0;
    dmem[12460] = 32'd0;
    dmem[12461] = 32'd0;
    dmem[12462] = 32'd0;
    dmem[12463] = 32'd0;
    dmem[12464] = 32'd0;
    dmem[12465] = 32'd0;
    dmem[12466] = 32'd0;
    dmem[12467] = 32'd0;
    dmem[12468] = 32'd0;
    dmem[12469] = 32'd0;
    dmem[12470] = 32'd0;
    dmem[12471] = 32'd0;
    dmem[12472] = 32'd0;
    dmem[12473] = 32'd0;
    dmem[12474] = 32'd0;
    dmem[12475] = 32'd0;
    dmem[12476] = 32'd0;
    dmem[12477] = 32'd0;
    dmem[12478] = 32'd0;
    dmem[12479] = 32'd0;
    dmem[12480] = 32'd0;
    dmem[12481] = 32'd0;
    dmem[12482] = 32'd0;
    dmem[12483] = 32'd0;
    dmem[12484] = 32'd0;
    dmem[12485] = 32'd0;
    dmem[12486] = 32'd0;
    dmem[12487] = 32'd0;
    dmem[12488] = 32'd0;
    dmem[12489] = 32'd0;
    dmem[12490] = 32'd0;
    dmem[12491] = 32'd0;
    dmem[12492] = 32'd0;
    dmem[12493] = 32'd0;
    dmem[12494] = 32'd0;
    dmem[12495] = 32'd0;
    dmem[12496] = 32'd0;
    dmem[12497] = 32'd0;
    dmem[12498] = 32'd0;
    dmem[12499] = 32'd0;
    dmem[12500] = 32'd0;
    dmem[12501] = 32'd0;
    dmem[12502] = 32'd0;
    dmem[12503] = 32'd0;
    dmem[12504] = 32'd0;
    dmem[12505] = 32'd0;
    dmem[12506] = 32'd0;
    dmem[12507] = 32'd0;
    dmem[12508] = 32'd0;
    dmem[12509] = 32'd0;
    dmem[12510] = 32'd0;
    dmem[12511] = 32'd0;
    dmem[12512] = 32'd0;
    dmem[12513] = 32'd0;
    dmem[12514] = 32'd0;
    dmem[12515] = 32'd0;
    dmem[12516] = 32'd0;
    dmem[12517] = 32'd0;
    dmem[12518] = 32'd0;
    dmem[12519] = 32'd0;
    dmem[12520] = 32'd0;
    dmem[12521] = 32'd0;
    dmem[12522] = 32'd0;
    dmem[12523] = 32'd0;
    dmem[12524] = 32'd0;
    dmem[12525] = 32'd0;
    dmem[12526] = 32'd0;
    dmem[12527] = 32'd0;
    dmem[12528] = 32'd0;
    dmem[12529] = 32'd0;
    dmem[12530] = 32'd0;
    dmem[12531] = 32'd0;
    dmem[12532] = 32'd0;
    dmem[12533] = 32'd0;
    dmem[12534] = 32'd0;
    dmem[12535] = 32'd0;
    dmem[12536] = 32'd0;
    dmem[12537] = 32'd0;
    dmem[12538] = 32'd0;
    dmem[12539] = 32'd0;
    dmem[12540] = 32'd0;
    dmem[12541] = 32'd0;
    dmem[12542] = 32'd0;
    dmem[12543] = 32'd0;
    dmem[12544] = 32'd0;
    dmem[12545] = 32'd0;
    dmem[12546] = 32'd0;
    dmem[12547] = 32'd0;
    dmem[12548] = 32'd0;
    dmem[12549] = 32'd0;
    dmem[12550] = 32'd0;
    dmem[12551] = 32'd0;
    dmem[12552] = 32'd0;
    dmem[12553] = 32'd0;
    dmem[12554] = 32'd0;
    dmem[12555] = 32'd0;
    dmem[12556] = 32'd0;
    dmem[12557] = 32'd0;
    dmem[12558] = 32'd0;
    dmem[12559] = 32'd0;
    dmem[12560] = 32'd0;
    dmem[12561] = 32'd0;
    dmem[12562] = 32'd0;
    dmem[12563] = 32'd0;
    dmem[12564] = 32'd0;
    dmem[12565] = 32'd0;
    dmem[12566] = 32'd0;
    dmem[12567] = 32'd0;
    dmem[12568] = 32'd0;
    dmem[12569] = 32'd0;
    dmem[12570] = 32'd0;
    dmem[12571] = 32'd0;
    dmem[12572] = 32'd0;
    dmem[12573] = 32'd0;
    dmem[12574] = 32'd0;
    dmem[12575] = 32'd0;
    dmem[12576] = 32'd0;
    dmem[12577] = 32'd0;
    dmem[12578] = 32'd0;
    dmem[12579] = 32'd0;
    dmem[12580] = 32'd0;
    dmem[12581] = 32'd0;
    dmem[12582] = 32'd0;
    dmem[12583] = 32'd0;
    dmem[12584] = 32'd0;
    dmem[12585] = 32'd0;
    dmem[12586] = 32'd0;
    dmem[12587] = 32'd0;
    dmem[12588] = 32'd0;
    dmem[12589] = 32'd0;
    dmem[12590] = 32'd0;
    dmem[12591] = 32'd0;
    dmem[12592] = 32'd0;
    dmem[12593] = 32'd0;
    dmem[12594] = 32'd0;
    dmem[12595] = 32'd0;
    dmem[12596] = 32'd0;
    dmem[12597] = 32'd0;
    dmem[12598] = 32'd0;
    dmem[12599] = 32'd0;
    dmem[12600] = 32'd0;
    dmem[12601] = 32'd0;
    dmem[12602] = 32'd0;
    dmem[12603] = 32'd0;
    dmem[12604] = 32'd0;
    dmem[12605] = 32'd0;
    dmem[12606] = 32'd0;
    dmem[12607] = 32'd0;
    dmem[12608] = 32'd0;
    dmem[12609] = 32'd0;
    dmem[12610] = 32'd0;
    dmem[12611] = 32'd0;
    dmem[12612] = 32'd0;
    dmem[12613] = 32'd0;
    dmem[12614] = 32'd0;
    dmem[12615] = 32'd0;
    dmem[12616] = 32'd0;
    dmem[12617] = 32'd0;
    dmem[12618] = 32'd0;
    dmem[12619] = 32'd0;
    dmem[12620] = 32'd0;
    dmem[12621] = 32'd0;
    dmem[12622] = 32'd0;
    dmem[12623] = 32'd0;
    dmem[12624] = 32'd0;
    dmem[12625] = 32'd0;
    dmem[12626] = 32'd0;
    dmem[12627] = 32'd0;
    dmem[12628] = 32'd0;
    dmem[12629] = 32'd0;
    dmem[12630] = 32'd0;
    dmem[12631] = 32'd0;
    dmem[12632] = 32'd0;
    dmem[12633] = 32'd0;
    dmem[12634] = 32'd0;
    dmem[12635] = 32'd0;
    dmem[12636] = 32'd0;
    dmem[12637] = 32'd0;
    dmem[12638] = 32'd0;
    dmem[12639] = 32'd0;
    dmem[12640] = 32'd0;
    dmem[12641] = 32'd0;
    dmem[12642] = 32'd0;
    dmem[12643] = 32'd0;
    dmem[12644] = 32'd0;
    dmem[12645] = 32'd0;
    dmem[12646] = 32'd0;
    dmem[12647] = 32'd0;
    dmem[12648] = 32'd0;
    dmem[12649] = 32'd0;
    dmem[12650] = 32'd0;
    dmem[12651] = 32'd0;
    dmem[12652] = 32'd0;
    dmem[12653] = 32'd0;
    dmem[12654] = 32'd0;
    dmem[12655] = 32'd0;
    dmem[12656] = 32'd0;
    dmem[12657] = 32'd0;
    dmem[12658] = 32'd0;
    dmem[12659] = 32'd0;
    dmem[12660] = 32'd0;
    dmem[12661] = 32'd0;
    dmem[12662] = 32'd0;
    dmem[12663] = 32'd0;
    dmem[12664] = 32'd0;
    dmem[12665] = 32'd0;
    dmem[12666] = 32'd0;
    dmem[12667] = 32'd0;
    dmem[12668] = 32'd0;
    dmem[12669] = 32'd0;
    dmem[12670] = 32'd0;
    dmem[12671] = 32'd0;
    dmem[12672] = 32'd0;
    dmem[12673] = 32'd0;
    dmem[12674] = 32'd0;
    dmem[12675] = 32'd0;
    dmem[12676] = 32'd0;
    dmem[12677] = 32'd0;
    dmem[12678] = 32'd0;
    dmem[12679] = 32'd0;
    dmem[12680] = 32'd0;
    dmem[12681] = 32'd0;
    dmem[12682] = 32'd0;
    dmem[12683] = 32'd0;
    dmem[12684] = 32'd0;
    dmem[12685] = 32'd0;
    dmem[12686] = 32'd0;
    dmem[12687] = 32'd0;
    dmem[12688] = 32'd0;
    dmem[12689] = 32'd0;
    dmem[12690] = 32'd0;
    dmem[12691] = 32'd0;
    dmem[12692] = 32'd0;
    dmem[12693] = 32'd0;
    dmem[12694] = 32'd0;
    dmem[12695] = 32'd0;
    dmem[12696] = 32'd0;
    dmem[12697] = 32'd0;
    dmem[12698] = 32'd0;
    dmem[12699] = 32'd0;
    dmem[12700] = 32'd0;
    dmem[12701] = 32'd0;
    dmem[12702] = 32'd0;
    dmem[12703] = 32'd0;
    dmem[12704] = 32'd0;
    dmem[12705] = 32'd0;
    dmem[12706] = 32'd0;
    dmem[12707] = 32'd0;
    dmem[12708] = 32'd0;
    dmem[12709] = 32'd0;
    dmem[12710] = 32'd0;
    dmem[12711] = 32'd0;
    dmem[12712] = 32'd0;
    dmem[12713] = 32'd0;
    dmem[12714] = 32'd0;
    dmem[12715] = 32'd0;
    dmem[12716] = 32'd0;
    dmem[12717] = 32'd0;
    dmem[12718] = 32'd0;
    dmem[12719] = 32'd0;
    dmem[12720] = 32'd0;
    dmem[12721] = 32'd0;
    dmem[12722] = 32'd0;
    dmem[12723] = 32'd0;
    dmem[12724] = 32'd0;
    dmem[12725] = 32'd0;
    dmem[12726] = 32'd0;
    dmem[12727] = 32'd0;
    dmem[12728] = 32'd0;
    dmem[12729] = 32'd0;
    dmem[12730] = 32'd0;
    dmem[12731] = 32'd0;
    dmem[12732] = 32'd0;
    dmem[12733] = 32'd0;
    dmem[12734] = 32'd0;
    dmem[12735] = 32'd0;
    dmem[12736] = 32'd0;
    dmem[12737] = 32'd0;
    dmem[12738] = 32'd0;
    dmem[12739] = 32'd0;
    dmem[12740] = 32'd0;
    dmem[12741] = 32'd0;
    dmem[12742] = 32'd0;
    dmem[12743] = 32'd0;
    dmem[12744] = 32'd0;
    dmem[12745] = 32'd0;
    dmem[12746] = 32'd0;
    dmem[12747] = 32'd0;
    dmem[12748] = 32'd0;
    dmem[12749] = 32'd0;
    dmem[12750] = 32'd0;
    dmem[12751] = 32'd0;
    dmem[12752] = 32'd0;
    dmem[12753] = 32'd0;
    dmem[12754] = 32'd0;
    dmem[12755] = 32'd0;
    dmem[12756] = 32'd0;
    dmem[12757] = 32'd0;
    dmem[12758] = 32'd0;
    dmem[12759] = 32'd0;
    dmem[12760] = 32'd0;
    dmem[12761] = 32'd0;
    dmem[12762] = 32'd0;
    dmem[12763] = 32'd0;
    dmem[12764] = 32'd0;
    dmem[12765] = 32'd0;
    dmem[12766] = 32'd0;
    dmem[12767] = 32'd0;
    dmem[12768] = 32'd0;
    dmem[12769] = 32'd0;
    dmem[12770] = 32'd0;
    dmem[12771] = 32'd0;
    dmem[12772] = 32'd0;
    dmem[12773] = 32'd0;
    dmem[12774] = 32'd0;
    dmem[12775] = 32'd0;
    dmem[12776] = 32'd0;
    dmem[12777] = 32'd0;
    dmem[12778] = 32'd0;
    dmem[12779] = 32'd0;
    dmem[12780] = 32'd0;
    dmem[12781] = 32'd0;
    dmem[12782] = 32'd0;
    dmem[12783] = 32'd0;
    dmem[12784] = 32'd0;
    dmem[12785] = 32'd0;
    dmem[12786] = 32'd0;
    dmem[12787] = 32'd0;
    dmem[12788] = 32'd0;
    dmem[12789] = 32'd0;
    dmem[12790] = 32'd0;
    dmem[12791] = 32'd0;
    dmem[12792] = 32'd0;
    dmem[12793] = 32'd0;
    dmem[12794] = 32'd0;
    dmem[12795] = 32'd0;
    dmem[12796] = 32'd0;
    dmem[12797] = 32'd0;
    dmem[12798] = 32'd0;
    dmem[12799] = 32'd0;
    dmem[12800] = 32'd0;
    dmem[12801] = 32'd0;
    dmem[12802] = 32'd0;
    dmem[12803] = 32'd0;
    dmem[12804] = 32'd0;
    dmem[12805] = 32'd0;
    dmem[12806] = 32'd0;
    dmem[12807] = 32'd0;
    dmem[12808] = 32'd0;
    dmem[12809] = 32'd0;
    dmem[12810] = 32'd0;
    dmem[12811] = 32'd0;
    dmem[12812] = 32'd0;
    dmem[12813] = 32'd0;
    dmem[12814] = 32'd0;
    dmem[12815] = 32'd0;
    dmem[12816] = 32'd0;
    dmem[12817] = 32'd0;
    dmem[12818] = 32'd0;
    dmem[12819] = 32'd0;
    dmem[12820] = 32'd0;
    dmem[12821] = 32'd0;
    dmem[12822] = 32'd0;
    dmem[12823] = 32'd0;
    dmem[12824] = 32'd0;
    dmem[12825] = 32'd0;
    dmem[12826] = 32'd0;
    dmem[12827] = 32'd0;
    dmem[12828] = 32'd0;
    dmem[12829] = 32'd0;
    dmem[12830] = 32'd0;
    dmem[12831] = 32'd0;
    dmem[12832] = 32'd0;
    dmem[12833] = 32'd0;
    dmem[12834] = 32'd0;
    dmem[12835] = 32'd0;
    dmem[12836] = 32'd0;
    dmem[12837] = 32'd0;
    dmem[12838] = 32'd0;
    dmem[12839] = 32'd0;
    dmem[12840] = 32'd0;
    dmem[12841] = 32'd0;
    dmem[12842] = 32'd0;
    dmem[12843] = 32'd0;
    dmem[12844] = 32'd0;
    dmem[12845] = 32'd0;
    dmem[12846] = 32'd0;
    dmem[12847] = 32'd0;
    dmem[12848] = 32'd0;
    dmem[12849] = 32'd0;
    dmem[12850] = 32'd0;
    dmem[12851] = 32'd0;
    dmem[12852] = 32'd0;
    dmem[12853] = 32'd0;
    dmem[12854] = 32'd0;
    dmem[12855] = 32'd0;
    dmem[12856] = 32'd0;
    dmem[12857] = 32'd0;
    dmem[12858] = 32'd0;
    dmem[12859] = 32'd0;
    dmem[12860] = 32'd0;
    dmem[12861] = 32'd0;
    dmem[12862] = 32'd0;
    dmem[12863] = 32'd0;
    dmem[12864] = 32'd0;
    dmem[12865] = 32'd0;
    dmem[12866] = 32'd0;
    dmem[12867] = 32'd0;
    dmem[12868] = 32'd0;
    dmem[12869] = 32'd0;
    dmem[12870] = 32'd0;
    dmem[12871] = 32'd0;
    dmem[12872] = 32'd0;
    dmem[12873] = 32'd0;
    dmem[12874] = 32'd0;
    dmem[12875] = 32'd0;
    dmem[12876] = 32'd0;
    dmem[12877] = 32'd0;
    dmem[12878] = 32'd0;
    dmem[12879] = 32'd0;
    dmem[12880] = 32'd0;
    dmem[12881] = 32'd0;
    dmem[12882] = 32'd0;
    dmem[12883] = 32'd0;
    dmem[12884] = 32'd0;
    dmem[12885] = 32'd0;
    dmem[12886] = 32'd0;
    dmem[12887] = 32'd0;
    dmem[12888] = 32'd0;
    dmem[12889] = 32'd0;
    dmem[12890] = 32'd0;
    dmem[12891] = 32'd0;
    dmem[12892] = 32'd0;
    dmem[12893] = 32'd0;
    dmem[12894] = 32'd0;
    dmem[12895] = 32'd0;
    dmem[12896] = 32'd0;
    dmem[12897] = 32'd0;
    dmem[12898] = 32'd0;
    dmem[12899] = 32'd0;
    dmem[12900] = 32'd0;
    dmem[12901] = 32'd0;
    dmem[12902] = 32'd0;
    dmem[12903] = 32'd0;
    dmem[12904] = 32'd0;
    dmem[12905] = 32'd0;
    dmem[12906] = 32'd0;
    dmem[12907] = 32'd0;
    dmem[12908] = 32'd0;
    dmem[12909] = 32'd0;
    dmem[12910] = 32'd0;
    dmem[12911] = 32'd0;
    dmem[12912] = 32'd0;
    dmem[12913] = 32'd0;
    dmem[12914] = 32'd0;
    dmem[12915] = 32'd0;
    dmem[12916] = 32'd0;
    dmem[12917] = 32'd0;
    dmem[12918] = 32'd0;
    dmem[12919] = 32'd0;
    dmem[12920] = 32'd0;
    dmem[12921] = 32'd0;
    dmem[12922] = 32'd0;
    dmem[12923] = 32'd0;
    dmem[12924] = 32'd0;
    dmem[12925] = 32'd0;
    dmem[12926] = 32'd0;
    dmem[12927] = 32'd0;
    dmem[12928] = 32'd0;
    dmem[12929] = 32'd0;
    dmem[12930] = 32'd0;
    dmem[12931] = 32'd0;
    dmem[12932] = 32'd0;
    dmem[12933] = 32'd0;
    dmem[12934] = 32'd0;
    dmem[12935] = 32'd0;
    dmem[12936] = 32'd0;
    dmem[12937] = 32'd0;
    dmem[12938] = 32'd0;
    dmem[12939] = 32'd0;
    dmem[12940] = 32'd0;
    dmem[12941] = 32'd0;
    dmem[12942] = 32'd0;
    dmem[12943] = 32'd0;
    dmem[12944] = 32'd0;
    dmem[12945] = 32'd0;
    dmem[12946] = 32'd0;
    dmem[12947] = 32'd0;
    dmem[12948] = 32'd0;
    dmem[12949] = 32'd0;
    dmem[12950] = 32'd0;
    dmem[12951] = 32'd0;
    dmem[12952] = 32'd0;
    dmem[12953] = 32'd0;
    dmem[12954] = 32'd0;
    dmem[12955] = 32'd0;
    dmem[12956] = 32'd0;
    dmem[12957] = 32'd0;
    dmem[12958] = 32'd0;
    dmem[12959] = 32'd0;
    dmem[12960] = 32'd0;
    dmem[12961] = 32'd0;
    dmem[12962] = 32'd0;
    dmem[12963] = 32'd0;
    dmem[12964] = 32'd0;
    dmem[12965] = 32'd0;
    dmem[12966] = 32'd0;
    dmem[12967] = 32'd0;
    dmem[12968] = 32'd0;
    dmem[12969] = 32'd0;
    dmem[12970] = 32'd0;
    dmem[12971] = 32'd0;
    dmem[12972] = 32'd0;
    dmem[12973] = 32'd0;
    dmem[12974] = 32'd0;
    dmem[12975] = 32'd0;
    dmem[12976] = 32'd0;
    dmem[12977] = 32'd0;
    dmem[12978] = 32'd0;
    dmem[12979] = 32'd0;
    dmem[12980] = 32'd0;
    dmem[12981] = 32'd0;
    dmem[12982] = 32'd0;
    dmem[12983] = 32'd0;
    dmem[12984] = 32'd0;
    dmem[12985] = 32'd0;
    dmem[12986] = 32'd0;
    dmem[12987] = 32'd0;
    dmem[12988] = 32'd0;
    dmem[12989] = 32'd0;
    dmem[12990] = 32'd0;
    dmem[12991] = 32'd0;
    dmem[12992] = 32'd0;
    dmem[12993] = 32'd0;
    dmem[12994] = 32'd0;
    dmem[12995] = 32'd0;
    dmem[12996] = 32'd0;
    dmem[12997] = 32'd0;
    dmem[12998] = 32'd0;
    dmem[12999] = 32'd0;
    dmem[13000] = 32'd0;
    dmem[13001] = 32'd0;
    dmem[13002] = 32'd0;
    dmem[13003] = 32'd0;
    dmem[13004] = 32'd0;
    dmem[13005] = 32'd0;
    dmem[13006] = 32'd0;
    dmem[13007] = 32'd0;
    dmem[13008] = 32'd0;
    dmem[13009] = 32'd0;
    dmem[13010] = 32'd0;
    dmem[13011] = 32'd0;
    dmem[13012] = 32'd0;
    dmem[13013] = 32'd0;
    dmem[13014] = 32'd0;
    dmem[13015] = 32'd0;
    dmem[13016] = 32'd0;
    dmem[13017] = 32'd0;
    dmem[13018] = 32'd0;
    dmem[13019] = 32'd0;
    dmem[13020] = 32'd0;
    dmem[13021] = 32'd0;
    dmem[13022] = 32'd0;
    dmem[13023] = 32'd0;
    dmem[13024] = 32'd0;
    dmem[13025] = 32'd0;
    dmem[13026] = 32'd0;
    dmem[13027] = 32'd0;
    dmem[13028] = 32'd0;
    dmem[13029] = 32'd0;
    dmem[13030] = 32'd0;
    dmem[13031] = 32'd0;
    dmem[13032] = 32'd0;
    dmem[13033] = 32'd0;
    dmem[13034] = 32'd0;
    dmem[13035] = 32'd0;
    dmem[13036] = 32'd0;
    dmem[13037] = 32'd0;
    dmem[13038] = 32'd0;
    dmem[13039] = 32'd0;
    dmem[13040] = 32'd0;
    dmem[13041] = 32'd0;
    dmem[13042] = 32'd0;
    dmem[13043] = 32'd0;
    dmem[13044] = 32'd0;
    dmem[13045] = 32'd0;
    dmem[13046] = 32'd0;
    dmem[13047] = 32'd0;
    dmem[13048] = 32'd0;
    dmem[13049] = 32'd0;
    dmem[13050] = 32'd0;
    dmem[13051] = 32'd0;
    dmem[13052] = 32'd0;
    dmem[13053] = 32'd0;
    dmem[13054] = 32'd0;
    dmem[13055] = 32'd0;
    dmem[13056] = 32'd0;
    dmem[13057] = 32'd0;
    dmem[13058] = 32'd0;
    dmem[13059] = 32'd0;
    dmem[13060] = 32'd0;
    dmem[13061] = 32'd0;
    dmem[13062] = 32'd0;
    dmem[13063] = 32'd0;
    dmem[13064] = 32'd0;
    dmem[13065] = 32'd0;
    dmem[13066] = 32'd0;
    dmem[13067] = 32'd0;
    dmem[13068] = 32'd0;
    dmem[13069] = 32'd0;
    dmem[13070] = 32'd0;
    dmem[13071] = 32'd0;
    dmem[13072] = 32'd0;
    dmem[13073] = 32'd0;
    dmem[13074] = 32'd0;
    dmem[13075] = 32'd0;
    dmem[13076] = 32'd0;
    dmem[13077] = 32'd0;
    dmem[13078] = 32'd0;
    dmem[13079] = 32'd0;
    dmem[13080] = 32'd0;
    dmem[13081] = 32'd0;
    dmem[13082] = 32'd0;
    dmem[13083] = 32'd0;
    dmem[13084] = 32'd0;
    dmem[13085] = 32'd0;
    dmem[13086] = 32'd0;
    dmem[13087] = 32'd0;
    dmem[13088] = 32'd0;
    dmem[13089] = 32'd0;
    dmem[13090] = 32'd0;
    dmem[13091] = 32'd0;
    dmem[13092] = 32'd0;
    dmem[13093] = 32'd0;
    dmem[13094] = 32'd0;
    dmem[13095] = 32'd0;
    dmem[13096] = 32'd0;
    dmem[13097] = 32'd0;
    dmem[13098] = 32'd0;
    dmem[13099] = 32'd0;
    dmem[13100] = 32'd0;
    dmem[13101] = 32'd0;
    dmem[13102] = 32'd0;
    dmem[13103] = 32'd0;
    dmem[13104] = 32'd0;
    dmem[13105] = 32'd0;
    dmem[13106] = 32'd0;
    dmem[13107] = 32'd0;
    dmem[13108] = 32'd0;
    dmem[13109] = 32'd0;
    dmem[13110] = 32'd0;
    dmem[13111] = 32'd0;
    dmem[13112] = 32'd0;
    dmem[13113] = 32'd0;
    dmem[13114] = 32'd0;
    dmem[13115] = 32'd0;
    dmem[13116] = 32'd0;
    dmem[13117] = 32'd0;
    dmem[13118] = 32'd0;
    dmem[13119] = 32'd0;
    dmem[13120] = 32'd0;
    dmem[13121] = 32'd0;
    dmem[13122] = 32'd0;
    dmem[13123] = 32'd0;
    dmem[13124] = 32'd0;
    dmem[13125] = 32'd0;
    dmem[13126] = 32'd0;
    dmem[13127] = 32'd0;
    dmem[13128] = 32'd0;
    dmem[13129] = 32'd0;
    dmem[13130] = 32'd0;
    dmem[13131] = 32'd0;
    dmem[13132] = 32'd0;
    dmem[13133] = 32'd0;
    dmem[13134] = 32'd0;
    dmem[13135] = 32'd0;
    dmem[13136] = 32'd0;
    dmem[13137] = 32'd0;
    dmem[13138] = 32'd0;
    dmem[13139] = 32'd0;
    dmem[13140] = 32'd0;
    dmem[13141] = 32'd0;
    dmem[13142] = 32'd0;
    dmem[13143] = 32'd0;
    dmem[13144] = 32'd0;
    dmem[13145] = 32'd0;
    dmem[13146] = 32'd0;
    dmem[13147] = 32'd0;
    dmem[13148] = 32'd0;
    dmem[13149] = 32'd0;
    dmem[13150] = 32'd0;
    dmem[13151] = 32'd0;
    dmem[13152] = 32'd0;
    dmem[13153] = 32'd0;
    dmem[13154] = 32'd0;
    dmem[13155] = 32'd0;
    dmem[13156] = 32'd0;
    dmem[13157] = 32'd0;
    dmem[13158] = 32'd0;
    dmem[13159] = 32'd0;
    dmem[13160] = 32'd0;
    dmem[13161] = 32'd0;
    dmem[13162] = 32'd0;
    dmem[13163] = 32'd0;
    dmem[13164] = 32'd0;
    dmem[13165] = 32'd0;
    dmem[13166] = 32'd0;
    dmem[13167] = 32'd0;
    dmem[13168] = 32'd0;
    dmem[13169] = 32'd0;
    dmem[13170] = 32'd0;
    dmem[13171] = 32'd0;
    dmem[13172] = 32'd0;
    dmem[13173] = 32'd0;
    dmem[13174] = 32'd0;
    dmem[13175] = 32'd0;
    dmem[13176] = 32'd0;
    dmem[13177] = 32'd0;
    dmem[13178] = 32'd0;
    dmem[13179] = 32'd0;
    dmem[13180] = 32'd0;
    dmem[13181] = 32'd0;
    dmem[13182] = 32'd0;
    dmem[13183] = 32'd0;
    dmem[13184] = 32'd0;
    dmem[13185] = 32'd0;
    dmem[13186] = 32'd0;
    dmem[13187] = 32'd0;
    dmem[13188] = 32'd0;
    dmem[13189] = 32'd0;
    dmem[13190] = 32'd0;
    dmem[13191] = 32'd0;
    dmem[13192] = 32'd0;
    dmem[13193] = 32'd0;
    dmem[13194] = 32'd0;
    dmem[13195] = 32'd0;
    dmem[13196] = 32'd0;
    dmem[13197] = 32'd0;
    dmem[13198] = 32'd0;
    dmem[13199] = 32'd0;
    dmem[13200] = 32'd0;
    dmem[13201] = 32'd0;
    dmem[13202] = 32'd0;
    dmem[13203] = 32'd0;
    dmem[13204] = 32'd0;
    dmem[13205] = 32'd0;
    dmem[13206] = 32'd0;
    dmem[13207] = 32'd0;
    dmem[13208] = 32'd0;
    dmem[13209] = 32'd0;
    dmem[13210] = 32'd0;
    dmem[13211] = 32'd0;
    dmem[13212] = 32'd0;
    dmem[13213] = 32'd0;
    dmem[13214] = 32'd0;
    dmem[13215] = 32'd0;
    dmem[13216] = 32'd0;
    dmem[13217] = 32'd0;
    dmem[13218] = 32'd0;
    dmem[13219] = 32'd0;
    dmem[13220] = 32'd0;
    dmem[13221] = 32'd0;
    dmem[13222] = 32'd0;
    dmem[13223] = 32'd0;
    dmem[13224] = 32'd0;
    dmem[13225] = 32'd0;
    dmem[13226] = 32'd0;
    dmem[13227] = 32'd0;
    dmem[13228] = 32'd0;
    dmem[13229] = 32'd0;
    dmem[13230] = 32'd0;
    dmem[13231] = 32'd0;
    dmem[13232] = 32'd0;
    dmem[13233] = 32'd0;
    dmem[13234] = 32'd0;
    dmem[13235] = 32'd0;
    dmem[13236] = 32'd0;
    dmem[13237] = 32'd0;
    dmem[13238] = 32'd0;
    dmem[13239] = 32'd0;
    dmem[13240] = 32'd0;
    dmem[13241] = 32'd0;
    dmem[13242] = 32'd0;
    dmem[13243] = 32'd0;
    dmem[13244] = 32'd0;
    dmem[13245] = 32'd0;
    dmem[13246] = 32'd0;
    dmem[13247] = 32'd0;
    dmem[13248] = 32'd0;
    dmem[13249] = 32'd0;
    dmem[13250] = 32'd0;
    dmem[13251] = 32'd0;
    dmem[13252] = 32'd0;
    dmem[13253] = 32'd0;
    dmem[13254] = 32'd0;
    dmem[13255] = 32'd0;
    dmem[13256] = 32'd0;
    dmem[13257] = 32'd0;
    dmem[13258] = 32'd0;
    dmem[13259] = 32'd0;
    dmem[13260] = 32'd0;
    dmem[13261] = 32'd0;
    dmem[13262] = 32'd0;
    dmem[13263] = 32'd0;
    dmem[13264] = 32'd0;
    dmem[13265] = 32'd0;
    dmem[13266] = 32'd0;
    dmem[13267] = 32'd0;
    dmem[13268] = 32'd0;
    dmem[13269] = 32'd0;
    dmem[13270] = 32'd0;
    dmem[13271] = 32'd0;
    dmem[13272] = 32'd0;
    dmem[13273] = 32'd0;
    dmem[13274] = 32'd0;
    dmem[13275] = 32'd0;
    dmem[13276] = 32'd0;
    dmem[13277] = 32'd0;
    dmem[13278] = 32'd0;
    dmem[13279] = 32'd0;
    dmem[13280] = 32'd0;
    dmem[13281] = 32'd0;
    dmem[13282] = 32'd0;
    dmem[13283] = 32'd0;
    dmem[13284] = 32'd0;
    dmem[13285] = 32'd0;
    dmem[13286] = 32'd0;
    dmem[13287] = 32'd0;
    dmem[13288] = 32'd0;
    dmem[13289] = 32'd0;
    dmem[13290] = 32'd0;
    dmem[13291] = 32'd0;
    dmem[13292] = 32'd0;
    dmem[13293] = 32'd0;
    dmem[13294] = 32'd0;
    dmem[13295] = 32'd0;
    dmem[13296] = 32'd0;
    dmem[13297] = 32'd0;
    dmem[13298] = 32'd0;
    dmem[13299] = 32'd0;
    dmem[13300] = 32'd0;
    dmem[13301] = 32'd0;
    dmem[13302] = 32'd0;
    dmem[13303] = 32'd0;
    dmem[13304] = 32'd0;
    dmem[13305] = 32'd0;
    dmem[13306] = 32'd0;
    dmem[13307] = 32'd0;
    dmem[13308] = 32'd0;
    dmem[13309] = 32'd0;
    dmem[13310] = 32'd0;
    dmem[13311] = 32'd0;
    dmem[13312] = 32'd0;
    dmem[13313] = 32'd0;
    dmem[13314] = 32'd0;
    dmem[13315] = 32'd0;
    dmem[13316] = 32'd0;
    dmem[13317] = 32'd0;
    dmem[13318] = 32'd0;
    dmem[13319] = 32'd0;
    dmem[13320] = 32'd0;
    dmem[13321] = 32'd0;
    dmem[13322] = 32'd0;
    dmem[13323] = 32'd0;
    dmem[13324] = 32'd0;
    dmem[13325] = 32'd0;
    dmem[13326] = 32'd0;
    dmem[13327] = 32'd0;
    dmem[13328] = 32'd0;
    dmem[13329] = 32'd0;
    dmem[13330] = 32'd0;
    dmem[13331] = 32'd0;
    dmem[13332] = 32'd0;
    dmem[13333] = 32'd0;
    dmem[13334] = 32'd0;
    dmem[13335] = 32'd0;
    dmem[13336] = 32'd0;
    dmem[13337] = 32'd0;
    dmem[13338] = 32'd0;
    dmem[13339] = 32'd0;
    dmem[13340] = 32'd0;
    dmem[13341] = 32'd0;
    dmem[13342] = 32'd0;
    dmem[13343] = 32'd0;
    dmem[13344] = 32'd0;
    dmem[13345] = 32'd0;
    dmem[13346] = 32'd0;
    dmem[13347] = 32'd0;
    dmem[13348] = 32'd0;
    dmem[13349] = 32'd0;
    dmem[13350] = 32'd0;
    dmem[13351] = 32'd0;
    dmem[13352] = 32'd0;
    dmem[13353] = 32'd0;
    dmem[13354] = 32'd0;
    dmem[13355] = 32'd0;
    dmem[13356] = 32'd0;
    dmem[13357] = 32'd0;
    dmem[13358] = 32'd0;
    dmem[13359] = 32'd0;
    dmem[13360] = 32'd0;
    dmem[13361] = 32'd0;
    dmem[13362] = 32'd0;
    dmem[13363] = 32'd0;
    dmem[13364] = 32'd0;
    dmem[13365] = 32'd0;
    dmem[13366] = 32'd0;
    dmem[13367] = 32'd0;
    dmem[13368] = 32'd0;
    dmem[13369] = 32'd0;
    dmem[13370] = 32'd0;
    dmem[13371] = 32'd0;
    dmem[13372] = 32'd0;
    dmem[13373] = 32'd0;
    dmem[13374] = 32'd0;
    dmem[13375] = 32'd0;
    dmem[13376] = 32'd0;
    dmem[13377] = 32'd0;
    dmem[13378] = 32'd0;
    dmem[13379] = 32'd0;
    dmem[13380] = 32'd0;
    dmem[13381] = 32'd0;
    dmem[13382] = 32'd0;
    dmem[13383] = 32'd0;
    dmem[13384] = 32'd0;
    dmem[13385] = 32'd0;
    dmem[13386] = 32'd0;
    dmem[13387] = 32'd0;
    dmem[13388] = 32'd0;
    dmem[13389] = 32'd0;
    dmem[13390] = 32'd0;
    dmem[13391] = 32'd0;
    dmem[13392] = 32'd0;
    dmem[13393] = 32'd0;
    dmem[13394] = 32'd0;
    dmem[13395] = 32'd0;
    dmem[13396] = 32'd0;
    dmem[13397] = 32'd0;
    dmem[13398] = 32'd0;
    dmem[13399] = 32'd0;
    dmem[13400] = 32'd0;
    dmem[13401] = 32'd0;
    dmem[13402] = 32'd0;
    dmem[13403] = 32'd0;
    dmem[13404] = 32'd0;
    dmem[13405] = 32'd0;
    dmem[13406] = 32'd0;
    dmem[13407] = 32'd0;
    dmem[13408] = 32'd0;
    dmem[13409] = 32'd0;
    dmem[13410] = 32'd0;
    dmem[13411] = 32'd0;
    dmem[13412] = 32'd0;
    dmem[13413] = 32'd0;
    dmem[13414] = 32'd0;
    dmem[13415] = 32'd0;
    dmem[13416] = 32'd0;
    dmem[13417] = 32'd0;
    dmem[13418] = 32'd0;
    dmem[13419] = 32'd0;
    dmem[13420] = 32'd0;
    dmem[13421] = 32'd0;
    dmem[13422] = 32'd0;
    dmem[13423] = 32'd0;
    dmem[13424] = 32'd0;
    dmem[13425] = 32'd0;
    dmem[13426] = 32'd0;
    dmem[13427] = 32'd0;
    dmem[13428] = 32'd0;
    dmem[13429] = 32'd0;
    dmem[13430] = 32'd0;
    dmem[13431] = 32'd0;
    dmem[13432] = 32'd0;
    dmem[13433] = 32'd0;
    dmem[13434] = 32'd0;
    dmem[13435] = 32'd0;
    dmem[13436] = 32'd0;
    dmem[13437] = 32'd0;
    dmem[13438] = 32'd0;
    dmem[13439] = 32'd0;
    dmem[13440] = 32'd0;
    dmem[13441] = 32'd0;
    dmem[13442] = 32'd0;
    dmem[13443] = 32'd0;
    dmem[13444] = 32'd0;
    dmem[13445] = 32'd0;
    dmem[13446] = 32'd0;
    dmem[13447] = 32'd0;
    dmem[13448] = 32'd0;
    dmem[13449] = 32'd0;
    dmem[13450] = 32'd0;
    dmem[13451] = 32'd0;
    dmem[13452] = 32'd0;
    dmem[13453] = 32'd0;
    dmem[13454] = 32'd0;
    dmem[13455] = 32'd0;
    dmem[13456] = 32'd0;
    dmem[13457] = 32'd0;
    dmem[13458] = 32'd0;
    dmem[13459] = 32'd0;
    dmem[13460] = 32'd0;
    dmem[13461] = 32'd0;
    dmem[13462] = 32'd0;
    dmem[13463] = 32'd0;
    dmem[13464] = 32'd0;
    dmem[13465] = 32'd0;
    dmem[13466] = 32'd0;
    dmem[13467] = 32'd0;
    dmem[13468] = 32'd0;
    dmem[13469] = 32'd0;
    dmem[13470] = 32'd0;
    dmem[13471] = 32'd0;
    dmem[13472] = 32'd0;
    dmem[13473] = 32'd0;
    dmem[13474] = 32'd0;
    dmem[13475] = 32'd0;
    dmem[13476] = 32'd0;
    dmem[13477] = 32'd0;
    dmem[13478] = 32'd0;
    dmem[13479] = 32'd0;
    dmem[13480] = 32'd0;
    dmem[13481] = 32'd0;
    dmem[13482] = 32'd0;
    dmem[13483] = 32'd0;
    dmem[13484] = 32'd0;
    dmem[13485] = 32'd0;
    dmem[13486] = 32'd0;
    dmem[13487] = 32'd0;
    dmem[13488] = 32'd0;
    dmem[13489] = 32'd0;
    dmem[13490] = 32'd0;
    dmem[13491] = 32'd0;
    dmem[13492] = 32'd0;
    dmem[13493] = 32'd0;
    dmem[13494] = 32'd0;
    dmem[13495] = 32'd0;
    dmem[13496] = 32'd0;
    dmem[13497] = 32'd0;
    dmem[13498] = 32'd0;
    dmem[13499] = 32'd0;
    dmem[13500] = 32'd0;
    dmem[13501] = 32'd0;
    dmem[13502] = 32'd0;
    dmem[13503] = 32'd0;
    dmem[13504] = 32'd0;
    dmem[13505] = 32'd0;
    dmem[13506] = 32'd0;
    dmem[13507] = 32'd0;
    dmem[13508] = 32'd0;
    dmem[13509] = 32'd0;
    dmem[13510] = 32'd0;
    dmem[13511] = 32'd0;
    dmem[13512] = 32'd0;
    dmem[13513] = 32'd0;
    dmem[13514] = 32'd0;
    dmem[13515] = 32'd0;
    dmem[13516] = 32'd0;
    dmem[13517] = 32'd0;
    dmem[13518] = 32'd0;
    dmem[13519] = 32'd0;
    dmem[13520] = 32'd0;
    dmem[13521] = 32'd0;
    dmem[13522] = 32'd0;
    dmem[13523] = 32'd0;
    dmem[13524] = 32'd0;
    dmem[13525] = 32'd0;
    dmem[13526] = 32'd0;
    dmem[13527] = 32'd0;
    dmem[13528] = 32'd0;
    dmem[13529] = 32'd0;
    dmem[13530] = 32'd0;
    dmem[13531] = 32'd0;
    dmem[13532] = 32'd0;
    dmem[13533] = 32'd0;
    dmem[13534] = 32'd0;
    dmem[13535] = 32'd0;
    dmem[13536] = 32'd0;
    dmem[13537] = 32'd0;
    dmem[13538] = 32'd0;
    dmem[13539] = 32'd0;
    dmem[13540] = 32'd0;
    dmem[13541] = 32'd0;
    dmem[13542] = 32'd0;
    dmem[13543] = 32'd0;
    dmem[13544] = 32'd0;
    dmem[13545] = 32'd0;
    dmem[13546] = 32'd0;
    dmem[13547] = 32'd0;
    dmem[13548] = 32'd0;
    dmem[13549] = 32'd0;
    dmem[13550] = 32'd0;
    dmem[13551] = 32'd0;
    dmem[13552] = 32'd0;
    dmem[13553] = 32'd0;
    dmem[13554] = 32'd0;
    dmem[13555] = 32'd0;
    dmem[13556] = 32'd0;
    dmem[13557] = 32'd0;
    dmem[13558] = 32'd0;
    dmem[13559] = 32'd0;
    dmem[13560] = 32'd0;
    dmem[13561] = 32'd0;
    dmem[13562] = 32'd0;
    dmem[13563] = 32'd0;
    dmem[13564] = 32'd0;
    dmem[13565] = 32'd0;
    dmem[13566] = 32'd0;
    dmem[13567] = 32'd0;
    dmem[13568] = 32'd0;
    dmem[13569] = 32'd0;
    dmem[13570] = 32'd0;
    dmem[13571] = 32'd0;
    dmem[13572] = 32'd0;
    dmem[13573] = 32'd0;
    dmem[13574] = 32'd0;
    dmem[13575] = 32'd0;
    dmem[13576] = 32'd0;
    dmem[13577] = 32'd0;
    dmem[13578] = 32'd0;
    dmem[13579] = 32'd0;
    dmem[13580] = 32'd0;
    dmem[13581] = 32'd0;
    dmem[13582] = 32'd0;
    dmem[13583] = 32'd0;
    dmem[13584] = 32'd0;
    dmem[13585] = 32'd0;
    dmem[13586] = 32'd0;
    dmem[13587] = 32'd0;
    dmem[13588] = 32'd0;
    dmem[13589] = 32'd0;
    dmem[13590] = 32'd0;
    dmem[13591] = 32'd0;
    dmem[13592] = 32'd0;
    dmem[13593] = 32'd0;
    dmem[13594] = 32'd0;
    dmem[13595] = 32'd0;
    dmem[13596] = 32'd0;
    dmem[13597] = 32'd0;
    dmem[13598] = 32'd0;
    dmem[13599] = 32'd0;
    dmem[13600] = 32'd0;
    dmem[13601] = 32'd0;
    dmem[13602] = 32'd0;
    dmem[13603] = 32'd0;
    dmem[13604] = 32'd0;
    dmem[13605] = 32'd0;
    dmem[13606] = 32'd0;
    dmem[13607] = 32'd0;
    dmem[13608] = 32'd0;
    dmem[13609] = 32'd0;
    dmem[13610] = 32'd0;
    dmem[13611] = 32'd0;
    dmem[13612] = 32'd0;
    dmem[13613] = 32'd0;
    dmem[13614] = 32'd0;
    dmem[13615] = 32'd0;
    dmem[13616] = 32'd0;
    dmem[13617] = 32'd0;
    dmem[13618] = 32'd0;
    dmem[13619] = 32'd0;
    dmem[13620] = 32'd0;
    dmem[13621] = 32'd0;
    dmem[13622] = 32'd0;
    dmem[13623] = 32'd0;
    dmem[13624] = 32'd0;
    dmem[13625] = 32'd0;
    dmem[13626] = 32'd0;
    dmem[13627] = 32'd0;
    dmem[13628] = 32'd0;
    dmem[13629] = 32'd0;
    dmem[13630] = 32'd0;
    dmem[13631] = 32'd0;
    dmem[13632] = 32'd0;
    dmem[13633] = 32'd0;
    dmem[13634] = 32'd0;
    dmem[13635] = 32'd0;
    dmem[13636] = 32'd0;
    dmem[13637] = 32'd0;
    dmem[13638] = 32'd0;
    dmem[13639] = 32'd0;
    dmem[13640] = 32'd0;
    dmem[13641] = 32'd0;
    dmem[13642] = 32'd0;
    dmem[13643] = 32'd0;
    dmem[13644] = 32'd0;
    dmem[13645] = 32'd0;
    dmem[13646] = 32'd0;
    dmem[13647] = 32'd0;
    dmem[13648] = 32'd0;
    dmem[13649] = 32'd0;
    dmem[13650] = 32'd0;
    dmem[13651] = 32'd0;
    dmem[13652] = 32'd0;
    dmem[13653] = 32'd0;
    dmem[13654] = 32'd0;
    dmem[13655] = 32'd0;
    dmem[13656] = 32'd0;
    dmem[13657] = 32'd0;
    dmem[13658] = 32'd0;
    dmem[13659] = 32'd0;
    dmem[13660] = 32'd0;
    dmem[13661] = 32'd0;
    dmem[13662] = 32'd0;
    dmem[13663] = 32'd0;
    dmem[13664] = 32'd0;
    dmem[13665] = 32'd0;
    dmem[13666] = 32'd0;
    dmem[13667] = 32'd0;
    dmem[13668] = 32'd0;
    dmem[13669] = 32'd0;
    dmem[13670] = 32'd0;
    dmem[13671] = 32'd0;
    dmem[13672] = 32'd0;
    dmem[13673] = 32'd0;
    dmem[13674] = 32'd0;
    dmem[13675] = 32'd0;
    dmem[13676] = 32'd0;
    dmem[13677] = 32'd0;
    dmem[13678] = 32'd0;
    dmem[13679] = 32'd0;
    dmem[13680] = 32'd0;
    dmem[13681] = 32'd0;
    dmem[13682] = 32'd0;
    dmem[13683] = 32'd0;
    dmem[13684] = 32'd0;
    dmem[13685] = 32'd0;
    dmem[13686] = 32'd0;
    dmem[13687] = 32'd0;
    dmem[13688] = 32'd0;
    dmem[13689] = 32'd0;
    dmem[13690] = 32'd0;
    dmem[13691] = 32'd0;
    dmem[13692] = 32'd0;
    dmem[13693] = 32'd0;
    dmem[13694] = 32'd0;
    dmem[13695] = 32'd0;
    dmem[13696] = 32'd0;
    dmem[13697] = 32'd0;
    dmem[13698] = 32'd0;
    dmem[13699] = 32'd0;
    dmem[13700] = 32'd0;
    dmem[13701] = 32'd0;
    dmem[13702] = 32'd0;
    dmem[13703] = 32'd0;
    dmem[13704] = 32'd0;
    dmem[13705] = 32'd0;
    dmem[13706] = 32'd0;
    dmem[13707] = 32'd0;
    dmem[13708] = 32'd0;
    dmem[13709] = 32'd0;
    dmem[13710] = 32'd0;
    dmem[13711] = 32'd0;
    dmem[13712] = 32'd0;
    dmem[13713] = 32'd0;
    dmem[13714] = 32'd0;
    dmem[13715] = 32'd0;
    dmem[13716] = 32'd0;
    dmem[13717] = 32'd0;
    dmem[13718] = 32'd0;
    dmem[13719] = 32'd0;
    dmem[13720] = 32'd0;
    dmem[13721] = 32'd0;
    dmem[13722] = 32'd0;
    dmem[13723] = 32'd0;
    dmem[13724] = 32'd0;
    dmem[13725] = 32'd0;
    dmem[13726] = 32'd0;
    dmem[13727] = 32'd0;
    dmem[13728] = 32'd0;
    dmem[13729] = 32'd0;
    dmem[13730] = 32'd0;
    dmem[13731] = 32'd0;
    dmem[13732] = 32'd0;
    dmem[13733] = 32'd0;
    dmem[13734] = 32'd0;
    dmem[13735] = 32'd0;
    dmem[13736] = 32'd0;
    dmem[13737] = 32'd0;
    dmem[13738] = 32'd0;
    dmem[13739] = 32'd0;
    dmem[13740] = 32'd0;
    dmem[13741] = 32'd0;
    dmem[13742] = 32'd0;
    dmem[13743] = 32'd0;
    dmem[13744] = 32'd0;
    dmem[13745] = 32'd0;
    dmem[13746] = 32'd0;
    dmem[13747] = 32'd0;
    dmem[13748] = 32'd0;
    dmem[13749] = 32'd0;
    dmem[13750] = 32'd0;
    dmem[13751] = 32'd0;
    dmem[13752] = 32'd0;
    dmem[13753] = 32'd0;
    dmem[13754] = 32'd0;
    dmem[13755] = 32'd0;
    dmem[13756] = 32'd0;
    dmem[13757] = 32'd0;
    dmem[13758] = 32'd0;
    dmem[13759] = 32'd0;
    dmem[13760] = 32'd0;
    dmem[13761] = 32'd0;
    dmem[13762] = 32'd0;
    dmem[13763] = 32'd0;
    dmem[13764] = 32'd0;
    dmem[13765] = 32'd0;
    dmem[13766] = 32'd0;
    dmem[13767] = 32'd0;
    dmem[13768] = 32'd0;
    dmem[13769] = 32'd0;
    dmem[13770] = 32'd0;
    dmem[13771] = 32'd0;
    dmem[13772] = 32'd0;
    dmem[13773] = 32'd0;
    dmem[13774] = 32'd0;
    dmem[13775] = 32'd0;
    dmem[13776] = 32'd0;
    dmem[13777] = 32'd0;
    dmem[13778] = 32'd0;
    dmem[13779] = 32'd0;
    dmem[13780] = 32'd0;
    dmem[13781] = 32'd0;
    dmem[13782] = 32'd0;
    dmem[13783] = 32'd0;
    dmem[13784] = 32'd0;
    dmem[13785] = 32'd0;
    dmem[13786] = 32'd0;
    dmem[13787] = 32'd0;
    dmem[13788] = 32'd0;
    dmem[13789] = 32'd0;
    dmem[13790] = 32'd0;
    dmem[13791] = 32'd0;
    dmem[13792] = 32'd0;
    dmem[13793] = 32'd0;
    dmem[13794] = 32'd0;
    dmem[13795] = 32'd0;
    dmem[13796] = 32'd0;
    dmem[13797] = 32'd0;
    dmem[13798] = 32'd0;
    dmem[13799] = 32'd0;
    dmem[13800] = 32'd0;
    dmem[13801] = 32'd0;
    dmem[13802] = 32'd0;
    dmem[13803] = 32'd0;
    dmem[13804] = 32'd0;
    dmem[13805] = 32'd0;
    dmem[13806] = 32'd0;
    dmem[13807] = 32'd0;
    dmem[13808] = 32'd0;
    dmem[13809] = 32'd0;
    dmem[13810] = 32'd0;
    dmem[13811] = 32'd0;
    dmem[13812] = 32'd0;
    dmem[13813] = 32'd0;
    dmem[13814] = 32'd0;
    dmem[13815] = 32'd0;
    dmem[13816] = 32'd0;
    dmem[13817] = 32'd0;
    dmem[13818] = 32'd0;
    dmem[13819] = 32'd0;
    dmem[13820] = 32'd0;
    dmem[13821] = 32'd0;
    dmem[13822] = 32'd0;
    dmem[13823] = 32'd0;
    dmem[13824] = 32'd0;
    dmem[13825] = 32'd0;
    dmem[13826] = 32'd0;
    dmem[13827] = 32'd0;
    dmem[13828] = 32'd0;
    dmem[13829] = 32'd0;
    dmem[13830] = 32'd0;
    dmem[13831] = 32'd0;
    dmem[13832] = 32'd0;
    dmem[13833] = 32'd0;
    dmem[13834] = 32'd0;
    dmem[13835] = 32'd0;
    dmem[13836] = 32'd0;
    dmem[13837] = 32'd0;
    dmem[13838] = 32'd0;
    dmem[13839] = 32'd0;
    dmem[13840] = 32'd0;
    dmem[13841] = 32'd0;
    dmem[13842] = 32'd0;
    dmem[13843] = 32'd0;
    dmem[13844] = 32'd0;
    dmem[13845] = 32'd0;
    dmem[13846] = 32'd0;
    dmem[13847] = 32'd0;
    dmem[13848] = 32'd0;
    dmem[13849] = 32'd0;
    dmem[13850] = 32'd0;
    dmem[13851] = 32'd0;
    dmem[13852] = 32'd0;
    dmem[13853] = 32'd0;
    dmem[13854] = 32'd0;
    dmem[13855] = 32'd0;
    dmem[13856] = 32'd0;
    dmem[13857] = 32'd0;
    dmem[13858] = 32'd0;
    dmem[13859] = 32'd0;
    dmem[13860] = 32'd0;
    dmem[13861] = 32'd0;
    dmem[13862] = 32'd0;
    dmem[13863] = 32'd0;
    dmem[13864] = 32'd0;
    dmem[13865] = 32'd0;
    dmem[13866] = 32'd0;
    dmem[13867] = 32'd0;
    dmem[13868] = 32'd0;
    dmem[13869] = 32'd0;
    dmem[13870] = 32'd0;
    dmem[13871] = 32'd0;
    dmem[13872] = 32'd0;
    dmem[13873] = 32'd0;
    dmem[13874] = 32'd0;
    dmem[13875] = 32'd0;
    dmem[13876] = 32'd0;
    dmem[13877] = 32'd0;
    dmem[13878] = 32'd0;
    dmem[13879] = 32'd0;
    dmem[13880] = 32'd0;
    dmem[13881] = 32'd0;
    dmem[13882] = 32'd0;
    dmem[13883] = 32'd0;
    dmem[13884] = 32'd0;
    dmem[13885] = 32'd0;
    dmem[13886] = 32'd0;
    dmem[13887] = 32'd0;
    dmem[13888] = 32'd0;
    dmem[13889] = 32'd0;
    dmem[13890] = 32'd0;
    dmem[13891] = 32'd0;
    dmem[13892] = 32'd0;
    dmem[13893] = 32'd0;
    dmem[13894] = 32'd0;
    dmem[13895] = 32'd0;
    dmem[13896] = 32'd0;
    dmem[13897] = 32'd0;
    dmem[13898] = 32'd0;
    dmem[13899] = 32'd0;
    dmem[13900] = 32'd0;
    dmem[13901] = 32'd0;
    dmem[13902] = 32'd0;
    dmem[13903] = 32'd0;
    dmem[13904] = 32'd0;
    dmem[13905] = 32'd0;
    dmem[13906] = 32'd0;
    dmem[13907] = 32'd0;
    dmem[13908] = 32'd0;
    dmem[13909] = 32'd0;
    dmem[13910] = 32'd0;
    dmem[13911] = 32'd0;
    dmem[13912] = 32'd0;
    dmem[13913] = 32'd0;
    dmem[13914] = 32'd0;
    dmem[13915] = 32'd0;
    dmem[13916] = 32'd0;
    dmem[13917] = 32'd0;
    dmem[13918] = 32'd0;
    dmem[13919] = 32'd0;
    dmem[13920] = 32'd0;
    dmem[13921] = 32'd0;
    dmem[13922] = 32'd0;
    dmem[13923] = 32'd0;
    dmem[13924] = 32'd0;
    dmem[13925] = 32'd0;
    dmem[13926] = 32'd0;
    dmem[13927] = 32'd0;
    dmem[13928] = 32'd0;
    dmem[13929] = 32'd0;
    dmem[13930] = 32'd0;
    dmem[13931] = 32'd0;
    dmem[13932] = 32'd0;
    dmem[13933] = 32'd0;
    dmem[13934] = 32'd0;
    dmem[13935] = 32'd0;
    dmem[13936] = 32'd0;
    dmem[13937] = 32'd0;
    dmem[13938] = 32'd0;
    dmem[13939] = 32'd0;
    dmem[13940] = 32'd0;
    dmem[13941] = 32'd0;
    dmem[13942] = 32'd0;
    dmem[13943] = 32'd0;
    dmem[13944] = 32'd0;
    dmem[13945] = 32'd0;
    dmem[13946] = 32'd0;
    dmem[13947] = 32'd0;
    dmem[13948] = 32'd0;
    dmem[13949] = 32'd0;
    dmem[13950] = 32'd0;
    dmem[13951] = 32'd0;
    dmem[13952] = 32'd0;
    dmem[13953] = 32'd0;
    dmem[13954] = 32'd0;
    dmem[13955] = 32'd0;
    dmem[13956] = 32'd0;
    dmem[13957] = 32'd0;
    dmem[13958] = 32'd0;
    dmem[13959] = 32'd0;
    dmem[13960] = 32'd0;
    dmem[13961] = 32'd0;
    dmem[13962] = 32'd0;
    dmem[13963] = 32'd0;
    dmem[13964] = 32'd0;
    dmem[13965] = 32'd0;
    dmem[13966] = 32'd0;
    dmem[13967] = 32'd0;
    dmem[13968] = 32'd0;
    dmem[13969] = 32'd0;
    dmem[13970] = 32'd0;
    dmem[13971] = 32'd0;
    dmem[13972] = 32'd0;
    dmem[13973] = 32'd0;
    dmem[13974] = 32'd0;
    dmem[13975] = 32'd0;
    dmem[13976] = 32'd0;
    dmem[13977] = 32'd0;
    dmem[13978] = 32'd0;
    dmem[13979] = 32'd0;
    dmem[13980] = 32'd0;
    dmem[13981] = 32'd0;
    dmem[13982] = 32'd0;
    dmem[13983] = 32'd0;
    dmem[13984] = 32'd0;
    dmem[13985] = 32'd0;
    dmem[13986] = 32'd0;
    dmem[13987] = 32'd0;
    dmem[13988] = 32'd0;
    dmem[13989] = 32'd0;
    dmem[13990] = 32'd0;
    dmem[13991] = 32'd0;
    dmem[13992] = 32'd0;
    dmem[13993] = 32'd0;
    dmem[13994] = 32'd0;
    dmem[13995] = 32'd0;
    dmem[13996] = 32'd0;
    dmem[13997] = 32'd0;
    dmem[13998] = 32'd0;
    dmem[13999] = 32'd0;
    dmem[14000] = 32'd0;
    dmem[14001] = 32'd0;
    dmem[14002] = 32'd0;
    dmem[14003] = 32'd0;
    dmem[14004] = 32'd0;
    dmem[14005] = 32'd0;
    dmem[14006] = 32'd0;
    dmem[14007] = 32'd0;
    dmem[14008] = 32'd0;
    dmem[14009] = 32'd0;
    dmem[14010] = 32'd0;
    dmem[14011] = 32'd0;
    dmem[14012] = 32'd0;
    dmem[14013] = 32'd0;
    dmem[14014] = 32'd0;
    dmem[14015] = 32'd0;
    dmem[14016] = 32'd0;
    dmem[14017] = 32'd0;
    dmem[14018] = 32'd0;
    dmem[14019] = 32'd0;
    dmem[14020] = 32'd0;
    dmem[14021] = 32'd0;
    dmem[14022] = 32'd0;
    dmem[14023] = 32'd0;
    dmem[14024] = 32'd0;
    dmem[14025] = 32'd0;
    dmem[14026] = 32'd0;
    dmem[14027] = 32'd0;
    dmem[14028] = 32'd0;
    dmem[14029] = 32'd0;
    dmem[14030] = 32'd0;
    dmem[14031] = 32'd0;
    dmem[14032] = 32'd0;
    dmem[14033] = 32'd0;
    dmem[14034] = 32'd0;
    dmem[14035] = 32'd0;
    dmem[14036] = 32'd0;
    dmem[14037] = 32'd0;
    dmem[14038] = 32'd0;
    dmem[14039] = 32'd0;
    dmem[14040] = 32'd0;
    dmem[14041] = 32'd0;
    dmem[14042] = 32'd0;
    dmem[14043] = 32'd0;
    dmem[14044] = 32'd0;
    dmem[14045] = 32'd0;
    dmem[14046] = 32'd0;
    dmem[14047] = 32'd0;
    dmem[14048] = 32'd0;
    dmem[14049] = 32'd0;
    dmem[14050] = 32'd0;
    dmem[14051] = 32'd0;
    dmem[14052] = 32'd0;
    dmem[14053] = 32'd0;
    dmem[14054] = 32'd0;
    dmem[14055] = 32'd0;
    dmem[14056] = 32'd0;
    dmem[14057] = 32'd0;
    dmem[14058] = 32'd0;
    dmem[14059] = 32'd0;
    dmem[14060] = 32'd0;
    dmem[14061] = 32'd0;
    dmem[14062] = 32'd0;
    dmem[14063] = 32'd0;
    dmem[14064] = 32'd0;
    dmem[14065] = 32'd0;
    dmem[14066] = 32'd0;
    dmem[14067] = 32'd0;
    dmem[14068] = 32'd0;
    dmem[14069] = 32'd0;
    dmem[14070] = 32'd0;
    dmem[14071] = 32'd0;
    dmem[14072] = 32'd0;
    dmem[14073] = 32'd0;
    dmem[14074] = 32'd0;
    dmem[14075] = 32'd0;
    dmem[14076] = 32'd0;
    dmem[14077] = 32'd0;
    dmem[14078] = 32'd0;
    dmem[14079] = 32'd0;
    dmem[14080] = 32'd0;
    dmem[14081] = 32'd0;
    dmem[14082] = 32'd0;
    dmem[14083] = 32'd0;
    dmem[14084] = 32'd0;
    dmem[14085] = 32'd0;
    dmem[14086] = 32'd0;
    dmem[14087] = 32'd0;
    dmem[14088] = 32'd0;
    dmem[14089] = 32'd0;
    dmem[14090] = 32'd0;
    dmem[14091] = 32'd0;
    dmem[14092] = 32'd0;
    dmem[14093] = 32'd0;
    dmem[14094] = 32'd0;
    dmem[14095] = 32'd0;
    dmem[14096] = 32'd0;
    dmem[14097] = 32'd0;
    dmem[14098] = 32'd0;
    dmem[14099] = 32'd0;
    dmem[14100] = 32'd0;
    dmem[14101] = 32'd0;
    dmem[14102] = 32'd0;
    dmem[14103] = 32'd0;
    dmem[14104] = 32'd0;
    dmem[14105] = 32'd0;
    dmem[14106] = 32'd0;
    dmem[14107] = 32'd0;
    dmem[14108] = 32'd0;
    dmem[14109] = 32'd0;
    dmem[14110] = 32'd0;
    dmem[14111] = 32'd0;
    dmem[14112] = 32'd0;
    dmem[14113] = 32'd0;
    dmem[14114] = 32'd0;
    dmem[14115] = 32'd0;
    dmem[14116] = 32'd0;
    dmem[14117] = 32'd0;
    dmem[14118] = 32'd0;
    dmem[14119] = 32'd0;
    dmem[14120] = 32'd0;
    dmem[14121] = 32'd0;
    dmem[14122] = 32'd0;
    dmem[14123] = 32'd0;
    dmem[14124] = 32'd0;
    dmem[14125] = 32'd0;
    dmem[14126] = 32'd0;
    dmem[14127] = 32'd0;
    dmem[14128] = 32'd0;
    dmem[14129] = 32'd0;
    dmem[14130] = 32'd0;
    dmem[14131] = 32'd0;
    dmem[14132] = 32'd0;
    dmem[14133] = 32'd0;
    dmem[14134] = 32'd0;
    dmem[14135] = 32'd0;
    dmem[14136] = 32'd0;
    dmem[14137] = 32'd0;
    dmem[14138] = 32'd0;
    dmem[14139] = 32'd0;
    dmem[14140] = 32'd0;
    dmem[14141] = 32'd0;
    dmem[14142] = 32'd0;
    dmem[14143] = 32'd0;
    dmem[14144] = 32'd0;
    dmem[14145] = 32'd0;
    dmem[14146] = 32'd0;
    dmem[14147] = 32'd0;
    dmem[14148] = 32'd0;
    dmem[14149] = 32'd0;
    dmem[14150] = 32'd0;
    dmem[14151] = 32'd0;
    dmem[14152] = 32'd0;
    dmem[14153] = 32'd0;
    dmem[14154] = 32'd0;
    dmem[14155] = 32'd0;
    dmem[14156] = 32'd0;
    dmem[14157] = 32'd0;
    dmem[14158] = 32'd0;
    dmem[14159] = 32'd0;
    dmem[14160] = 32'd0;
    dmem[14161] = 32'd0;
    dmem[14162] = 32'd0;
    dmem[14163] = 32'd0;
    dmem[14164] = 32'd0;
    dmem[14165] = 32'd0;
    dmem[14166] = 32'd0;
    dmem[14167] = 32'd0;
    dmem[14168] = 32'd0;
    dmem[14169] = 32'd0;
    dmem[14170] = 32'd0;
    dmem[14171] = 32'd0;
    dmem[14172] = 32'd0;
    dmem[14173] = 32'd0;
    dmem[14174] = 32'd0;
    dmem[14175] = 32'd0;
    dmem[14176] = 32'd0;
    dmem[14177] = 32'd0;
    dmem[14178] = 32'd0;
    dmem[14179] = 32'd0;
    dmem[14180] = 32'd0;
    dmem[14181] = 32'd0;
    dmem[14182] = 32'd0;
    dmem[14183] = 32'd0;
    dmem[14184] = 32'd0;
    dmem[14185] = 32'd0;
    dmem[14186] = 32'd0;
    dmem[14187] = 32'd0;
    dmem[14188] = 32'd0;
    dmem[14189] = 32'd0;
    dmem[14190] = 32'd0;
    dmem[14191] = 32'd0;
    dmem[14192] = 32'd0;
    dmem[14193] = 32'd0;
    dmem[14194] = 32'd0;
    dmem[14195] = 32'd0;
    dmem[14196] = 32'd0;
    dmem[14197] = 32'd0;
    dmem[14198] = 32'd0;
    dmem[14199] = 32'd0;
    dmem[14200] = 32'd0;
    dmem[14201] = 32'd0;
    dmem[14202] = 32'd0;
    dmem[14203] = 32'd0;
    dmem[14204] = 32'd0;
    dmem[14205] = 32'd0;
    dmem[14206] = 32'd0;
    dmem[14207] = 32'd0;
    dmem[14208] = 32'd0;
    dmem[14209] = 32'd0;
    dmem[14210] = 32'd0;
    dmem[14211] = 32'd0;
    dmem[14212] = 32'd0;
    dmem[14213] = 32'd0;
    dmem[14214] = 32'd0;
    dmem[14215] = 32'd0;
    dmem[14216] = 32'd0;
    dmem[14217] = 32'd0;
    dmem[14218] = 32'd0;
    dmem[14219] = 32'd0;
    dmem[14220] = 32'd0;
    dmem[14221] = 32'd0;
    dmem[14222] = 32'd0;
    dmem[14223] = 32'd0;
    dmem[14224] = 32'd0;
    dmem[14225] = 32'd0;
    dmem[14226] = 32'd0;
    dmem[14227] = 32'd0;
    dmem[14228] = 32'd0;
    dmem[14229] = 32'd0;
    dmem[14230] = 32'd0;
    dmem[14231] = 32'd0;
    dmem[14232] = 32'd0;
    dmem[14233] = 32'd0;
    dmem[14234] = 32'd0;
    dmem[14235] = 32'd0;
    dmem[14236] = 32'd0;
    dmem[14237] = 32'd0;
    dmem[14238] = 32'd0;
    dmem[14239] = 32'd0;
    dmem[14240] = 32'd0;
    dmem[14241] = 32'd0;
    dmem[14242] = 32'd0;
    dmem[14243] = 32'd0;
    dmem[14244] = 32'd0;
    dmem[14245] = 32'd0;
    dmem[14246] = 32'd0;
    dmem[14247] = 32'd0;
    dmem[14248] = 32'd0;
    dmem[14249] = 32'd0;
    dmem[14250] = 32'd0;
    dmem[14251] = 32'd0;
    dmem[14252] = 32'd0;
    dmem[14253] = 32'd0;
    dmem[14254] = 32'd0;
    dmem[14255] = 32'd0;
    dmem[14256] = 32'd0;
    dmem[14257] = 32'd0;
    dmem[14258] = 32'd0;
    dmem[14259] = 32'd0;
    dmem[14260] = 32'd0;
    dmem[14261] = 32'd0;
    dmem[14262] = 32'd0;
    dmem[14263] = 32'd0;
    dmem[14264] = 32'd0;
    dmem[14265] = 32'd0;
    dmem[14266] = 32'd0;
    dmem[14267] = 32'd0;
    dmem[14268] = 32'd0;
    dmem[14269] = 32'd0;
    dmem[14270] = 32'd0;
    dmem[14271] = 32'd0;
    dmem[14272] = 32'd0;
    dmem[14273] = 32'd0;
    dmem[14274] = 32'd0;
    dmem[14275] = 32'd0;
    dmem[14276] = 32'd0;
    dmem[14277] = 32'd0;
    dmem[14278] = 32'd0;
    dmem[14279] = 32'd0;
    dmem[14280] = 32'd0;
    dmem[14281] = 32'd0;
    dmem[14282] = 32'd0;
    dmem[14283] = 32'd0;
    dmem[14284] = 32'd0;
    dmem[14285] = 32'd0;
    dmem[14286] = 32'd0;
    dmem[14287] = 32'd0;
    dmem[14288] = 32'd0;
    dmem[14289] = 32'd0;
    dmem[14290] = 32'd0;
    dmem[14291] = 32'd0;
    dmem[14292] = 32'd0;
    dmem[14293] = 32'd0;
    dmem[14294] = 32'd0;
    dmem[14295] = 32'd0;
    dmem[14296] = 32'd0;
    dmem[14297] = 32'd0;
    dmem[14298] = 32'd0;
    dmem[14299] = 32'd0;
    dmem[14300] = 32'd0;
    dmem[14301] = 32'd0;
    dmem[14302] = 32'd0;
    dmem[14303] = 32'd0;
    dmem[14304] = 32'd0;
    dmem[14305] = 32'd0;
    dmem[14306] = 32'd0;
    dmem[14307] = 32'd0;
    dmem[14308] = 32'd0;
    dmem[14309] = 32'd0;
    dmem[14310] = 32'd0;
    dmem[14311] = 32'd0;
    dmem[14312] = 32'd0;
    dmem[14313] = 32'd0;
    dmem[14314] = 32'd0;
    dmem[14315] = 32'd0;
    dmem[14316] = 32'd0;
    dmem[14317] = 32'd0;
    dmem[14318] = 32'd0;
    dmem[14319] = 32'd0;
    dmem[14320] = 32'd0;
    dmem[14321] = 32'd0;
    dmem[14322] = 32'd0;
    dmem[14323] = 32'd0;
    dmem[14324] = 32'd0;
    dmem[14325] = 32'd0;
    dmem[14326] = 32'd0;
    dmem[14327] = 32'd0;
    dmem[14328] = 32'd0;
    dmem[14329] = 32'd0;
    dmem[14330] = 32'd0;
    dmem[14331] = 32'd0;
    dmem[14332] = 32'd0;
    dmem[14333] = 32'd0;
    dmem[14334] = 32'd0;
    dmem[14335] = 32'd0;
    dmem[14336] = 32'd0;
    dmem[14337] = 32'd0;
    dmem[14338] = 32'd0;
    dmem[14339] = 32'd0;
    dmem[14340] = 32'd0;
    dmem[14341] = 32'd0;
    dmem[14342] = 32'd0;
    dmem[14343] = 32'd0;
    dmem[14344] = 32'd0;
    dmem[14345] = 32'd0;
    dmem[14346] = 32'd0;
    dmem[14347] = 32'd0;
    dmem[14348] = 32'd0;
    dmem[14349] = 32'd0;
    dmem[14350] = 32'd0;
    dmem[14351] = 32'd0;
    dmem[14352] = 32'd0;
    dmem[14353] = 32'd0;
    dmem[14354] = 32'd0;
    dmem[14355] = 32'd0;
    dmem[14356] = 32'd0;
    dmem[14357] = 32'd0;
    dmem[14358] = 32'd0;
    dmem[14359] = 32'd0;
    dmem[14360] = 32'd0;
    dmem[14361] = 32'd0;
    dmem[14362] = 32'd0;
    dmem[14363] = 32'd0;
    dmem[14364] = 32'd0;
    dmem[14365] = 32'd0;
    dmem[14366] = 32'd0;
    dmem[14367] = 32'd0;
    dmem[14368] = 32'd0;
    dmem[14369] = 32'd0;
    dmem[14370] = 32'd0;
    dmem[14371] = 32'd0;
    dmem[14372] = 32'd0;
    dmem[14373] = 32'd0;
    dmem[14374] = 32'd0;
    dmem[14375] = 32'd0;
    dmem[14376] = 32'd0;
    dmem[14377] = 32'd0;
    dmem[14378] = 32'd0;
    dmem[14379] = 32'd0;
    dmem[14380] = 32'd0;
    dmem[14381] = 32'd0;
    dmem[14382] = 32'd0;
    dmem[14383] = 32'd0;
    dmem[14384] = 32'd0;
    dmem[14385] = 32'd0;
    dmem[14386] = 32'd0;
    dmem[14387] = 32'd0;
    dmem[14388] = 32'd0;
    dmem[14389] = 32'd0;
    dmem[14390] = 32'd0;
    dmem[14391] = 32'd0;
    dmem[14392] = 32'd0;
    dmem[14393] = 32'd0;
    dmem[14394] = 32'd0;
    dmem[14395] = 32'd0;
    dmem[14396] = 32'd0;
    dmem[14397] = 32'd0;
    dmem[14398] = 32'd0;
    dmem[14399] = 32'd0;
    dmem[14400] = 32'd0;
    dmem[14401] = 32'd0;
    dmem[14402] = 32'd0;
    dmem[14403] = 32'd0;
    dmem[14404] = 32'd0;
    dmem[14405] = 32'd0;
    dmem[14406] = 32'd0;
    dmem[14407] = 32'd0;
    dmem[14408] = 32'd0;
    dmem[14409] = 32'd0;
    dmem[14410] = 32'd0;
    dmem[14411] = 32'd0;
    dmem[14412] = 32'd0;
    dmem[14413] = 32'd0;
    dmem[14414] = 32'd0;
    dmem[14415] = 32'd0;
    dmem[14416] = 32'd0;
    dmem[14417] = 32'd0;
    dmem[14418] = 32'd0;
    dmem[14419] = 32'd0;
    dmem[14420] = 32'd0;
    dmem[14421] = 32'd0;
    dmem[14422] = 32'd0;
    dmem[14423] = 32'd0;
    dmem[14424] = 32'd0;
    dmem[14425] = 32'd0;
    dmem[14426] = 32'd0;
    dmem[14427] = 32'd0;
    dmem[14428] = 32'd0;
    dmem[14429] = 32'd0;
    dmem[14430] = 32'd0;
    dmem[14431] = 32'd0;
    dmem[14432] = 32'd0;
    dmem[14433] = 32'd0;
    dmem[14434] = 32'd0;
    dmem[14435] = 32'd0;
    dmem[14436] = 32'd0;
    dmem[14437] = 32'd0;
    dmem[14438] = 32'd0;
    dmem[14439] = 32'd0;
    dmem[14440] = 32'd0;
    dmem[14441] = 32'd0;
    dmem[14442] = 32'd0;
    dmem[14443] = 32'd0;
    dmem[14444] = 32'd0;
    dmem[14445] = 32'd0;
    dmem[14446] = 32'd0;
    dmem[14447] = 32'd0;
    dmem[14448] = 32'd0;
    dmem[14449] = 32'd0;
    dmem[14450] = 32'd0;
    dmem[14451] = 32'd0;
    dmem[14452] = 32'd0;
    dmem[14453] = 32'd0;
    dmem[14454] = 32'd0;
    dmem[14455] = 32'd0;
    dmem[14456] = 32'd0;
    dmem[14457] = 32'd0;
    dmem[14458] = 32'd0;
    dmem[14459] = 32'd0;
    dmem[14460] = 32'd0;
    dmem[14461] = 32'd0;
    dmem[14462] = 32'd0;
    dmem[14463] = 32'd0;
    dmem[14464] = 32'd0;
    dmem[14465] = 32'd0;
    dmem[14466] = 32'd0;
    dmem[14467] = 32'd0;
    dmem[14468] = 32'd0;
    dmem[14469] = 32'd0;
    dmem[14470] = 32'd0;
    dmem[14471] = 32'd0;
    dmem[14472] = 32'd0;
    dmem[14473] = 32'd0;
    dmem[14474] = 32'd0;
    dmem[14475] = 32'd0;
    dmem[14476] = 32'd0;
    dmem[14477] = 32'd0;
    dmem[14478] = 32'd0;
    dmem[14479] = 32'd0;
    dmem[14480] = 32'd0;
    dmem[14481] = 32'd0;
    dmem[14482] = 32'd0;
    dmem[14483] = 32'd0;
    dmem[14484] = 32'd0;
    dmem[14485] = 32'd0;
    dmem[14486] = 32'd0;
    dmem[14487] = 32'd0;
    dmem[14488] = 32'd0;
    dmem[14489] = 32'd0;
    dmem[14490] = 32'd0;
    dmem[14491] = 32'd0;
    dmem[14492] = 32'd0;
    dmem[14493] = 32'd0;
    dmem[14494] = 32'd0;
    dmem[14495] = 32'd0;
    dmem[14496] = 32'd0;
    dmem[14497] = 32'd0;
    dmem[14498] = 32'd0;
    dmem[14499] = 32'd0;
    dmem[14500] = 32'd0;
    dmem[14501] = 32'd0;
    dmem[14502] = 32'd0;
    dmem[14503] = 32'd0;
    dmem[14504] = 32'd0;
    dmem[14505] = 32'd0;
    dmem[14506] = 32'd0;
    dmem[14507] = 32'd0;
    dmem[14508] = 32'd0;
    dmem[14509] = 32'd0;
    dmem[14510] = 32'd0;
    dmem[14511] = 32'd0;
    dmem[14512] = 32'd0;
    dmem[14513] = 32'd0;
    dmem[14514] = 32'd0;
    dmem[14515] = 32'd0;
    dmem[14516] = 32'd0;
    dmem[14517] = 32'd0;
    dmem[14518] = 32'd0;
    dmem[14519] = 32'd0;
    dmem[14520] = 32'd0;
    dmem[14521] = 32'd0;
    dmem[14522] = 32'd0;
    dmem[14523] = 32'd0;
    dmem[14524] = 32'd0;
    dmem[14525] = 32'd0;
    dmem[14526] = 32'd0;
    dmem[14527] = 32'd0;
    dmem[14528] = 32'd0;
    dmem[14529] = 32'd0;
    dmem[14530] = 32'd0;
    dmem[14531] = 32'd0;
    dmem[14532] = 32'd0;
    dmem[14533] = 32'd0;
    dmem[14534] = 32'd0;
    dmem[14535] = 32'd0;
    dmem[14536] = 32'd0;
    dmem[14537] = 32'd0;
    dmem[14538] = 32'd0;
    dmem[14539] = 32'd0;
    dmem[14540] = 32'd0;
    dmem[14541] = 32'd0;
    dmem[14542] = 32'd0;
    dmem[14543] = 32'd0;
    dmem[14544] = 32'd0;
    dmem[14545] = 32'd0;
    dmem[14546] = 32'd0;
    dmem[14547] = 32'd0;
    dmem[14548] = 32'd0;
    dmem[14549] = 32'd0;
    dmem[14550] = 32'd0;
    dmem[14551] = 32'd0;
    dmem[14552] = 32'd0;
    dmem[14553] = 32'd0;
    dmem[14554] = 32'd0;
    dmem[14555] = 32'd0;
    dmem[14556] = 32'd0;
    dmem[14557] = 32'd0;
    dmem[14558] = 32'd0;
    dmem[14559] = 32'd0;
    dmem[14560] = 32'd0;
    dmem[14561] = 32'd0;
    dmem[14562] = 32'd0;
    dmem[14563] = 32'd0;
    dmem[14564] = 32'd0;
    dmem[14565] = 32'd0;
    dmem[14566] = 32'd0;
    dmem[14567] = 32'd0;
    dmem[14568] = 32'd0;
    dmem[14569] = 32'd0;
    dmem[14570] = 32'd0;
    dmem[14571] = 32'd0;
    dmem[14572] = 32'd0;
    dmem[14573] = 32'd0;
    dmem[14574] = 32'd0;
    dmem[14575] = 32'd0;
    dmem[14576] = 32'd0;
    dmem[14577] = 32'd0;
    dmem[14578] = 32'd0;
    dmem[14579] = 32'd0;
    dmem[14580] = 32'd0;
    dmem[14581] = 32'd0;
    dmem[14582] = 32'd0;
    dmem[14583] = 32'd0;
    dmem[14584] = 32'd0;
    dmem[14585] = 32'd0;
    dmem[14586] = 32'd0;
    dmem[14587] = 32'd0;
    dmem[14588] = 32'd0;
    dmem[14589] = 32'd0;
    dmem[14590] = 32'd0;
    dmem[14591] = 32'd0;
    dmem[14592] = 32'd0;
    dmem[14593] = 32'd0;
    dmem[14594] = 32'd0;
    dmem[14595] = 32'd0;
    dmem[14596] = 32'd0;
    dmem[14597] = 32'd0;
    dmem[14598] = 32'd0;
    dmem[14599] = 32'd0;
    dmem[14600] = 32'd0;
    dmem[14601] = 32'd0;
    dmem[14602] = 32'd0;
    dmem[14603] = 32'd0;
    dmem[14604] = 32'd0;
    dmem[14605] = 32'd0;
    dmem[14606] = 32'd0;
    dmem[14607] = 32'd0;
    dmem[14608] = 32'd0;
    dmem[14609] = 32'd0;
    dmem[14610] = 32'd0;
    dmem[14611] = 32'd0;
    dmem[14612] = 32'd0;
    dmem[14613] = 32'd0;
    dmem[14614] = 32'd0;
    dmem[14615] = 32'd0;
    dmem[14616] = 32'd0;
    dmem[14617] = 32'd0;
    dmem[14618] = 32'd0;
    dmem[14619] = 32'd0;
    dmem[14620] = 32'd0;
    dmem[14621] = 32'd0;
    dmem[14622] = 32'd0;
    dmem[14623] = 32'd0;
    dmem[14624] = 32'd0;
    dmem[14625] = 32'd0;
    dmem[14626] = 32'd0;
    dmem[14627] = 32'd0;
    dmem[14628] = 32'd0;
    dmem[14629] = 32'd0;
    dmem[14630] = 32'd0;
    dmem[14631] = 32'd0;
    dmem[14632] = 32'd0;
    dmem[14633] = 32'd0;
    dmem[14634] = 32'd0;
    dmem[14635] = 32'd0;
    dmem[14636] = 32'd0;
    dmem[14637] = 32'd0;
    dmem[14638] = 32'd0;
    dmem[14639] = 32'd0;
    dmem[14640] = 32'd0;
    dmem[14641] = 32'd0;
    dmem[14642] = 32'd0;
    dmem[14643] = 32'd0;
    dmem[14644] = 32'd0;
    dmem[14645] = 32'd0;
    dmem[14646] = 32'd0;
    dmem[14647] = 32'd0;
    dmem[14648] = 32'd0;
    dmem[14649] = 32'd0;
    dmem[14650] = 32'd0;
    dmem[14651] = 32'd0;
    dmem[14652] = 32'd0;
    dmem[14653] = 32'd0;
    dmem[14654] = 32'd0;
    dmem[14655] = 32'd0;
    dmem[14656] = 32'd0;
    dmem[14657] = 32'd0;
    dmem[14658] = 32'd0;
    dmem[14659] = 32'd0;
    dmem[14660] = 32'd0;
    dmem[14661] = 32'd0;
    dmem[14662] = 32'd0;
    dmem[14663] = 32'd0;
    dmem[14664] = 32'd0;
    dmem[14665] = 32'd0;
    dmem[14666] = 32'd0;
    dmem[14667] = 32'd0;
    dmem[14668] = 32'd0;
    dmem[14669] = 32'd0;
    dmem[14670] = 32'd0;
    dmem[14671] = 32'd0;
    dmem[14672] = 32'd0;
    dmem[14673] = 32'd0;
    dmem[14674] = 32'd0;
    dmem[14675] = 32'd0;
    dmem[14676] = 32'd0;
    dmem[14677] = 32'd0;
    dmem[14678] = 32'd0;
    dmem[14679] = 32'd0;
    dmem[14680] = 32'd0;
    dmem[14681] = 32'd0;
    dmem[14682] = 32'd0;
    dmem[14683] = 32'd0;
    dmem[14684] = 32'd0;
    dmem[14685] = 32'd0;
    dmem[14686] = 32'd0;
    dmem[14687] = 32'd0;
    dmem[14688] = 32'd0;
    dmem[14689] = 32'd0;
    dmem[14690] = 32'd0;
    dmem[14691] = 32'd0;
    dmem[14692] = 32'd0;
    dmem[14693] = 32'd0;
    dmem[14694] = 32'd0;
    dmem[14695] = 32'd0;
    dmem[14696] = 32'd0;
    dmem[14697] = 32'd0;
    dmem[14698] = 32'd0;
    dmem[14699] = 32'd0;
    dmem[14700] = 32'd0;
    dmem[14701] = 32'd0;
    dmem[14702] = 32'd0;
    dmem[14703] = 32'd0;
    dmem[14704] = 32'd0;
    dmem[14705] = 32'd0;
    dmem[14706] = 32'd0;
    dmem[14707] = 32'd0;
    dmem[14708] = 32'd0;
    dmem[14709] = 32'd0;
    dmem[14710] = 32'd0;
    dmem[14711] = 32'd0;
    dmem[14712] = 32'd0;
    dmem[14713] = 32'd0;
    dmem[14714] = 32'd0;
    dmem[14715] = 32'd0;
    dmem[14716] = 32'd0;
    dmem[14717] = 32'd0;
    dmem[14718] = 32'd0;
    dmem[14719] = 32'd0;
    dmem[14720] = 32'd0;
    dmem[14721] = 32'd0;
    dmem[14722] = 32'd0;
    dmem[14723] = 32'd0;
    dmem[14724] = 32'd0;
    dmem[14725] = 32'd0;
    dmem[14726] = 32'd0;
    dmem[14727] = 32'd0;
    dmem[14728] = 32'd0;
    dmem[14729] = 32'd0;
    dmem[14730] = 32'd0;
    dmem[14731] = 32'd0;
    dmem[14732] = 32'd0;
    dmem[14733] = 32'd0;
    dmem[14734] = 32'd0;
    dmem[14735] = 32'd0;
    dmem[14736] = 32'd0;
    dmem[14737] = 32'd0;
    dmem[14738] = 32'd0;
    dmem[14739] = 32'd0;
    dmem[14740] = 32'd0;
    dmem[14741] = 32'd0;
    dmem[14742] = 32'd0;
    dmem[14743] = 32'd0;
    dmem[14744] = 32'd0;
    dmem[14745] = 32'd0;
    dmem[14746] = 32'd0;
    dmem[14747] = 32'd0;
    dmem[14748] = 32'd0;
    dmem[14749] = 32'd0;
    dmem[14750] = 32'd0;
    dmem[14751] = 32'd0;
    dmem[14752] = 32'd0;
    dmem[14753] = 32'd0;
    dmem[14754] = 32'd0;
    dmem[14755] = 32'd0;
    dmem[14756] = 32'd0;
    dmem[14757] = 32'd0;
    dmem[14758] = 32'd0;
    dmem[14759] = 32'd0;
    dmem[14760] = 32'd0;
    dmem[14761] = 32'd0;
    dmem[14762] = 32'd0;
    dmem[14763] = 32'd0;
    dmem[14764] = 32'd0;
    dmem[14765] = 32'd0;
    dmem[14766] = 32'd0;
    dmem[14767] = 32'd0;
    dmem[14768] = 32'd0;
    dmem[14769] = 32'd0;
    dmem[14770] = 32'd0;
    dmem[14771] = 32'd0;
    dmem[14772] = 32'd0;
    dmem[14773] = 32'd0;
    dmem[14774] = 32'd0;
    dmem[14775] = 32'd0;
    dmem[14776] = 32'd0;
    dmem[14777] = 32'd0;
    dmem[14778] = 32'd0;
    dmem[14779] = 32'd0;
    dmem[14780] = 32'd0;
    dmem[14781] = 32'd0;
    dmem[14782] = 32'd0;
    dmem[14783] = 32'd0;
    dmem[14784] = 32'd0;
    dmem[14785] = 32'd0;
    dmem[14786] = 32'd0;
    dmem[14787] = 32'd0;
    dmem[14788] = 32'd0;
    dmem[14789] = 32'd0;
    dmem[14790] = 32'd0;
    dmem[14791] = 32'd0;
    dmem[14792] = 32'd0;
    dmem[14793] = 32'd0;
    dmem[14794] = 32'd0;
    dmem[14795] = 32'd0;
    dmem[14796] = 32'd0;
    dmem[14797] = 32'd0;
    dmem[14798] = 32'd0;
    dmem[14799] = 32'd0;
    dmem[14800] = 32'd0;
    dmem[14801] = 32'd0;
    dmem[14802] = 32'd0;
    dmem[14803] = 32'd0;
    dmem[14804] = 32'd0;
    dmem[14805] = 32'd0;
    dmem[14806] = 32'd0;
    dmem[14807] = 32'd0;
    dmem[14808] = 32'd0;
    dmem[14809] = 32'd0;
    dmem[14810] = 32'd0;
    dmem[14811] = 32'd0;
    dmem[14812] = 32'd0;
    dmem[14813] = 32'd0;
    dmem[14814] = 32'd0;
    dmem[14815] = 32'd0;
    dmem[14816] = 32'd0;
    dmem[14817] = 32'd0;
    dmem[14818] = 32'd0;
    dmem[14819] = 32'd0;
    dmem[14820] = 32'd0;
    dmem[14821] = 32'd0;
    dmem[14822] = 32'd0;
    dmem[14823] = 32'd0;
    dmem[14824] = 32'd0;
    dmem[14825] = 32'd0;
    dmem[14826] = 32'd0;
    dmem[14827] = 32'd0;
    dmem[14828] = 32'd0;
    dmem[14829] = 32'd0;
    dmem[14830] = 32'd0;
    dmem[14831] = 32'd0;
    dmem[14832] = 32'd0;
    dmem[14833] = 32'd0;
    dmem[14834] = 32'd0;
    dmem[14835] = 32'd0;
    dmem[14836] = 32'd0;
    dmem[14837] = 32'd0;
    dmem[14838] = 32'd0;
    dmem[14839] = 32'd0;
    dmem[14840] = 32'd0;
    dmem[14841] = 32'd0;
    dmem[14842] = 32'd0;
    dmem[14843] = 32'd0;
    dmem[14844] = 32'd0;
    dmem[14845] = 32'd0;
    dmem[14846] = 32'd0;
    dmem[14847] = 32'd0;
    dmem[14848] = 32'd0;
    dmem[14849] = 32'd0;
    dmem[14850] = 32'd0;
    dmem[14851] = 32'd0;
    dmem[14852] = 32'd0;
    dmem[14853] = 32'd0;
    dmem[14854] = 32'd0;
    dmem[14855] = 32'd0;
    dmem[14856] = 32'd0;
    dmem[14857] = 32'd0;
    dmem[14858] = 32'd0;
    dmem[14859] = 32'd0;
    dmem[14860] = 32'd0;
    dmem[14861] = 32'd0;
    dmem[14862] = 32'd0;
    dmem[14863] = 32'd0;
    dmem[14864] = 32'd0;
    dmem[14865] = 32'd0;
    dmem[14866] = 32'd0;
    dmem[14867] = 32'd0;
    dmem[14868] = 32'd0;
    dmem[14869] = 32'd0;
    dmem[14870] = 32'd0;
    dmem[14871] = 32'd0;
    dmem[14872] = 32'd0;
    dmem[14873] = 32'd0;
    dmem[14874] = 32'd0;
    dmem[14875] = 32'd0;
    dmem[14876] = 32'd0;
    dmem[14877] = 32'd0;
    dmem[14878] = 32'd0;
    dmem[14879] = 32'd0;
    dmem[14880] = 32'd0;
    dmem[14881] = 32'd0;
    dmem[14882] = 32'd0;
    dmem[14883] = 32'd0;
    dmem[14884] = 32'd0;
    dmem[14885] = 32'd0;
    dmem[14886] = 32'd0;
    dmem[14887] = 32'd0;
    dmem[14888] = 32'd0;
    dmem[14889] = 32'd0;
    dmem[14890] = 32'd0;
    dmem[14891] = 32'd0;
    dmem[14892] = 32'd0;
    dmem[14893] = 32'd0;
    dmem[14894] = 32'd0;
    dmem[14895] = 32'd0;
    dmem[14896] = 32'd0;
    dmem[14897] = 32'd0;
    dmem[14898] = 32'd0;
    dmem[14899] = 32'd0;
    dmem[14900] = 32'd0;
    dmem[14901] = 32'd0;
    dmem[14902] = 32'd0;
    dmem[14903] = 32'd0;
    dmem[14904] = 32'd0;
    dmem[14905] = 32'd0;
    dmem[14906] = 32'd0;
    dmem[14907] = 32'd0;
    dmem[14908] = 32'd0;
    dmem[14909] = 32'd0;
    dmem[14910] = 32'd0;
    dmem[14911] = 32'd0;
    dmem[14912] = 32'd0;
    dmem[14913] = 32'd0;
    dmem[14914] = 32'd0;
    dmem[14915] = 32'd0;
    dmem[14916] = 32'd0;
    dmem[14917] = 32'd0;
    dmem[14918] = 32'd0;
    dmem[14919] = 32'd0;
    dmem[14920] = 32'd0;
    dmem[14921] = 32'd0;
    dmem[14922] = 32'd0;
    dmem[14923] = 32'd0;
    dmem[14924] = 32'd0;
    dmem[14925] = 32'd0;
    dmem[14926] = 32'd0;
    dmem[14927] = 32'd0;
    dmem[14928] = 32'd0;
    dmem[14929] = 32'd0;
    dmem[14930] = 32'd0;
    dmem[14931] = 32'd0;
    dmem[14932] = 32'd0;
    dmem[14933] = 32'd0;
    dmem[14934] = 32'd0;
    dmem[14935] = 32'd0;
    dmem[14936] = 32'd0;
    dmem[14937] = 32'd0;
    dmem[14938] = 32'd0;
    dmem[14939] = 32'd0;
    dmem[14940] = 32'd0;
    dmem[14941] = 32'd0;
    dmem[14942] = 32'd0;
    dmem[14943] = 32'd0;
    dmem[14944] = 32'd0;
    dmem[14945] = 32'd0;
    dmem[14946] = 32'd0;
    dmem[14947] = 32'd0;
    dmem[14948] = 32'd0;
    dmem[14949] = 32'd0;
    dmem[14950] = 32'd0;
    dmem[14951] = 32'd0;
    dmem[14952] = 32'd0;
    dmem[14953] = 32'd0;
    dmem[14954] = 32'd0;
    dmem[14955] = 32'd0;
    dmem[14956] = 32'd0;
    dmem[14957] = 32'd0;
    dmem[14958] = 32'd0;
    dmem[14959] = 32'd0;
    dmem[14960] = 32'd0;
    dmem[14961] = 32'd0;
    dmem[14962] = 32'd0;
    dmem[14963] = 32'd0;
    dmem[14964] = 32'd0;
    dmem[14965] = 32'd0;
    dmem[14966] = 32'd0;
    dmem[14967] = 32'd0;
    dmem[14968] = 32'd0;
    dmem[14969] = 32'd0;
    dmem[14970] = 32'd0;
    dmem[14971] = 32'd0;
    dmem[14972] = 32'd0;
    dmem[14973] = 32'd0;
    dmem[14974] = 32'd0;
    dmem[14975] = 32'd0;
    dmem[14976] = 32'd0;
    dmem[14977] = 32'd0;
    dmem[14978] = 32'd0;
    dmem[14979] = 32'd0;
    dmem[14980] = 32'd0;
    dmem[14981] = 32'd0;
    dmem[14982] = 32'd0;
    dmem[14983] = 32'd0;
    dmem[14984] = 32'd0;
    dmem[14985] = 32'd0;
    dmem[14986] = 32'd0;
    dmem[14987] = 32'd0;
    dmem[14988] = 32'd0;
    dmem[14989] = 32'd0;
    dmem[14990] = 32'd0;
    dmem[14991] = 32'd0;
    dmem[14992] = 32'd0;
    dmem[14993] = 32'd0;
    dmem[14994] = 32'd0;
    dmem[14995] = 32'd0;
    dmem[14996] = 32'd0;
    dmem[14997] = 32'd0;
    dmem[14998] = 32'd0;
    dmem[14999] = 32'd0;
    dmem[15000] = 32'd0;
    dmem[15001] = 32'd0;
    dmem[15002] = 32'd0;
    dmem[15003] = 32'd0;
    dmem[15004] = 32'd0;
    dmem[15005] = 32'd0;
    dmem[15006] = 32'd0;
    dmem[15007] = 32'd0;
    dmem[15008] = 32'd0;
    dmem[15009] = 32'd0;
    dmem[15010] = 32'd0;
    dmem[15011] = 32'd0;
    dmem[15012] = 32'd0;
    dmem[15013] = 32'd0;
    dmem[15014] = 32'd0;
    dmem[15015] = 32'd0;
    dmem[15016] = 32'd0;
    dmem[15017] = 32'd0;
    dmem[15018] = 32'd0;
    dmem[15019] = 32'd0;
    dmem[15020] = 32'd0;
    dmem[15021] = 32'd0;
    dmem[15022] = 32'd0;
    dmem[15023] = 32'd0;
    dmem[15024] = 32'd0;
    dmem[15025] = 32'd0;
    dmem[15026] = 32'd0;
    dmem[15027] = 32'd0;
    dmem[15028] = 32'd0;
    dmem[15029] = 32'd0;
    dmem[15030] = 32'd0;
    dmem[15031] = 32'd0;
    dmem[15032] = 32'd0;
    dmem[15033] = 32'd0;
    dmem[15034] = 32'd0;
    dmem[15035] = 32'd0;
    dmem[15036] = 32'd0;
    dmem[15037] = 32'd0;
    dmem[15038] = 32'd0;
    dmem[15039] = 32'd0;
    dmem[15040] = 32'd0;
    dmem[15041] = 32'd0;
    dmem[15042] = 32'd0;
    dmem[15043] = 32'd0;
    dmem[15044] = 32'd0;
    dmem[15045] = 32'd0;
    dmem[15046] = 32'd0;
    dmem[15047] = 32'd0;
    dmem[15048] = 32'd0;
    dmem[15049] = 32'd0;
    dmem[15050] = 32'd0;
    dmem[15051] = 32'd0;
    dmem[15052] = 32'd0;
    dmem[15053] = 32'd0;
    dmem[15054] = 32'd0;
    dmem[15055] = 32'd0;
    dmem[15056] = 32'd0;
    dmem[15057] = 32'd0;
    dmem[15058] = 32'd0;
    dmem[15059] = 32'd0;
    dmem[15060] = 32'd0;
    dmem[15061] = 32'd0;
    dmem[15062] = 32'd0;
    dmem[15063] = 32'd0;
    dmem[15064] = 32'd0;
    dmem[15065] = 32'd0;
    dmem[15066] = 32'd0;
    dmem[15067] = 32'd0;
    dmem[15068] = 32'd0;
    dmem[15069] = 32'd0;
    dmem[15070] = 32'd0;
    dmem[15071] = 32'd0;
    dmem[15072] = 32'd0;
    dmem[15073] = 32'd0;
    dmem[15074] = 32'd0;
    dmem[15075] = 32'd0;
    dmem[15076] = 32'd0;
    dmem[15077] = 32'd0;
    dmem[15078] = 32'd0;
    dmem[15079] = 32'd0;
    dmem[15080] = 32'd0;
    dmem[15081] = 32'd0;
    dmem[15082] = 32'd0;
    dmem[15083] = 32'd0;
    dmem[15084] = 32'd0;
    dmem[15085] = 32'd0;
    dmem[15086] = 32'd0;
    dmem[15087] = 32'd0;
    dmem[15088] = 32'd0;
    dmem[15089] = 32'd0;
    dmem[15090] = 32'd0;
    dmem[15091] = 32'd0;
    dmem[15092] = 32'd0;
    dmem[15093] = 32'd0;
    dmem[15094] = 32'd0;
    dmem[15095] = 32'd0;
    dmem[15096] = 32'd0;
    dmem[15097] = 32'd0;
    dmem[15098] = 32'd0;
    dmem[15099] = 32'd0;
    dmem[15100] = 32'd0;
    dmem[15101] = 32'd0;
    dmem[15102] = 32'd0;
    dmem[15103] = 32'd0;
    dmem[15104] = 32'd0;
    dmem[15105] = 32'd0;
    dmem[15106] = 32'd0;
    dmem[15107] = 32'd0;
    dmem[15108] = 32'd0;
    dmem[15109] = 32'd0;
    dmem[15110] = 32'd0;
    dmem[15111] = 32'd0;
    dmem[15112] = 32'd0;
    dmem[15113] = 32'd0;
    dmem[15114] = 32'd0;
    dmem[15115] = 32'd0;
    dmem[15116] = 32'd0;
    dmem[15117] = 32'd0;
    dmem[15118] = 32'd0;
    dmem[15119] = 32'd0;
    dmem[15120] = 32'd0;
    dmem[15121] = 32'd0;
    dmem[15122] = 32'd0;
    dmem[15123] = 32'd0;
    dmem[15124] = 32'd0;
    dmem[15125] = 32'd0;
    dmem[15126] = 32'd0;
    dmem[15127] = 32'd0;
    dmem[15128] = 32'd0;
    dmem[15129] = 32'd0;
    dmem[15130] = 32'd0;
    dmem[15131] = 32'd0;
    dmem[15132] = 32'd0;
    dmem[15133] = 32'd0;
    dmem[15134] = 32'd0;
    dmem[15135] = 32'd0;
    dmem[15136] = 32'd0;
    dmem[15137] = 32'd0;
    dmem[15138] = 32'd0;
    dmem[15139] = 32'd0;
    dmem[15140] = 32'd0;
    dmem[15141] = 32'd0;
    dmem[15142] = 32'd0;
    dmem[15143] = 32'd0;
    dmem[15144] = 32'd0;
    dmem[15145] = 32'd0;
    dmem[15146] = 32'd0;
    dmem[15147] = 32'd0;
    dmem[15148] = 32'd0;
    dmem[15149] = 32'd0;
    dmem[15150] = 32'd0;
    dmem[15151] = 32'd0;
    dmem[15152] = 32'd0;
    dmem[15153] = 32'd0;
    dmem[15154] = 32'd0;
    dmem[15155] = 32'd0;
    dmem[15156] = 32'd0;
    dmem[15157] = 32'd0;
    dmem[15158] = 32'd0;
    dmem[15159] = 32'd0;
    dmem[15160] = 32'd0;
    dmem[15161] = 32'd0;
    dmem[15162] = 32'd0;
    dmem[15163] = 32'd0;
    dmem[15164] = 32'd0;
    dmem[15165] = 32'd0;
    dmem[15166] = 32'd0;
    dmem[15167] = 32'd0;
    dmem[15168] = 32'd0;
    dmem[15169] = 32'd0;
    dmem[15170] = 32'd0;
    dmem[15171] = 32'd0;
    dmem[15172] = 32'd0;
    dmem[15173] = 32'd0;
    dmem[15174] = 32'd0;
    dmem[15175] = 32'd0;
    dmem[15176] = 32'd0;
    dmem[15177] = 32'd0;
    dmem[15178] = 32'd0;
    dmem[15179] = 32'd0;
    dmem[15180] = 32'd0;
    dmem[15181] = 32'd0;
    dmem[15182] = 32'd0;
    dmem[15183] = 32'd0;
    dmem[15184] = 32'd0;
    dmem[15185] = 32'd0;
    dmem[15186] = 32'd0;
    dmem[15187] = 32'd0;
    dmem[15188] = 32'd0;
    dmem[15189] = 32'd0;
    dmem[15190] = 32'd0;
    dmem[15191] = 32'd0;
    dmem[15192] = 32'd0;
    dmem[15193] = 32'd0;
    dmem[15194] = 32'd0;
    dmem[15195] = 32'd0;
    dmem[15196] = 32'd0;
    dmem[15197] = 32'd0;
    dmem[15198] = 32'd0;
    dmem[15199] = 32'd0;
    dmem[15200] = 32'd0;
    dmem[15201] = 32'd0;
    dmem[15202] = 32'd0;
    dmem[15203] = 32'd0;
    dmem[15204] = 32'd0;
    dmem[15205] = 32'd0;
    dmem[15206] = 32'd0;
    dmem[15207] = 32'd0;
    dmem[15208] = 32'd0;
    dmem[15209] = 32'd0;
    dmem[15210] = 32'd0;
    dmem[15211] = 32'd0;
    dmem[15212] = 32'd0;
    dmem[15213] = 32'd0;
    dmem[15214] = 32'd0;
    dmem[15215] = 32'd0;
    dmem[15216] = 32'd0;
    dmem[15217] = 32'd0;
    dmem[15218] = 32'd0;
    dmem[15219] = 32'd0;
    dmem[15220] = 32'd0;
    dmem[15221] = 32'd0;
    dmem[15222] = 32'd0;
    dmem[15223] = 32'd0;
    dmem[15224] = 32'd0;
    dmem[15225] = 32'd0;
    dmem[15226] = 32'd0;
    dmem[15227] = 32'd0;
    dmem[15228] = 32'd0;
    dmem[15229] = 32'd0;
    dmem[15230] = 32'd0;
    dmem[15231] = 32'd0;
    dmem[15232] = 32'd0;
    dmem[15233] = 32'd0;
    dmem[15234] = 32'd0;
    dmem[15235] = 32'd0;
    dmem[15236] = 32'd0;
    dmem[15237] = 32'd0;
    dmem[15238] = 32'd0;
    dmem[15239] = 32'd0;
    dmem[15240] = 32'd0;
    dmem[15241] = 32'd0;
    dmem[15242] = 32'd0;
    dmem[15243] = 32'd0;
    dmem[15244] = 32'd0;
    dmem[15245] = 32'd0;
    dmem[15246] = 32'd0;
    dmem[15247] = 32'd0;
    dmem[15248] = 32'd0;
    dmem[15249] = 32'd0;
    dmem[15250] = 32'd0;
    dmem[15251] = 32'd0;
    dmem[15252] = 32'd0;
    dmem[15253] = 32'd0;
    dmem[15254] = 32'd0;
    dmem[15255] = 32'd0;
    dmem[15256] = 32'd0;
    dmem[15257] = 32'd0;
    dmem[15258] = 32'd0;
    dmem[15259] = 32'd0;
    dmem[15260] = 32'd0;
    dmem[15261] = 32'd0;
    dmem[15262] = 32'd0;
    dmem[15263] = 32'd0;
    dmem[15264] = 32'd0;
    dmem[15265] = 32'd0;
    dmem[15266] = 32'd0;
    dmem[15267] = 32'd0;
    dmem[15268] = 32'd0;
    dmem[15269] = 32'd0;
    dmem[15270] = 32'd0;
    dmem[15271] = 32'd0;
    dmem[15272] = 32'd0;
    dmem[15273] = 32'd0;
    dmem[15274] = 32'd0;
    dmem[15275] = 32'd0;
    dmem[15276] = 32'd0;
    dmem[15277] = 32'd0;
    dmem[15278] = 32'd0;
    dmem[15279] = 32'd0;
    dmem[15280] = 32'd0;
    dmem[15281] = 32'd0;
    dmem[15282] = 32'd0;
    dmem[15283] = 32'd0;
    dmem[15284] = 32'd0;
    dmem[15285] = 32'd0;
    dmem[15286] = 32'd0;
    dmem[15287] = 32'd0;
    dmem[15288] = 32'd0;
    dmem[15289] = 32'd0;
    dmem[15290] = 32'd0;
    dmem[15291] = 32'd0;
    dmem[15292] = 32'd0;
    dmem[15293] = 32'd0;
    dmem[15294] = 32'd0;
    dmem[15295] = 32'd0;
    dmem[15296] = 32'd0;
    dmem[15297] = 32'd0;
    dmem[15298] = 32'd0;
    dmem[15299] = 32'd0;
    dmem[15300] = 32'd0;
    dmem[15301] = 32'd0;
    dmem[15302] = 32'd0;
    dmem[15303] = 32'd0;
    dmem[15304] = 32'd0;
    dmem[15305] = 32'd0;
    dmem[15306] = 32'd0;
    dmem[15307] = 32'd0;
    dmem[15308] = 32'd0;
    dmem[15309] = 32'd0;
    dmem[15310] = 32'd0;
    dmem[15311] = 32'd0;
    dmem[15312] = 32'd0;
    dmem[15313] = 32'd0;
    dmem[15314] = 32'd0;
    dmem[15315] = 32'd0;
    dmem[15316] = 32'd0;
    dmem[15317] = 32'd0;
    dmem[15318] = 32'd0;
    dmem[15319] = 32'd0;
    dmem[15320] = 32'd0;
    dmem[15321] = 32'd0;
    dmem[15322] = 32'd0;
    dmem[15323] = 32'd0;
    dmem[15324] = 32'd0;
    dmem[15325] = 32'd0;
    dmem[15326] = 32'd0;
    dmem[15327] = 32'd0;
    dmem[15328] = 32'd0;
    dmem[15329] = 32'd0;
    dmem[15330] = 32'd0;
    dmem[15331] = 32'd0;
    dmem[15332] = 32'd0;
    dmem[15333] = 32'd0;
    dmem[15334] = 32'd0;
    dmem[15335] = 32'd0;
    dmem[15336] = 32'd0;
    dmem[15337] = 32'd0;
    dmem[15338] = 32'd0;
    dmem[15339] = 32'd0;
    dmem[15340] = 32'd0;
    dmem[15341] = 32'd0;
    dmem[15342] = 32'd0;
    dmem[15343] = 32'd0;
    dmem[15344] = 32'd0;
    dmem[15345] = 32'd0;
    dmem[15346] = 32'd0;
    dmem[15347] = 32'd0;
    dmem[15348] = 32'd0;
    dmem[15349] = 32'd0;
    dmem[15350] = 32'd0;
    dmem[15351] = 32'd0;
    dmem[15352] = 32'd0;
    dmem[15353] = 32'd0;
    dmem[15354] = 32'd0;
    dmem[15355] = 32'd0;
    dmem[15356] = 32'd0;
    dmem[15357] = 32'd0;
    dmem[15358] = 32'd0;
    dmem[15359] = 32'd0;
    dmem[15360] = 32'd0;
    dmem[15361] = 32'd0;
    dmem[15362] = 32'd0;
    dmem[15363] = 32'd0;
    dmem[15364] = 32'd0;
    dmem[15365] = 32'd0;
    dmem[15366] = 32'd0;
    dmem[15367] = 32'd0;
    dmem[15368] = 32'd0;
    dmem[15369] = 32'd0;
    dmem[15370] = 32'd0;
    dmem[15371] = 32'd0;
    dmem[15372] = 32'd0;
    dmem[15373] = 32'd0;
    dmem[15374] = 32'd0;
    dmem[15375] = 32'd0;
    dmem[15376] = 32'd0;
    dmem[15377] = 32'd0;
    dmem[15378] = 32'd0;
    dmem[15379] = 32'd0;
    dmem[15380] = 32'd0;
    dmem[15381] = 32'd0;
    dmem[15382] = 32'd0;
    dmem[15383] = 32'd0;
    dmem[15384] = 32'd0;
    dmem[15385] = 32'd0;
    dmem[15386] = 32'd0;
    dmem[15387] = 32'd0;
    dmem[15388] = 32'd0;
    dmem[15389] = 32'd0;
    dmem[15390] = 32'd0;
    dmem[15391] = 32'd0;
    dmem[15392] = 32'd0;
    dmem[15393] = 32'd0;
    dmem[15394] = 32'd0;
    dmem[15395] = 32'd0;
    dmem[15396] = 32'd0;
    dmem[15397] = 32'd0;
    dmem[15398] = 32'd0;
    dmem[15399] = 32'd0;
    dmem[15400] = 32'd0;
    dmem[15401] = 32'd0;
    dmem[15402] = 32'd0;
    dmem[15403] = 32'd0;
    dmem[15404] = 32'd0;
    dmem[15405] = 32'd0;
    dmem[15406] = 32'd0;
    dmem[15407] = 32'd0;
    dmem[15408] = 32'd0;
    dmem[15409] = 32'd0;
    dmem[15410] = 32'd0;
    dmem[15411] = 32'd0;
    dmem[15412] = 32'd0;
    dmem[15413] = 32'd0;
    dmem[15414] = 32'd0;
    dmem[15415] = 32'd0;
    dmem[15416] = 32'd0;
    dmem[15417] = 32'd0;
    dmem[15418] = 32'd0;
    dmem[15419] = 32'd0;
    dmem[15420] = 32'd0;
    dmem[15421] = 32'd0;
    dmem[15422] = 32'd0;
    dmem[15423] = 32'd0;
    dmem[15424] = 32'd0;
    dmem[15425] = 32'd0;
    dmem[15426] = 32'd0;
    dmem[15427] = 32'd0;
    dmem[15428] = 32'd0;
    dmem[15429] = 32'd0;
    dmem[15430] = 32'd0;
    dmem[15431] = 32'd0;
    dmem[15432] = 32'd0;
    dmem[15433] = 32'd0;
    dmem[15434] = 32'd0;
    dmem[15435] = 32'd0;
    dmem[15436] = 32'd0;
    dmem[15437] = 32'd0;
    dmem[15438] = 32'd0;
    dmem[15439] = 32'd0;
    dmem[15440] = 32'd0;
    dmem[15441] = 32'd0;
    dmem[15442] = 32'd0;
    dmem[15443] = 32'd0;
    dmem[15444] = 32'd0;
    dmem[15445] = 32'd0;
    dmem[15446] = 32'd0;
    dmem[15447] = 32'd0;
    dmem[15448] = 32'd0;
    dmem[15449] = 32'd0;
    dmem[15450] = 32'd0;
    dmem[15451] = 32'd0;
    dmem[15452] = 32'd0;
    dmem[15453] = 32'd0;
    dmem[15454] = 32'd0;
    dmem[15455] = 32'd0;
    dmem[15456] = 32'd0;
    dmem[15457] = 32'd0;
    dmem[15458] = 32'd0;
    dmem[15459] = 32'd0;
    dmem[15460] = 32'd0;
    dmem[15461] = 32'd0;
    dmem[15462] = 32'd0;
    dmem[15463] = 32'd0;
    dmem[15464] = 32'd0;
    dmem[15465] = 32'd0;
    dmem[15466] = 32'd0;
    dmem[15467] = 32'd0;
    dmem[15468] = 32'd0;
    dmem[15469] = 32'd0;
    dmem[15470] = 32'd0;
    dmem[15471] = 32'd0;
    dmem[15472] = 32'd0;
    dmem[15473] = 32'd0;
    dmem[15474] = 32'd0;
    dmem[15475] = 32'd0;
    dmem[15476] = 32'd0;
    dmem[15477] = 32'd0;
    dmem[15478] = 32'd0;
    dmem[15479] = 32'd0;
    dmem[15480] = 32'd0;
    dmem[15481] = 32'd0;
    dmem[15482] = 32'd0;
    dmem[15483] = 32'd0;
    dmem[15484] = 32'd0;
    dmem[15485] = 32'd0;
    dmem[15486] = 32'd0;
    dmem[15487] = 32'd0;
    dmem[15488] = 32'd0;
    dmem[15489] = 32'd0;
    dmem[15490] = 32'd0;
    dmem[15491] = 32'd0;
    dmem[15492] = 32'd0;
    dmem[15493] = 32'd0;
    dmem[15494] = 32'd0;
    dmem[15495] = 32'd0;
    dmem[15496] = 32'd0;
    dmem[15497] = 32'd0;
    dmem[15498] = 32'd0;
    dmem[15499] = 32'd0;
    dmem[15500] = 32'd0;
    dmem[15501] = 32'd0;
    dmem[15502] = 32'd0;
    dmem[15503] = 32'd0;
    dmem[15504] = 32'd0;
    dmem[15505] = 32'd0;
    dmem[15506] = 32'd0;
    dmem[15507] = 32'd0;
    dmem[15508] = 32'd0;
    dmem[15509] = 32'd0;
    dmem[15510] = 32'd0;
    dmem[15511] = 32'd0;
    dmem[15512] = 32'd0;
    dmem[15513] = 32'd0;
    dmem[15514] = 32'd0;
    dmem[15515] = 32'd0;
    dmem[15516] = 32'd0;
    dmem[15517] = 32'd0;
    dmem[15518] = 32'd0;
    dmem[15519] = 32'd0;
    dmem[15520] = 32'd0;
    dmem[15521] = 32'd0;
    dmem[15522] = 32'd0;
    dmem[15523] = 32'd0;
    dmem[15524] = 32'd0;
    dmem[15525] = 32'd0;
    dmem[15526] = 32'd0;
    dmem[15527] = 32'd0;
    dmem[15528] = 32'd0;
    dmem[15529] = 32'd0;
    dmem[15530] = 32'd0;
    dmem[15531] = 32'd0;
    dmem[15532] = 32'd0;
    dmem[15533] = 32'd0;
    dmem[15534] = 32'd0;
    dmem[15535] = 32'd0;
    dmem[15536] = 32'd0;
    dmem[15537] = 32'd0;
    dmem[15538] = 32'd0;
    dmem[15539] = 32'd0;
    dmem[15540] = 32'd0;
    dmem[15541] = 32'd0;
    dmem[15542] = 32'd0;
    dmem[15543] = 32'd0;
    dmem[15544] = 32'd0;
    dmem[15545] = 32'd0;
    dmem[15546] = 32'd0;
    dmem[15547] = 32'd0;
    dmem[15548] = 32'd0;
    dmem[15549] = 32'd0;
    dmem[15550] = 32'd0;
    dmem[15551] = 32'd0;
    dmem[15552] = 32'd0;
    dmem[15553] = 32'd0;
    dmem[15554] = 32'd0;
    dmem[15555] = 32'd0;
    dmem[15556] = 32'd0;
    dmem[15557] = 32'd0;
    dmem[15558] = 32'd0;
    dmem[15559] = 32'd0;
    dmem[15560] = 32'd0;
    dmem[15561] = 32'd0;
    dmem[15562] = 32'd0;
    dmem[15563] = 32'd0;
    dmem[15564] = 32'd0;
    dmem[15565] = 32'd0;
    dmem[15566] = 32'd0;
    dmem[15567] = 32'd0;
    dmem[15568] = 32'd0;
    dmem[15569] = 32'd0;
    dmem[15570] = 32'd0;
    dmem[15571] = 32'd0;
    dmem[15572] = 32'd0;
    dmem[15573] = 32'd0;
    dmem[15574] = 32'd0;
    dmem[15575] = 32'd0;
    dmem[15576] = 32'd0;
    dmem[15577] = 32'd0;
    dmem[15578] = 32'd0;
    dmem[15579] = 32'd0;
    dmem[15580] = 32'd0;
    dmem[15581] = 32'd0;
    dmem[15582] = 32'd0;
    dmem[15583] = 32'd0;
    dmem[15584] = 32'd0;
    dmem[15585] = 32'd0;
    dmem[15586] = 32'd0;
    dmem[15587] = 32'd0;
    dmem[15588] = 32'd0;
    dmem[15589] = 32'd0;
    dmem[15590] = 32'd0;
    dmem[15591] = 32'd0;
    dmem[15592] = 32'd0;
    dmem[15593] = 32'd0;
    dmem[15594] = 32'd0;
    dmem[15595] = 32'd0;
    dmem[15596] = 32'd0;
    dmem[15597] = 32'd0;
    dmem[15598] = 32'd0;
    dmem[15599] = 32'd0;
    dmem[15600] = 32'd0;
    dmem[15601] = 32'd0;
    dmem[15602] = 32'd0;
    dmem[15603] = 32'd0;
    dmem[15604] = 32'd0;
    dmem[15605] = 32'd0;
    dmem[15606] = 32'd0;
    dmem[15607] = 32'd0;
    dmem[15608] = 32'd0;
    dmem[15609] = 32'd0;
    dmem[15610] = 32'd0;
    dmem[15611] = 32'd0;
    dmem[15612] = 32'd0;
    dmem[15613] = 32'd0;
    dmem[15614] = 32'd0;
    dmem[15615] = 32'd0;
    dmem[15616] = 32'd0;
    dmem[15617] = 32'd0;
    dmem[15618] = 32'd0;
    dmem[15619] = 32'd0;
    dmem[15620] = 32'd0;
    dmem[15621] = 32'd0;
    dmem[15622] = 32'd0;
    dmem[15623] = 32'd0;
    dmem[15624] = 32'd0;
    dmem[15625] = 32'd0;
    dmem[15626] = 32'd0;
    dmem[15627] = 32'd0;
    dmem[15628] = 32'd0;
    dmem[15629] = 32'd0;
    dmem[15630] = 32'd0;
    dmem[15631] = 32'd0;
    dmem[15632] = 32'd0;
    dmem[15633] = 32'd0;
    dmem[15634] = 32'd0;
    dmem[15635] = 32'd0;
    dmem[15636] = 32'd0;
    dmem[15637] = 32'd0;
    dmem[15638] = 32'd0;
    dmem[15639] = 32'd0;
    dmem[15640] = 32'd0;
    dmem[15641] = 32'd0;
    dmem[15642] = 32'd0;
    dmem[15643] = 32'd0;
    dmem[15644] = 32'd0;
    dmem[15645] = 32'd0;
    dmem[15646] = 32'd0;
    dmem[15647] = 32'd0;
    dmem[15648] = 32'd0;
    dmem[15649] = 32'd0;
    dmem[15650] = 32'd0;
    dmem[15651] = 32'd0;
    dmem[15652] = 32'd0;
    dmem[15653] = 32'd0;
    dmem[15654] = 32'd0;
    dmem[15655] = 32'd0;
    dmem[15656] = 32'd0;
    dmem[15657] = 32'd0;
    dmem[15658] = 32'd0;
    dmem[15659] = 32'd0;
    dmem[15660] = 32'd0;
    dmem[15661] = 32'd0;
    dmem[15662] = 32'd0;
    dmem[15663] = 32'd0;
    dmem[15664] = 32'd0;
    dmem[15665] = 32'd0;
    dmem[15666] = 32'd0;
    dmem[15667] = 32'd0;
    dmem[15668] = 32'd0;
    dmem[15669] = 32'd0;
    dmem[15670] = 32'd0;
    dmem[15671] = 32'd0;
    dmem[15672] = 32'd0;
    dmem[15673] = 32'd0;
    dmem[15674] = 32'd0;
    dmem[15675] = 32'd0;
    dmem[15676] = 32'd0;
    dmem[15677] = 32'd0;
    dmem[15678] = 32'd0;
    dmem[15679] = 32'd0;
    dmem[15680] = 32'd0;
    dmem[15681] = 32'd0;
    dmem[15682] = 32'd0;
    dmem[15683] = 32'd0;
    dmem[15684] = 32'd0;
    dmem[15685] = 32'd0;
    dmem[15686] = 32'd0;
    dmem[15687] = 32'd0;
    dmem[15688] = 32'd0;
    dmem[15689] = 32'd0;
    dmem[15690] = 32'd0;
    dmem[15691] = 32'd0;
    dmem[15692] = 32'd0;
    dmem[15693] = 32'd0;
    dmem[15694] = 32'd0;
    dmem[15695] = 32'd0;
    dmem[15696] = 32'd0;
    dmem[15697] = 32'd0;
    dmem[15698] = 32'd0;
    dmem[15699] = 32'd0;
    dmem[15700] = 32'd0;
    dmem[15701] = 32'd0;
    dmem[15702] = 32'd0;
    dmem[15703] = 32'd0;
    dmem[15704] = 32'd0;
    dmem[15705] = 32'd0;
    dmem[15706] = 32'd0;
    dmem[15707] = 32'd0;
    dmem[15708] = 32'd0;
    dmem[15709] = 32'd0;
    dmem[15710] = 32'd0;
    dmem[15711] = 32'd0;
    dmem[15712] = 32'd0;
    dmem[15713] = 32'd0;
    dmem[15714] = 32'd0;
    dmem[15715] = 32'd0;
    dmem[15716] = 32'd0;
    dmem[15717] = 32'd0;
    dmem[15718] = 32'd0;
    dmem[15719] = 32'd0;
    dmem[15720] = 32'd0;
    dmem[15721] = 32'd0;
    dmem[15722] = 32'd0;
    dmem[15723] = 32'd0;
    dmem[15724] = 32'd0;
    dmem[15725] = 32'd0;
    dmem[15726] = 32'd0;
    dmem[15727] = 32'd0;
    dmem[15728] = 32'd0;
    dmem[15729] = 32'd0;
    dmem[15730] = 32'd0;
    dmem[15731] = 32'd0;
    dmem[15732] = 32'd0;
    dmem[15733] = 32'd0;
    dmem[15734] = 32'd0;
    dmem[15735] = 32'd0;
    dmem[15736] = 32'd0;
    dmem[15737] = 32'd0;
    dmem[15738] = 32'd0;
    dmem[15739] = 32'd0;
    dmem[15740] = 32'd0;
    dmem[15741] = 32'd0;
    dmem[15742] = 32'd0;
    dmem[15743] = 32'd0;
    dmem[15744] = 32'd0;
    dmem[15745] = 32'd0;
    dmem[15746] = 32'd0;
    dmem[15747] = 32'd0;
    dmem[15748] = 32'd0;
    dmem[15749] = 32'd0;
    dmem[15750] = 32'd0;
    dmem[15751] = 32'd0;
    dmem[15752] = 32'd0;
    dmem[15753] = 32'd0;
    dmem[15754] = 32'd0;
    dmem[15755] = 32'd0;
    dmem[15756] = 32'd0;
    dmem[15757] = 32'd0;
    dmem[15758] = 32'd0;
    dmem[15759] = 32'd0;
    dmem[15760] = 32'd0;
    dmem[15761] = 32'd0;
    dmem[15762] = 32'd0;
    dmem[15763] = 32'd0;
    dmem[15764] = 32'd0;
    dmem[15765] = 32'd0;
    dmem[15766] = 32'd0;
    dmem[15767] = 32'd0;
    dmem[15768] = 32'd0;
    dmem[15769] = 32'd0;
    dmem[15770] = 32'd0;
    dmem[15771] = 32'd0;
    dmem[15772] = 32'd0;
    dmem[15773] = 32'd0;
    dmem[15774] = 32'd0;
    dmem[15775] = 32'd0;
    dmem[15776] = 32'd0;
    dmem[15777] = 32'd0;
    dmem[15778] = 32'd0;
    dmem[15779] = 32'd0;
    dmem[15780] = 32'd0;
    dmem[15781] = 32'd0;
    dmem[15782] = 32'd0;
    dmem[15783] = 32'd0;
    dmem[15784] = 32'd0;
    dmem[15785] = 32'd0;
    dmem[15786] = 32'd0;
    dmem[15787] = 32'd0;
    dmem[15788] = 32'd0;
    dmem[15789] = 32'd0;
    dmem[15790] = 32'd0;
    dmem[15791] = 32'd0;
    dmem[15792] = 32'd0;
    dmem[15793] = 32'd0;
    dmem[15794] = 32'd0;
    dmem[15795] = 32'd0;
    dmem[15796] = 32'd0;
    dmem[15797] = 32'd0;
    dmem[15798] = 32'd0;
    dmem[15799] = 32'd0;
    dmem[15800] = 32'd0;
    dmem[15801] = 32'd0;
    dmem[15802] = 32'd0;
    dmem[15803] = 32'd0;
    dmem[15804] = 32'd0;
    dmem[15805] = 32'd0;
    dmem[15806] = 32'd0;
    dmem[15807] = 32'd0;
    dmem[15808] = 32'd0;
    dmem[15809] = 32'd0;
    dmem[15810] = 32'd0;
    dmem[15811] = 32'd0;
    dmem[15812] = 32'd0;
    dmem[15813] = 32'd0;
    dmem[15814] = 32'd0;
    dmem[15815] = 32'd0;
    dmem[15816] = 32'd0;
    dmem[15817] = 32'd0;
    dmem[15818] = 32'd0;
    dmem[15819] = 32'd0;
    dmem[15820] = 32'd0;
    dmem[15821] = 32'd0;
    dmem[15822] = 32'd0;
    dmem[15823] = 32'd0;
    dmem[15824] = 32'd0;
    dmem[15825] = 32'd0;
    dmem[15826] = 32'd0;
    dmem[15827] = 32'd0;
    dmem[15828] = 32'd0;
    dmem[15829] = 32'd0;
    dmem[15830] = 32'd0;
    dmem[15831] = 32'd0;
    dmem[15832] = 32'd0;
    dmem[15833] = 32'd0;
    dmem[15834] = 32'd0;
    dmem[15835] = 32'd0;
    dmem[15836] = 32'd0;
    dmem[15837] = 32'd0;
    dmem[15838] = 32'd0;
    dmem[15839] = 32'd0;
    dmem[15840] = 32'd0;
    dmem[15841] = 32'd0;
    dmem[15842] = 32'd0;
    dmem[15843] = 32'd0;
    dmem[15844] = 32'd0;
    dmem[15845] = 32'd0;
    dmem[15846] = 32'd0;
    dmem[15847] = 32'd0;
    dmem[15848] = 32'd0;
    dmem[15849] = 32'd0;
    dmem[15850] = 32'd0;
    dmem[15851] = 32'd0;
    dmem[15852] = 32'd0;
    dmem[15853] = 32'd0;
    dmem[15854] = 32'd0;
    dmem[15855] = 32'd0;
    dmem[15856] = 32'd0;
    dmem[15857] = 32'd0;
    dmem[15858] = 32'd0;
    dmem[15859] = 32'd0;
    dmem[15860] = 32'd0;
    dmem[15861] = 32'd0;
    dmem[15862] = 32'd0;
    dmem[15863] = 32'd0;
    dmem[15864] = 32'd0;
    dmem[15865] = 32'd0;
    dmem[15866] = 32'd0;
    dmem[15867] = 32'd0;
    dmem[15868] = 32'd0;
    dmem[15869] = 32'd0;
    dmem[15870] = 32'd0;
    dmem[15871] = 32'd0;
    dmem[15872] = 32'd0;
    dmem[15873] = 32'd0;
    dmem[15874] = 32'd0;
    dmem[15875] = 32'd0;
    dmem[15876] = 32'd0;
    dmem[15877] = 32'd0;
    dmem[15878] = 32'd0;
    dmem[15879] = 32'd0;
    dmem[15880] = 32'd0;
    dmem[15881] = 32'd0;
    dmem[15882] = 32'd0;
    dmem[15883] = 32'd0;
    dmem[15884] = 32'd0;
    dmem[15885] = 32'd0;
    dmem[15886] = 32'd0;
    dmem[15887] = 32'd0;
    dmem[15888] = 32'd0;
    dmem[15889] = 32'd0;
    dmem[15890] = 32'd0;
    dmem[15891] = 32'd0;
    dmem[15892] = 32'd0;
    dmem[15893] = 32'd0;
    dmem[15894] = 32'd0;
    dmem[15895] = 32'd0;
    dmem[15896] = 32'd0;
    dmem[15897] = 32'd0;
    dmem[15898] = 32'd0;
    dmem[15899] = 32'd0;
    dmem[15900] = 32'd0;
    dmem[15901] = 32'd0;
    dmem[15902] = 32'd0;
    dmem[15903] = 32'd0;
    dmem[15904] = 32'd0;
    dmem[15905] = 32'd0;
    dmem[15906] = 32'd0;
    dmem[15907] = 32'd0;
    dmem[15908] = 32'd0;
    dmem[15909] = 32'd0;
    dmem[15910] = 32'd0;
    dmem[15911] = 32'd0;
    dmem[15912] = 32'd0;
    dmem[15913] = 32'd0;
    dmem[15914] = 32'd0;
    dmem[15915] = 32'd0;
    dmem[15916] = 32'd0;
    dmem[15917] = 32'd0;
    dmem[15918] = 32'd0;
    dmem[15919] = 32'd0;
    dmem[15920] = 32'd0;
    dmem[15921] = 32'd0;
    dmem[15922] = 32'd0;
    dmem[15923] = 32'd0;
    dmem[15924] = 32'd0;
    dmem[15925] = 32'd0;
    dmem[15926] = 32'd0;
    dmem[15927] = 32'd0;
    dmem[15928] = 32'd0;
    dmem[15929] = 32'd0;
    dmem[15930] = 32'd0;
    dmem[15931] = 32'd0;
    dmem[15932] = 32'd0;
    dmem[15933] = 32'd0;
    dmem[15934] = 32'd0;
    dmem[15935] = 32'd0;
    dmem[15936] = 32'd0;
    dmem[15937] = 32'd0;
    dmem[15938] = 32'd0;
    dmem[15939] = 32'd0;
    dmem[15940] = 32'd0;
    dmem[15941] = 32'd0;
    dmem[15942] = 32'd0;
    dmem[15943] = 32'd0;
    dmem[15944] = 32'd0;
    dmem[15945] = 32'd0;
    dmem[15946] = 32'd0;
    dmem[15947] = 32'd0;
    dmem[15948] = 32'd0;
    dmem[15949] = 32'd0;
    dmem[15950] = 32'd0;
    dmem[15951] = 32'd0;
    dmem[15952] = 32'd0;
    dmem[15953] = 32'd0;
    dmem[15954] = 32'd0;
    dmem[15955] = 32'd0;
    dmem[15956] = 32'd0;
    dmem[15957] = 32'd0;
    dmem[15958] = 32'd0;
    dmem[15959] = 32'd0;
    dmem[15960] = 32'd0;
    dmem[15961] = 32'd0;
    dmem[15962] = 32'd0;
    dmem[15963] = 32'd0;
    dmem[15964] = 32'd0;
    dmem[15965] = 32'd0;
    dmem[15966] = 32'd0;
    dmem[15967] = 32'd0;
    dmem[15968] = 32'd0;
    dmem[15969] = 32'd0;
    dmem[15970] = 32'd0;
    dmem[15971] = 32'd0;
    dmem[15972] = 32'd0;
    dmem[15973] = 32'd0;
    dmem[15974] = 32'd0;
    dmem[15975] = 32'd0;
    dmem[15976] = 32'd0;
    dmem[15977] = 32'd0;
    dmem[15978] = 32'd0;
    dmem[15979] = 32'd0;
    dmem[15980] = 32'd0;
    dmem[15981] = 32'd0;
    dmem[15982] = 32'd0;
    dmem[15983] = 32'd0;
    dmem[15984] = 32'd0;
    dmem[15985] = 32'd0;
    dmem[15986] = 32'd0;
    dmem[15987] = 32'd0;
    dmem[15988] = 32'd0;
    dmem[15989] = 32'd0;
    dmem[15990] = 32'd0;
    dmem[15991] = 32'd0;
    dmem[15992] = 32'd0;
    dmem[15993] = 32'd0;
    dmem[15994] = 32'd0;
    dmem[15995] = 32'd0;
    dmem[15996] = 32'd0;
    dmem[15997] = 32'd0;
    dmem[15998] = 32'd0;
    dmem[15999] = 32'd0;
    dmem[16000] = 32'd0;
    dmem[16001] = 32'd0;
    dmem[16002] = 32'd0;
    dmem[16003] = 32'd0;
    dmem[16004] = 32'd0;
    dmem[16005] = 32'd0;
    dmem[16006] = 32'd0;
    dmem[16007] = 32'd0;
    dmem[16008] = 32'd0;
    dmem[16009] = 32'd0;
    dmem[16010] = 32'd0;
    dmem[16011] = 32'd0;
    dmem[16012] = 32'd0;
    dmem[16013] = 32'd0;
    dmem[16014] = 32'd0;
    dmem[16015] = 32'd0;
    dmem[16016] = 32'd0;
    dmem[16017] = 32'd0;
    dmem[16018] = 32'd0;
    dmem[16019] = 32'd0;
    dmem[16020] = 32'd0;
    dmem[16021] = 32'd0;
    dmem[16022] = 32'd0;
    dmem[16023] = 32'd0;
    dmem[16024] = 32'd0;
    dmem[16025] = 32'd0;
    dmem[16026] = 32'd0;
    dmem[16027] = 32'd0;
    dmem[16028] = 32'd0;
    dmem[16029] = 32'd0;
    dmem[16030] = 32'd0;
    dmem[16031] = 32'd0;
    dmem[16032] = 32'd0;
    dmem[16033] = 32'd0;
    dmem[16034] = 32'd0;
    dmem[16035] = 32'd0;
    dmem[16036] = 32'd0;
    dmem[16037] = 32'd0;
    dmem[16038] = 32'd0;
    dmem[16039] = 32'd0;
    dmem[16040] = 32'd0;
    dmem[16041] = 32'd0;
    dmem[16042] = 32'd0;
    dmem[16043] = 32'd0;
    dmem[16044] = 32'd0;
    dmem[16045] = 32'd0;
    dmem[16046] = 32'd0;
    dmem[16047] = 32'd0;
    dmem[16048] = 32'd0;
    dmem[16049] = 32'd0;
    dmem[16050] = 32'd0;
    dmem[16051] = 32'd0;
    dmem[16052] = 32'd0;
    dmem[16053] = 32'd0;
    dmem[16054] = 32'd0;
    dmem[16055] = 32'd0;
    dmem[16056] = 32'd0;
    dmem[16057] = 32'd0;
    dmem[16058] = 32'd0;
    dmem[16059] = 32'd0;
    dmem[16060] = 32'd0;
    dmem[16061] = 32'd0;
    dmem[16062] = 32'd0;
    dmem[16063] = 32'd0;
    dmem[16064] = 32'd0;
    dmem[16065] = 32'd0;
    dmem[16066] = 32'd0;
    dmem[16067] = 32'd0;
    dmem[16068] = 32'd0;
    dmem[16069] = 32'd0;
    dmem[16070] = 32'd0;
    dmem[16071] = 32'd0;
    dmem[16072] = 32'd0;
    dmem[16073] = 32'd0;
    dmem[16074] = 32'd0;
    dmem[16075] = 32'd0;
    dmem[16076] = 32'd0;
    dmem[16077] = 32'd0;
    dmem[16078] = 32'd0;
    dmem[16079] = 32'd0;
    dmem[16080] = 32'd0;
    dmem[16081] = 32'd0;
    dmem[16082] = 32'd0;
    dmem[16083] = 32'd0;
    dmem[16084] = 32'd0;
    dmem[16085] = 32'd0;
    dmem[16086] = 32'd0;
    dmem[16087] = 32'd0;
    dmem[16088] = 32'd0;
    dmem[16089] = 32'd0;
    dmem[16090] = 32'd0;
    dmem[16091] = 32'd0;
    dmem[16092] = 32'd0;
    dmem[16093] = 32'd0;
    dmem[16094] = 32'd0;
    dmem[16095] = 32'd0;
    dmem[16096] = 32'd0;
    dmem[16097] = 32'd0;
    dmem[16098] = 32'd0;
    dmem[16099] = 32'd0;
    dmem[16100] = 32'd0;
    dmem[16101] = 32'd0;
    dmem[16102] = 32'd0;
    dmem[16103] = 32'd0;
    dmem[16104] = 32'd0;
    dmem[16105] = 32'd0;
    dmem[16106] = 32'd0;
    dmem[16107] = 32'd0;
    dmem[16108] = 32'd0;
    dmem[16109] = 32'd0;
    dmem[16110] = 32'd0;
    dmem[16111] = 32'd0;
    dmem[16112] = 32'd0;
    dmem[16113] = 32'd0;
    dmem[16114] = 32'd0;
    dmem[16115] = 32'd0;
    dmem[16116] = 32'd0;
    dmem[16117] = 32'd0;
    dmem[16118] = 32'd0;
    dmem[16119] = 32'd0;
    dmem[16120] = 32'd0;
    dmem[16121] = 32'd0;
    dmem[16122] = 32'd0;
    dmem[16123] = 32'd0;
    dmem[16124] = 32'd0;
    dmem[16125] = 32'd0;
    dmem[16126] = 32'd0;
    dmem[16127] = 32'd0;
    dmem[16128] = 32'd0;
    dmem[16129] = 32'd0;
    dmem[16130] = 32'd0;
    dmem[16131] = 32'd0;
    dmem[16132] = 32'd0;
    dmem[16133] = 32'd0;
    dmem[16134] = 32'd0;
    dmem[16135] = 32'd0;
    dmem[16136] = 32'd0;
    dmem[16137] = 32'd0;
    dmem[16138] = 32'd0;
    dmem[16139] = 32'd0;
    dmem[16140] = 32'd0;
    dmem[16141] = 32'd0;
    dmem[16142] = 32'd0;
    dmem[16143] = 32'd0;
    dmem[16144] = 32'd0;
    dmem[16145] = 32'd0;
    dmem[16146] = 32'd0;
    dmem[16147] = 32'd0;
    dmem[16148] = 32'd0;
    dmem[16149] = 32'd0;
    dmem[16150] = 32'd0;
    dmem[16151] = 32'd0;
    dmem[16152] = 32'd0;
    dmem[16153] = 32'd0;
    dmem[16154] = 32'd0;
    dmem[16155] = 32'd0;
    dmem[16156] = 32'd0;
    dmem[16157] = 32'd0;
    dmem[16158] = 32'd0;
    dmem[16159] = 32'd0;
    dmem[16160] = 32'd0;
    dmem[16161] = 32'd0;
    dmem[16162] = 32'd0;
    dmem[16163] = 32'd0;
    dmem[16164] = 32'd0;
    dmem[16165] = 32'd0;
    dmem[16166] = 32'd0;
    dmem[16167] = 32'd0;
    dmem[16168] = 32'd0;
    dmem[16169] = 32'd0;
    dmem[16170] = 32'd0;
    dmem[16171] = 32'd0;
    dmem[16172] = 32'd0;
    dmem[16173] = 32'd0;
    dmem[16174] = 32'd0;
    dmem[16175] = 32'd0;
    dmem[16176] = 32'd0;
    dmem[16177] = 32'd0;
    dmem[16178] = 32'd0;
    dmem[16179] = 32'd0;
    dmem[16180] = 32'd0;
    dmem[16181] = 32'd0;
    dmem[16182] = 32'd0;
    dmem[16183] = 32'd0;
    dmem[16184] = 32'd0;
    dmem[16185] = 32'd0;
    dmem[16186] = 32'd0;
    dmem[16187] = 32'd0;
    dmem[16188] = 32'd0;
    dmem[16189] = 32'd0;
    dmem[16190] = 32'd0;
    dmem[16191] = 32'd0;
    dmem[16192] = 32'd0;
    dmem[16193] = 32'd0;
    dmem[16194] = 32'd0;
    dmem[16195] = 32'd0;
    dmem[16196] = 32'd0;
    dmem[16197] = 32'd0;
    dmem[16198] = 32'd0;
    dmem[16199] = 32'd0;
    dmem[16200] = 32'd0;
    dmem[16201] = 32'd0;
    dmem[16202] = 32'd0;
    dmem[16203] = 32'd0;
    dmem[16204] = 32'd0;
    dmem[16205] = 32'd0;
    dmem[16206] = 32'd0;
    dmem[16207] = 32'd0;
    dmem[16208] = 32'd0;
    dmem[16209] = 32'd0;
    dmem[16210] = 32'd0;
    dmem[16211] = 32'd0;
    dmem[16212] = 32'd0;
    dmem[16213] = 32'd0;
    dmem[16214] = 32'd0;
    dmem[16215] = 32'd0;
    dmem[16216] = 32'd0;
    dmem[16217] = 32'd0;
    dmem[16218] = 32'd0;
    dmem[16219] = 32'd0;
    dmem[16220] = 32'd0;
    dmem[16221] = 32'd0;
    dmem[16222] = 32'd0;
    dmem[16223] = 32'd0;
    dmem[16224] = 32'd0;
    dmem[16225] = 32'd0;
    dmem[16226] = 32'd0;
    dmem[16227] = 32'd0;
    dmem[16228] = 32'd0;
    dmem[16229] = 32'd0;
    dmem[16230] = 32'd0;
    dmem[16231] = 32'd0;
    dmem[16232] = 32'd0;
    dmem[16233] = 32'd0;
    dmem[16234] = 32'd0;
    dmem[16235] = 32'd0;
    dmem[16236] = 32'd0;
    dmem[16237] = 32'd0;
    dmem[16238] = 32'd0;
    dmem[16239] = 32'd0;
    dmem[16240] = 32'd0;
    dmem[16241] = 32'd0;
    dmem[16242] = 32'd0;
    dmem[16243] = 32'd0;
    dmem[16244] = 32'd0;
    dmem[16245] = 32'd0;
    dmem[16246] = 32'd0;
    dmem[16247] = 32'd0;
    dmem[16248] = 32'd0;
    dmem[16249] = 32'd0;
    dmem[16250] = 32'd0;
    dmem[16251] = 32'd0;
    dmem[16252] = 32'd0;
    dmem[16253] = 32'd0;
    dmem[16254] = 32'd0;
    dmem[16255] = 32'd0;
    dmem[16256] = 32'd0;
    dmem[16257] = 32'd0;
    dmem[16258] = 32'd0;
    dmem[16259] = 32'd0;
    dmem[16260] = 32'd0;
    dmem[16261] = 32'd0;
    dmem[16262] = 32'd0;
    dmem[16263] = 32'd0;
    dmem[16264] = 32'd0;
    dmem[16265] = 32'd0;
    dmem[16266] = 32'd0;
    dmem[16267] = 32'd0;
    dmem[16268] = 32'd0;
    dmem[16269] = 32'd0;
    dmem[16270] = 32'd0;
    dmem[16271] = 32'd0;
    dmem[16272] = 32'd0;
    dmem[16273] = 32'd0;
    dmem[16274] = 32'd0;
    dmem[16275] = 32'd0;
    dmem[16276] = 32'd0;
    dmem[16277] = 32'd0;
    dmem[16278] = 32'd0;
    dmem[16279] = 32'd0;
    dmem[16280] = 32'd0;
    dmem[16281] = 32'd0;
    dmem[16282] = 32'd0;
    dmem[16283] = 32'd0;
    dmem[16284] = 32'd0;
    dmem[16285] = 32'd0;
    dmem[16286] = 32'd0;
    dmem[16287] = 32'd0;
    dmem[16288] = 32'd0;
    dmem[16289] = 32'd0;
    dmem[16290] = 32'd0;
    dmem[16291] = 32'd0;
    dmem[16292] = 32'd0;
    dmem[16293] = 32'd0;
    dmem[16294] = 32'd0;
    dmem[16295] = 32'd0;
    dmem[16296] = 32'd0;
    dmem[16297] = 32'd0;
    dmem[16298] = 32'd0;
    dmem[16299] = 32'd0;
    dmem[16300] = 32'd0;
    dmem[16301] = 32'd0;
    dmem[16302] = 32'd0;
    dmem[16303] = 32'd0;
    dmem[16304] = 32'd0;
    dmem[16305] = 32'd0;
    dmem[16306] = 32'd0;
    dmem[16307] = 32'd0;
    dmem[16308] = 32'd0;
    dmem[16309] = 32'd0;
    dmem[16310] = 32'd0;
    dmem[16311] = 32'd0;
    dmem[16312] = 32'd0;
    dmem[16313] = 32'd0;
    dmem[16314] = 32'd0;
    dmem[16315] = 32'd0;
    dmem[16316] = 32'd0;
    dmem[16317] = 32'd0;
    dmem[16318] = 32'd0;
    dmem[16319] = 32'd0;
    dmem[16320] = 32'd0;
    dmem[16321] = 32'd0;
    dmem[16322] = 32'd0;
    dmem[16323] = 32'd0;
    dmem[16324] = 32'd0;
    dmem[16325] = 32'd0;
    dmem[16326] = 32'd0;
    dmem[16327] = 32'd0;
    dmem[16328] = 32'd0;
    dmem[16329] = 32'd0;
    dmem[16330] = 32'd0;
    dmem[16331] = 32'd0;
    dmem[16332] = 32'd0;
    dmem[16333] = 32'd0;
    dmem[16334] = 32'd0;
    dmem[16335] = 32'd0;
    dmem[16336] = 32'd0;
    dmem[16337] = 32'd0;
    dmem[16338] = 32'd0;
    dmem[16339] = 32'd0;
    dmem[16340] = 32'd0;
    dmem[16341] = 32'd0;
    dmem[16342] = 32'd0;
    dmem[16343] = 32'd0;
    dmem[16344] = 32'd0;
    dmem[16345] = 32'd0;
    dmem[16346] = 32'd0;
    dmem[16347] = 32'd0;
    dmem[16348] = 32'd0;
    dmem[16349] = 32'd0;
    dmem[16350] = 32'd0;
    dmem[16351] = 32'd0;
    dmem[16352] = 32'd0;
    dmem[16353] = 32'd0;
    dmem[16354] = 32'd0;
    dmem[16355] = 32'd0;
    dmem[16356] = 32'd0;
    dmem[16357] = 32'd0;
    dmem[16358] = 32'd0;
    dmem[16359] = 32'd0;
    dmem[16360] = 32'd0;
    dmem[16361] = 32'd0;
    dmem[16362] = 32'd0;
    dmem[16363] = 32'd0;
    dmem[16364] = 32'd0;
    dmem[16365] = 32'd0;
    dmem[16366] = 32'd0;
    dmem[16367] = 32'd0;
    dmem[16368] = 32'd0;
    dmem[16369] = 32'd0;
    dmem[16370] = 32'd0;
    dmem[16371] = 32'd0;
    dmem[16372] = 32'd0;
    dmem[16373] = 32'd0;
    dmem[16374] = 32'd0;
    dmem[16375] = 32'd0;
    dmem[16376] = 32'd0;
    dmem[16377] = 32'd0;
    dmem[16378] = 32'd0;
    dmem[16379] = 32'd0;
    dmem[16380] = 32'd0;
    dmem[16381] = 32'd0;
    dmem[16382] = 32'd0;
    dmem[16383] = 32'd0;
  end
  always @(posedge clk) begin
    if (dmem_wr__en)
      dmem[dmem_wr__addr] <= dmem_wr__data;
  end
  reg [31:0] _0_;
  always @(posedge clk) begin
    _0_ <= dmem[mem_addr];
  end
  assign mem_rd_data = _0_;
  assign any_ns_access = ns_rd_en | (* src = "/home/runner/workspace/hardware/ti60_f225.py:121" *) ns_wr_en;
  assign \$1  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:164" *) dmem_addr[31];
  assign is_mmio = dmem_addr[30] & (* src = "/home/runner/workspace/hardware/ti60_f225.py:164" *) \$1 ;
  assign is_mmio_write = is_mmio & (* src = "/home/runner/workspace/hardware/ti60_f225.py:193" *) dmem_wr_en;
  assign is_mmio_read = is_mmio & (* src = "/home/runner/workspace/hardware/ti60_f225.py:216" *) dmem_rd_en;
  assign \$2  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:226" *) busy;
  assign dmem_rd_data = is_mmio_read ? (* src = "/home/runner/workspace/hardware/ti60_f225.py:248" *) mmio_rd_data : mem_rd_data;
  assign dmem_rd_valid = _dmem_rd_valid_r | (* src = "/home/runner/workspace/hardware/ti60_f225.py:259" *) is_mmio_read;
  assign \$3  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:314" *) is_mmio;
  assign nia_changed = dbg_nia != (* src = "/home/runner/workspace/hardware/ti60_f225.py:334" *) prev_nia;
  assign step_complete = stepping & (* src = "/home/runner/workspace/hardware/ti60_f225.py:337" *) nia_changed;
  assign \$4  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:339" *) halted;
  assign \$5  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:339" *) step_complete;
  assign \$6  = stepping & (* src = "/home/runner/workspace/hardware/ti60_f225.py:339" *) \$5 ;
  assign imem_valid = \$4  | (* src = "/home/runner/workspace/hardware/ti60_f225.py:339" *) \$6 ;
  assign \$7  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:350" *) btn_sync[2];
  assign btn_press = btn_prev & (* src = "/home/runner/workspace/hardware/ti60_f225.py:350" *) \$7 ;
  assign \$8  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:387" *) busy;
  assign \$9  = mmio_uart_pending & (* src = "/home/runner/workspace/hardware/ti60_f225.py:387" *) \$8 ;
  assign \$10  = dbg_boot_complete & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) halted;
  assign \$11  = ! (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) demo_phase;
  assign demo_led0 = \$10  & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) \$11 ;
  assign \$12  = dbg_boot_complete & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) halted;
  assign \$13  = demo_phase == (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) 1'h1;
  assign demo_led1 = \$12  & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) \$13 ;
  assign \$14  = dbg_boot_complete & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) halted;
  assign \$15  = demo_phase == (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) 2'h2;
  assign demo_led2 = \$14  & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) \$15 ;
  assign \$16  = dbg_boot_complete & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) halted;
  assign \$17  = demo_phase == (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) 2'h3;
  assign demo_led3 = \$16  & (* src = "/home/runner/workspace/hardware/ti60_f225.py:429" *) \$17 ;
  assign \$18  = mmio_led0[0] | (* src = "/home/runner/workspace/hardware/ti60_f225.py:451" *) demo_led0;
  assign \$19  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:409" *) dbg_boot_complete;
  assign led0 = dbg_boot_complete ? (* src = "/home/runner/workspace/hardware/ti60_f225.py:450" *) \$18  : \$19 ;
  assign \$20  = mmio_led1[0] | (* src = "/home/runner/workspace/hardware/ti60_f225.py:454" *) demo_led1;
  assign \$21  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:412" *) fault_latched;
  assign \$22  = halted & (* src = "/home/runner/workspace/hardware/ti60_f225.py:412" *) \$21 ;
  assign \$23  = \$22  & (* src = "/home/runner/workspace/hardware/ti60_f225.py:412" *) heartbeat_blink;
  assign \$24  = \$20  | (* src = "/home/runner/workspace/hardware/ti60_f225.py:454" *) \$23 ;
  assign \$25  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:410" *) fault_latched;
  assign \$26  = dbg_boot_complete & (* src = "/home/runner/workspace/hardware/ti60_f225.py:410" *) \$25 ;
  assign \$27  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:410" *) halted;
  assign \$28  = \$26  & (* src = "/home/runner/workspace/hardware/ti60_f225.py:410" *) \$27 ;
  assign \$29  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:412" *) fault_latched;
  assign \$30  = halted & (* src = "/home/runner/workspace/hardware/ti60_f225.py:412" *) \$29 ;
  assign \$31  = \$30  & (* src = "/home/runner/workspace/hardware/ti60_f225.py:412" *) heartbeat_blink;
  assign \$32  = \$28  | (* src = "/home/runner/workspace/hardware/ti60_f225.py:455" *) \$31 ;
  assign led1 = dbg_boot_complete ? (* src = "/home/runner/workspace/hardware/ti60_f225.py:453" *) \$24  : \$32 ;
  assign \$33  = mmio_led2[0] | (* src = "/home/runner/workspace/hardware/ti60_f225.py:457" *) demo_led2;
  assign \$34  = \$33  | (* src = "/home/runner/workspace/hardware/ti60_f225.py:457" *) fault_latched;
  assign \$35  = \$34  | (* src = "/home/runner/workspace/hardware/ti60_f225.py:457" *) banner_ever_sent;
  assign \$36  = fault_latched | (* src = "/home/runner/workspace/hardware/ti60_f225.py:458" *) banner_ever_sent;
  assign led2 = dbg_boot_complete ? (* src = "/home/runner/workspace/hardware/ti60_f225.py:456" *) \$35  : \$36 ;
  assign \$37  = mmio_led3[0] | (* src = "/home/runner/workspace/hardware/ti60_f225.py:460" *) demo_led3;
  assign led3 = dbg_boot_complete ? (* src = "/home/runner/workspace/hardware/ti60_f225.py:459" *) \$37  : dbg_boot_complete;
  assign \$38  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:467" *) boot_triggered;
  assign \$39  = boot_delay == (* src = "/home/runner/workspace/hardware/ti60_f225.py:469" *) 4'hf;
  assign \$40  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:541" *) busy;
  assign \$41  = banner_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:542" *) 5'h12;
  assign \$42  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:553" *) busy;
  assign \$43  = callhome_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:554" *) 5'h11;
  assign \$44  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:564" *) busy;
  assign \$45  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:572" *) busy;
  assign \$46  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:581" *) busy;
  assign \$47  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:598" *) busy;
  assign \$48  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:606" *) 8'hbe;
  assign \$49  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:606" *) \$48 ;
  assign \$50  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:613" *) busy;
  assign \$51  = halt_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:614" *) 3'h6;
  assign \$52  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:630" *) 8'hbe;
  assign \$53  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:630" *) \$52 ;
  assign \$54  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:666" *) 8'hbe;
  assign \$55  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:666" *) \$54 ;
  assign \$56  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:682" *) 8'hbe;
  assign \$57  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:682" *) \$56 ;
  assign \$58  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:707" *) busy;
  assign \$59  = step_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:708" *) 2'h2;
  assign \$60  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:719" *) busy;
  assign \$61  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:732" *) busy;
  assign \$62  = fault_msg_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:733" *) 2'h2;
  assign \$63  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:744" *) busy;
  assign \$64  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:757" *) busy;
  assign \$65  = halt_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:758" *) 3'h6;
  assign \$66  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:775" *) 8'hef;
  assign \$67  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:781" *) 8'had;
  assign \$68  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:783" *) 8'haa;
  assign \$69  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:896" *) busy;
  assign \$70  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:906" *) busy;
  assign \$71  = pl_ack_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:907" *) 3'h4;
  assign \$73  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:959" *) busy;
  assign \$74  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:964" *) busy;
  assign \$75  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:969" *) busy;
  assign \$76  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:974" *) busy;
  assign \$77  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) debug_fsm_state;
  assign \$78  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$79  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$80  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$81  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$82  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$83  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$84  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$85  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$86  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$87  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$88  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign \$89  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$90  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$91  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'he;
  assign \$92  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hf;
  assign \$93  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h10;
  assign \$94  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h11;
  assign \$95  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h12;
  assign \$96  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h13;
  assign \$97  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h14;
  assign \$98  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h15;
  assign \$99  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h16;
  assign \$100  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h17;
  assign \$101  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h18;
  assign \$102  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h19;
  assign \$103  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1a;
  assign \$104  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1b;
  assign \$105  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1c;
  assign \$106  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1d;
  assign \$107  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1e;
  assign \$108  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1f;
  assign \$109  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h20;
  assign \$110  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h21;
  assign \$111  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h22;
  assign \$112  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h23;
  assign \$113  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h24;
  assign \$114  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h25;
  assign \$115  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h26;
  assign \$116  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h27;
  assign \$117  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h28;
  assign \$118  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h29;
  assign \$119  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h2a;
  assign \$120  = debug_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 6'h2b;
  assign \$121  = timer_lo == (* src = "/home/runner/workspace/hardware/ti60_f225.py:184" *) 32'd4294967295;
  assign \$122  = timer_hi + (* src = "/home/runner/workspace/hardware/ti60_f225.py:185" *) 1'h1;
  assign \$123  = timer_lo + (* src = "/home/runner/workspace/hardware/ti60_f225.py:186" *) 1'h1;
  assign \$124  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:188" *) alarm_fired;
  assign \$125  = alarm_armed & (* src = "/home/runner/workspace/hardware/ti60_f225.py:188" *) \$124 ;
  assign \$126  = timer_lo == (* src = "/home/runner/workspace/hardware/ti60_f225.py:189" *) alarm_cmp;
  assign \$127  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:258" *) is_mmio;
  assign \$128  = dmem_rd_en & (* src = "/home/runner/workspace/hardware/ti60_f225.py:258" *) \$127 ;
  assign \$129  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:289" *) pl_active;
  assign \$130  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:289" *) \$129 ;
  assign \$131  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:356" *) btn_sync[2];
  assign \$132  = btn_hold_ctr < (* src = "/home/runner/workspace/hardware/ti60_f225.py:357" *) 25'h17d7840;
  assign \$133  = btn_hold_ctr + (* src = "/home/runner/workspace/hardware/ti60_f225.py:358" *) 1'h1;
  assign \$134  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:387" *) busy;
  assign \$135  = mmio_uart_pending & (* src = "/home/runner/workspace/hardware/ti60_f225.py:387" *) \$134 ;
  assign \$136  = heartbeat_ctr + (* src = "/home/runner/workspace/hardware/ti60_f225.py:402" *) 1'h1;
  assign \$137  = heartbeat_ctr == (* src = "/home/runner/workspace/hardware/ti60_f225.py:403" *) 25'h17d783f;
  assign \$138  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:404" *) heartbeat_blink;
  assign \$139  = fault_latched | (* src = "/home/runner/workspace/hardware/ti60_f225.py:407" *) dbg_fault_valid;
  assign \$140  = demo_ctr == (* src = "/home/runner/workspace/hardware/ti60_f225.py:432" *) 24'hbebc1f;
  assign \$141  = demo_phase == (* src = "/home/runner/workspace/hardware/ti60_f225.py:434" *) 3'h4;
  assign \$142  = demo_phase + (* src = "/home/runner/workspace/hardware/ti60_f225.py:437" *) 1'h1;
  assign \$143  = demo_ctr + (* src = "/home/runner/workspace/hardware/ti60_f225.py:439" *) 1'h1;
  assign \$144  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:467" *) boot_triggered;
  assign \$145  = boot_delay + (* src = "/home/runner/workspace/hardware/ti60_f225.py:468" *) 1'h1;
  assign \$146  = boot_delay == (* src = "/home/runner/workspace/hardware/ti60_f225.py:469" *) 4'hf;
  assign \$147  = startup_ctr + (* src = "/home/runner/workspace/hardware/ti60_f225.py:527" *) 1'h1;
  assign \$148  = startup_ctr == (* src = "/home/runner/workspace/hardware/ti60_f225.py:528" *) 27'h47868bf;
  assign \$149  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:541" *) busy;
  assign \$150  = banner_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:542" *) 5'h12;
  assign \$151  = banner_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:547" *) 1'h1;
  assign \$152  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:553" *) busy;
  assign \$153  = callhome_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:554" *) 5'h11;
  assign \$154  = callhome_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:559" *) 1'h1;
  assign \$155  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:564" *) busy;
  assign \$156  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:572" *) busy;
  assign \$157  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:581" *) busy;
  assign \$158  = fault_nia_idx == (* src = "/home/runner/workspace/hardware/ti60_f225.py:592" *) 2'h3;
  assign \$159  = fault_nia_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:595" *) 1'h1;
  assign \$160  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:598" *) busy;
  assign \$161  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:606" *) 8'hbe;
  assign \$162  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:606" *) \$161 ;
  assign \$163  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:613" *) busy;
  assign \$164  = halt_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:614" *) 3'h6;
  assign \$165  = halt_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:619" *) 1'h1;
  assign \$166  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:630" *) 8'hbe;
  assign \$167  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:630" *) \$166 ;
  assign \$168  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:666" *) 8'hbe;
  assign \$169  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:666" *) \$168 ;
  assign \$170  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:682" *) 8'hbe;
  assign \$171  = valid & (* src = "/home/runner/workspace/hardware/ti60_f225.py:682" *) \$170 ;
  assign \$172  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:707" *) busy;
  assign \$173  = step_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:708" *) 2'h2;
  assign \$174  = step_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:713" *) 1'h1;
  assign \$175  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:719" *) busy;
  assign \$176  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:732" *) busy;
  assign \$177  = fault_msg_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:733" *) 2'h2;
  assign \$178  = fault_msg_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:738" *) 1'h1;
  assign \$179  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:744" *) busy;
  assign \$180  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:757" *) busy;
  assign \$181  = halt_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:758" *) 3'h6;
  assign \$182  = halt_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:763" *) 1'h1;
  assign \$183  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:775" *) 8'hef;
  assign \$184  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:781" *) 8'had;
  assign \$185  = \data$123  == (* src = "/home/runner/workspace/hardware/ti60_f225.py:783" *) 8'haa;
  assign \$186  = pl_cur_addr + (* src = "/home/runner/workspace/hardware/ti60_f225.py:864" *) 1'h1;
  assign \$187  = pl_count == (* src = "/home/runner/workspace/hardware/ti60_f225.py:865" *) 1'h1;
  assign \$188  = pl_count - (* src = "/home/runner/workspace/hardware/ti60_f225.py:869" *) 1'h1;
  assign \$189  = \data$123  != (* src = "/home/runner/workspace/hardware/ti60_f225.py:876" *) crc[15:8];
  assign \$190  = \data$123  != (* src = "/home/runner/workspace/hardware/ti60_f225.py:882" *) crc[7:0];
  assign \$191  = pl_crc_fail | (* src = "/home/runner/workspace/hardware/ti60_f225.py:882" *) \$190 ;
  assign \$192  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:896" *) busy;
  assign \$193  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:906" *) busy;
  assign \$194  = pl_ack_idx < (* src = "/home/runner/workspace/hardware/ti60_f225.py:907" *) 3'h4;
  assign \$195  = pl_ack_idx + (* src = "/home/runner/workspace/hardware/ti60_f225.py:912" *) 1'h1;
  assign \$196  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:959" *) busy;
  assign \$197  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:964" *) busy;
  assign \$198  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:969" *) busy;
  assign \$199  = ~ (* src = "/home/runner/workspace/hardware/ti60_f225.py:974" *) busy;
  assign \$200  = rb_count - (* src = "/home/runner/workspace/hardware/ti60_f225.py:977" *) 1'h1;
  assign \$201  = rb_cur_addr + (* src = "/home/runner/workspace/hardware/ti60_f225.py:978" *) 1'h1;
  assign \$202  = rb_count == (* src = "/home/runner/workspace/hardware/ti60_f225.py:980" *) 1'h1;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:178" *)
  always @(posedge clk)
    timer_hi <= \$203 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:177" *)
  always @(posedge clk)
    timer_lo <= \$123 [31:0];
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:182" *)
  always @(posedge clk)
    alarm_fired <= \$204 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  always @(posedge clk)
    mmio_led0 <= \$205 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  always @(posedge clk)
    mmio_led1 <= \$206 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  always @(posedge clk)
    mmio_led2 <= \$207 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  always @(posedge clk)
    mmio_led3 <= \$208 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:169" *)
  always @(posedge clk)
    mmio_led4 <= \$209 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:179" *)
  always @(posedge clk)
    tod_epoch <= \$210 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:180" *)
  always @(posedge clk)
    alarm_cmp <= \$211 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:181" *)
  always @(posedge clk)
    alarm_armed <= \$212 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:257" *)
  always @(posedge clk)
    _dmem_rd_valid_r <= \$128 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:173" *)
  always @(posedge clk)
    mmio_rx_data <= \$213 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:174" *)
  always @(posedge clk)
    mmio_rx_valid <= \$214 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:331" *)
  always @(posedge clk)
    prev_nia <= dbg_nia;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:341" *)
  always @(posedge clk)
    btn_sync <= \$215 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:342" *)
  always @(posedge clk)
    btn_prev <= btn_sync[2];
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:354" *)
  always @(posedge clk)
    btn_hold_ctr <= \$216 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:355" *)
  always @(posedge clk)
    btn_hold_done <= \$217 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:376" *)
  always @(posedge clk)
    mmio_uart_pending <= \$218 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:377" *)
  always @(posedge clk)
    mmio_uart_byte_reg <= \$219 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:400" *)
  always @(posedge clk)
    heartbeat_ctr <= \$220 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:401" *)
  always @(posedge clk)
    heartbeat_blink <= \$221 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:263" *)
  always @(posedge clk)
    fault_latched <= \$139 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:422" *)
  always @(posedge clk)
    demo_ctr <= \$222 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:423" *)
  always @(posedge clk)
    demo_phase <= \$223 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:464" *)
  always @(posedge clk)
    boot_delay <= \$224 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:465" *)
  always @(posedge clk)
    boot_triggered <= \$225 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:523" *)
  always @(posedge clk)
    startup_ctr <= \$226 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    debug_fsm_state <= \$227 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:478" *)
  always @(posedge clk)
    banner_idx <= \$228 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:261" *)
  always @(posedge clk)
    halted <= \$229 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:446" *)
  always @(posedge clk)
    banner_ever_sent <= \$230 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:491" *)
  always @(posedge clk)
    callhome_idx <= \$231 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:513" *)
  always @(posedge clk)
    fault_nia_idx <= \$232 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:275" *)
  always @(posedge clk)
    pl_active <= \$233 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:496" *)
  always @(posedge clk)
    halt_idx <= \$234 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:262" *)
  always @(posedge clk)
    stepping <= \$235 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:511" *)
  always @(posedge clk)
    last_fault_code <= \$236 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:510" *)
  always @(posedge clk)
    boot_reason <= \$237 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:512" *)
  always @(posedge clk)
    fault_nia <= \$238 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:515" *)
  always @(posedge clk)
    step_nia <= \$239 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:516" *)
  always @(posedge clk)
    step_fault <= \$240 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:517" *)
  always @(posedge clk)
    step_had_fault <= \$241 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:501" *)
  always @(posedge clk)
    step_idx <= \$242 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:506" *)
  always @(posedge clk)
    fault_msg_idx <= \$243 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:276" *)
  always @(posedge clk)
    pl_addr <= \$244 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:277" *)
  always @(posedge clk)
    pl_total_count <= \$245 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:278" *)
  always @(posedge clk)
    pl_count <= \$246 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:280" *)
  always @(posedge clk)
    pl_cur_addr <= \$247 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:279" *)
  always @(posedge clk)
    pl_word <= \$248 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:281" *)
  always @(posedge clk)
    pl_crc_hi_buf <= \$249 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:282" *)
  always @(posedge clk)
    pl_crc_fail <= \$250 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  always @(posedge clk)
    pl_ack0 <= \$251 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  always @(posedge clk)
    pl_ack1 <= \$252 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  always @(posedge clk)
    pl_ack2 <= \$253 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:283" *)
  always @(posedge clk)
    pl_ack3 <= \$254 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:284" *)
  always @(posedge clk)
    pl_ack_idx <= \$255 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:304" *)
  always @(posedge clk)
    rb_addr <= \$256 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:305" *)
  always @(posedge clk)
    rb_count <= \$257 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:128" *)
  always @(posedge clk)
    rb_cur_addr <= \$258 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:306" *)
  always @(posedge clk)
    rb_word <= \$259 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:68" *)
  \top.boot_rom  boot_rom (
    .clk(clk),
    .addr(dbg_nia[11:2]),
    .data(imem_data)
  );
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:61" *)
  \top.core  core (
    .clk(clk),
    .boot_complete(dbg_boot_complete),
    .boot_start(boot_start),
    .clist_addr(clist_addr),
    .clist_wr_data(clist_wr_data),
    .clist_wr_en(clist_wr_en),
    .dmem_addr(dmem_addr),
    .dmem_rd_en(dmem_rd_en),
    .dmem_wr_data(dmem_wr_data),
    .dmem_wr_en(dmem_wr_en),
    .\fault$639 (fault),
    .\fault_valid$640 (dbg_fault_valid),
    .free_run_nia(free_run_nia),
    .free_run_start(free_run_start),
    .halt_valid(halt_valid),
    .imem_addr(dbg_nia),
    .imem_valid(imem_valid),
    .instruction(imem_data),
    .mem_rd_data(dmem_rd_data),
    .mem_rd_valid(dmem_rd_valid),
    .ns_addr(ns_addr),
    .ns_rd_en(ns_rd_en),
    .ns_wr_data(ns_wr_data),
    .ns_wr_en(ns_wr_en),
    .\port$4577$0 (mem_rd_data)
  );
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:287" *)
  \top.crc_mod  crc_mod (
    .clk(clk),
    .crc(crc),
    .data_in(data_in),
    .reset(reset),
    .valid(\valid$131 )
  );
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:71" *)
  \top.debug  debug (
    .clk(clk),
    .busy(busy),
    .byte_data(byte_data),
    .\data$15 (\data$120 ),
    .send(send),
    .send_byte(send_byte),
    .tx(uart_tx)
  );
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:74" *)
  \top.uart_rx_mod  uart_rx_mod (
    .clk(clk),
    .data(\data$123 ),
    .rx(uart_rx),
    .valid(valid)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    banner_byte = 8'h00;
    casez (banner_idx)
      5'h00:
          banner_byte = 8'h43;
      5'h01:
          banner_byte = 8'h48;
      5'h02:
          banner_byte = 8'h55;
      5'h03:
          banner_byte = 8'h52;
      5'h04:
          banner_byte = 8'h43;
      5'h05:
          banner_byte = 8'h48;
      5'h06:
          banner_byte = 8'h20;
      5'h07:
          banner_byte = 8'h54;
      5'h08:
          banner_byte = 8'h69;
      5'h09:
          banner_byte = 8'h36;
      5'h0a:
          banner_byte = 8'h30;
      5'h0b:
          banner_byte = 8'h20;
      5'h0c:
          banner_byte = 8'h76;
      5'h0d:
          banner_byte = 8'h31;
      5'h0e:
          banner_byte = 8'h2e;
      5'h0f:
          banner_byte = 8'h30;
      5'h10:
          banner_byte = 8'h0d;
      5'h11:
          banner_byte = 8'h0a;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    callhome_byte = 8'h00;
    casez (callhome_idx)
      5'h00:
          callhome_byte = 8'hce;
      5'h01:
          callhome_byte = 8'h11;
      5'h02:
          callhome_byte = 8'h03;
      5'h03:
          callhome_byte = 8'h01;
      5'h04:
          callhome_byte = 8'h00;
      5'h05:
          callhome_byte = 8'h00;
      5'h06:
          callhome_byte = 8'h00;
      5'h07:
          callhome_byte = 8'h00;
      5'h08:
          callhome_byte = 8'h00;
      5'h09:
          callhome_byte = 8'h54;
      5'h0a:
          callhome_byte = 8'h69;
      5'h0b:
          callhome_byte = 8'h36;
      5'h0c:
          callhome_byte = 8'h30;
      5'h0d:
          callhome_byte = 8'h46;
      5'h0e:
          callhome_byte = 8'h00;
      5'h0f:
          callhome_byte = 8'h00;
      5'h10:
          callhome_byte = 8'h01;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    halt_byte = 8'h00;
    casez (halt_idx)
      3'h0:
          halt_byte = 8'h48;
      3'h1:
          halt_byte = 8'h41;
      3'h2:
          halt_byte = 8'h4c;
      3'h3:
          halt_byte = 8'h54;
      3'h4:
          halt_byte = 8'h0d;
      3'h5:
          halt_byte = 8'h0a;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    step_byte = 8'h00;
    casez (step_idx)
      2'h0:
          step_byte = 8'h53;
      2'h1:
          step_byte = 8'h3a;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    fault_byte = 8'h00;
    casez (fault_msg_idx)
      2'h0:
          fault_byte = 8'h46;
      2'h1:
          fault_byte = 8'h3a;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$72  = 8'h00;
    casez (pl_ack_idx)
      3'h0:
          \$72  = pl_ack0;
      3'h1:
          \$72  = pl_ack1;
      3'h2:
          \$72  = pl_ack2;
      3'h3:
          \$72  = pl_ack3;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    (* full_case = 32'd1 *)
    if (rb_rd_en) begin
      mem_addr = rb_cur_addr[13:0];
    end else if (any_ns_access) begin
      mem_addr = ns_addr[15:2];
    end else if (any_clist_access) begin
      mem_addr = clist_addr[15:2];
    end else begin
      mem_addr = dmem_addr[15:2];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    mmio_uart_tx_wr = 1'h0;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            /* empty */;
        4'h4:
            /* empty */;
        4'h5:
            mmio_uart_tx_wr = 1'h1;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    mmio_uart_tx_data = 8'h00;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            /* empty */;
        4'h4:
            /* empty */;
        4'h5:
            mmio_uart_tx_data = dmem_wr_data[7:0];
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    (* full_case = 32'd1 *)
    casez (dmem_addr[5:2])
      4'h0:
          mmio_rd_data = { 29'h00000000, mmio_led0 };
      4'h1:
          mmio_rd_data = { 29'h00000000, mmio_led1 };
      4'h2:
          mmio_rd_data = { 29'h00000000, mmio_led2 };
      4'h3:
          mmio_rd_data = { 29'h00000000, mmio_led3 };
      4'h4:
          mmio_rd_data = { 29'h00000000, mmio_led4 };
      4'h5:
          mmio_rd_data = 32'd0;
      4'h6:
          mmio_rd_data = { 30'h00000000, mmio_rx_valid, \$2  };
      4'h7:
          mmio_rd_data = { 24'h000000, mmio_rx_data };
      4'ha:
          mmio_rd_data = { 31'h00000000, push_button };
      4'hb:
          mmio_rd_data = timer_lo;
      4'hc:
          mmio_rd_data = timer_hi;
      4'hd:
          mmio_rd_data = tod_epoch;
      4'he:
          mmio_rd_data = alarm_cmp;
      4'hf:
          mmio_rd_data = { 30'h00000000, alarm_fired, alarm_armed };
      default:
          mmio_rd_data = 32'd0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    mmio_rx_read = 1'h0;
    casez (dmem_addr[5:2])
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          mmio_rx_read = is_mmio_read;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    pl_wr_en = 1'h0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          pl_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    pl_wr_addr = 14'h0000;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          pl_wr_addr = pl_cur_addr[13:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    pl_wr_data = 32'd0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          pl_wr_data = pl_word;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    cpu_wr_data = 32'd0;
    if (ns_wr_en) begin
      cpu_wr_data = ns_wr_data[31:0];
    end else if (clist_wr_en) begin
      cpu_wr_data = clist_wr_data;
    end else if (\$3 ) begin
      cpu_wr_data = dmem_wr_data;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    cpu_wr_en = 1'h0;
    if (ns_wr_en) begin
      cpu_wr_en = 1'h1;
    end else if (clist_wr_en) begin
      cpu_wr_en = 1'h1;
    end else if (\$3 ) begin
      cpu_wr_en = dmem_wr_en;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    (* full_case = 32'd1 *)
    if (pl_wr_en) begin
      dmem_wr__addr = pl_wr_addr;
    end else begin
      dmem_wr__addr = mem_addr;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    (* full_case = 32'd1 *)
    if (pl_wr_en) begin
      dmem_wr__data = pl_wr_data;
    end else begin
      dmem_wr__data = cpu_wr_data;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    (* full_case = 32'd1 *)
    if (pl_wr_en) begin
      dmem_wr__en = 1'h1;
    end else begin
      dmem_wr__en = cpu_wr_en;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    free_run_start = 1'h0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          free_run_start = 1'h1;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          if (valid) begin
            if (\$66 ) begin
            end else if (\$67 ) begin
            end else if (\$68 ) begin
              free_run_start = 1'h1;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    free_run_nia = 32'd0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          free_run_nia = 32'd0;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          if (valid) begin
            if (\$66 ) begin
            end else if (\$67 ) begin
            end else if (\$68 ) begin
              free_run_nia = 32'd0;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    send_byte = 1'h0;
    if (fsm_send_byte) begin
      send_byte = 1'h1;
    end else if (\$9 ) begin
      send_byte = 1'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    byte_data = 8'h00;
    if (fsm_send_byte) begin
      byte_data = fsm_byte_data;
    end else if (\$9 ) begin
      byte_data = mmio_uart_byte_reg;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    boot_start = 1'h0;
    (* full_case = 32'd1 *)
    if (\$38 ) begin
      if (\$39 ) begin
        boot_start = 1'h1;
      end
    end else begin
      boot_start = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    fsm_byte_data = 8'h00;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          if (\$40 ) begin
            if (\$41 ) begin
              fsm_byte_data = banner_byte;
            end
          end
      6'h03:
          if (\$42 ) begin
            if (\$43 ) begin
              fsm_byte_data = callhome_byte;
            end
          end
      6'h04:
          if (\$44 ) begin
            fsm_byte_data = boot_reason;
          end
      6'h05:
          if (\$45 ) begin
            fsm_byte_data = last_fault_code;
          end
      6'h06:
          if (\$46 ) begin
            (* full_case = 32'd1 *)
            casez (fault_nia_idx)
              2'h0:
                  fsm_byte_data = fault_nia[31:24];
              2'h1:
                  fsm_byte_data = fault_nia[23:16];
              2'h2:
                  fsm_byte_data = fault_nia[15:8];
              default:
                  fsm_byte_data = fault_nia[7:0];
            endcase
          end
      6'h08:
          /* empty */;
      6'h09:
          if (\$49 ) begin
          end else if (\$50 ) begin
            if (\$51 ) begin
              fsm_byte_data = halt_byte;
            end
          end
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          if (\$58 ) begin
            if (\$59 ) begin
              fsm_byte_data = step_byte;
            end
          end
      6'h11:
          /* empty */;
      6'h12:
          if (\$61 ) begin
            if (\$62 ) begin
              fsm_byte_data = fault_byte;
            end
          end
      6'h13:
          /* empty */;
      6'h0f:
          if (\$64 ) begin
            if (\$65 ) begin
              fsm_byte_data = halt_byte;
            end
          end
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          if (\$69 ) begin
            fsm_byte_data = 8'h15;
          end
      6'h22:
          if (\$70 ) begin
            if (\$71 ) begin
              fsm_byte_data = \$72 ;
            end
          end
      6'h15:
          /* empty */;
      6'h23:
          /* empty */;
      6'h24:
          /* empty */;
      6'h25:
          /* empty */;
      6'h26:
          /* empty */;
      6'h27:
          /* empty */;
      6'h28:
          if (\$73 ) begin
            fsm_byte_data = rb_word[7:0];
          end
      6'h29:
          if (\$74 ) begin
            fsm_byte_data = rb_word[15:8];
          end
      6'h2a:
          if (\$75 ) begin
            fsm_byte_data = rb_word[23:16];
          end
      6'h2b:
          if (\$76 ) begin
            fsm_byte_data = rb_word[31:24];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    fsm_send_byte = 1'h0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          if (\$40 ) begin
            if (\$41 ) begin
              fsm_send_byte = 1'h1;
            end
          end
      6'h03:
          if (\$42 ) begin
            if (\$43 ) begin
              fsm_send_byte = 1'h1;
            end
          end
      6'h04:
          if (\$44 ) begin
            fsm_send_byte = 1'h1;
          end
      6'h05:
          if (\$45 ) begin
            fsm_send_byte = 1'h1;
          end
      6'h06:
          if (\$46 ) begin
            fsm_send_byte = 1'h1;
          end
      6'h08:
          /* empty */;
      6'h09:
          if (\$49 ) begin
          end else if (\$50 ) begin
            if (\$51 ) begin
              fsm_send_byte = 1'h1;
            end
          end
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          if (\$58 ) begin
            if (\$59 ) begin
              fsm_send_byte = 1'h1;
            end
          end
      6'h11:
          /* empty */;
      6'h12:
          if (\$61 ) begin
            if (\$62 ) begin
              fsm_send_byte = 1'h1;
            end
          end
      6'h13:
          /* empty */;
      6'h0f:
          if (\$64 ) begin
            if (\$65 ) begin
              fsm_send_byte = 1'h1;
            end
          end
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          if (\$69 ) begin
            fsm_send_byte = 1'h1;
          end
      6'h22:
          if (\$70 ) begin
            if (\$71 ) begin
              fsm_send_byte = 1'h1;
            end
          end
      6'h15:
          /* empty */;
      6'h23:
          /* empty */;
      6'h24:
          /* empty */;
      6'h25:
          /* empty */;
      6'h26:
          /* empty */;
      6'h27:
          /* empty */;
      6'h28:
          if (\$73 ) begin
            fsm_send_byte = 1'h1;
          end
      6'h29:
          if (\$74 ) begin
            fsm_send_byte = 1'h1;
          end
      6'h2a:
          if (\$75 ) begin
            fsm_send_byte = 1'h1;
          end
      6'h2b:
          if (\$76 ) begin
            fsm_send_byte = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \data$120  = 32'd0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          if (\$47 ) begin
            \data$120  = dbg_nia;
          end
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          if (\$60 ) begin
            \data$120  = step_nia;
          end
      6'h12:
          /* empty */;
      6'h13:
          if (\$63 ) begin
            \data$120  = fault_word;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    send = 1'h0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          if (\$47 ) begin
            send = 1'h1;
          end
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          if (\$60 ) begin
            send = 1'h1;
          end
      6'h12:
          /* empty */;
      6'h13:
          if (\$63 ) begin
            send = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    reset = 1'h0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          if (\$49 ) begin
            reset = 1'h1;
          end
      6'h0b:
          if (btn_hold_done) begin
          end else if (\$53 ) begin
            reset = 1'h1;
          end
      6'h07:
          /* empty */;
      6'h0d:
          if (dbg_fault_valid) begin
          end else if (halt_valid) begin
          end else if (\$55 ) begin
            reset = 1'h1;
          end
      6'h0e:
          if (\$57 ) begin
            reset = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    fault_word = 32'd0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          if (\$63 ) begin
            fault_word = { 28'h0000000, step_fault };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    data_in = 8'h00;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          if (valid) begin
            if (\$66 ) begin
              data_in = 8'hbe;
            end
          end
      6'h14:
          data_in = 8'hef;
      6'h16:
          if (valid) begin
            data_in = \data$123 ;
          end
      6'h17:
          if (valid) begin
            data_in = \data$123 ;
          end
      6'h18:
          if (valid) begin
            data_in = \data$123 ;
          end
      6'h19:
          if (valid) begin
            data_in = \data$123 ;
          end
      6'h1a:
          if (valid) begin
            data_in = \data$123 ;
          end
      6'h1b:
          if (valid) begin
            data_in = \data$123 ;
          end
      6'h1c:
          if (valid) begin
            data_in = \data$123 ;
          end
      6'h1d:
          if (valid) begin
            data_in = \data$123 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \valid$131  = 1'h0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          if (valid) begin
            if (\$66 ) begin
              \valid$131  = 1'h1;
            end
          end
      6'h14:
          \valid$131  = 1'h1;
      6'h16:
          if (valid) begin
            \valid$131  = 1'h1;
          end
      6'h17:
          if (valid) begin
            \valid$131  = 1'h1;
          end
      6'h18:
          if (valid) begin
            \valid$131  = 1'h1;
          end
      6'h19:
          if (valid) begin
            \valid$131  = 1'h1;
          end
      6'h1a:
          if (valid) begin
            \valid$131  = 1'h1;
          end
      6'h1b:
          if (valid) begin
            \valid$131  = 1'h1;
          end
      6'h1c:
          if (valid) begin
            \valid$131  = 1'h1;
          end
      6'h1d:
          if (valid) begin
            \valid$131  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    rb_rd_en = 1'h0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          /* empty */;
      6'h22:
          /* empty */;
      6'h15:
          /* empty */;
      6'h23:
          /* empty */;
      6'h24:
          /* empty */;
      6'h25:
          /* empty */;
      6'h26:
          rb_rd_en = 1'h1;
      6'h27:
          rb_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$203  = timer_hi;
    if (\$121 ) begin
      \$203  = \$122 [31:0];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$204  = alarm_fired;
    if (\$125 ) begin
      if (\$126 ) begin
        \$204  = 1'h1;
      end
    end
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            /* empty */;
        4'h4:
            /* empty */;
        4'h5:
            /* empty */;
        4'hd:
            /* empty */;
        4'he:
            /* empty */;
        4'hf:
            if (dmem_wr_data[1]) begin
              \$204  = 1'h0;
            end
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$205  = mmio_led0;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            \$205  = dmem_wr_data[2:0];
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$206  = mmio_led1;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            \$206  = dmem_wr_data[2:0];
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$207  = mmio_led2;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            \$207  = dmem_wr_data[2:0];
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$208  = mmio_led3;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            \$208  = dmem_wr_data[2:0];
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$209  = mmio_led4;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            /* empty */;
        4'h4:
            \$209  = dmem_wr_data[2:0];
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$210  = tod_epoch;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            /* empty */;
        4'h4:
            /* empty */;
        4'h5:
            /* empty */;
        4'hd:
            \$210  = dmem_wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$211  = alarm_cmp;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            /* empty */;
        4'h4:
            /* empty */;
        4'h5:
            /* empty */;
        4'hd:
            /* empty */;
        4'he:
            \$211  = dmem_wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$212  = alarm_armed;
    if (is_mmio_write) begin
      casez (dmem_addr[5:2])
        4'h0:
            /* empty */;
        4'h1:
            /* empty */;
        4'h2:
            /* empty */;
        4'h3:
            /* empty */;
        4'h4:
            /* empty */;
        4'h5:
            /* empty */;
        4'hd:
            /* empty */;
        4'he:
            /* empty */;
        4'hf:
            if (dmem_wr_data[0]) begin
              \$212  = 1'h1;
            end
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$213  = mmio_rx_data;
    if (\$130 ) begin
      \$213  = \data$123 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$214  = mmio_rx_valid;
    if (\$130 ) begin
      \$214  = 1'h1;
    end else if (mmio_rx_read) begin
      \$214  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$216  = btn_hold_ctr;
    (* full_case = 32'd1 *)
    if (\$131 ) begin
      if (\$132 ) begin
        \$216  = \$133 [24:0];
      end
    end else begin
      \$216  = 25'h0000000;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$217  = btn_hold_done;
    (* full_case = 32'd1 *)
    if (\$131 ) begin
      (* full_case = 32'd1 *)
      if (\$132 ) begin
      end else begin
        \$217  = 1'h1;
      end
    end else begin
      \$217  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$218  = mmio_uart_pending;
    if (mmio_uart_tx_wr) begin
      \$218  = 1'h1;
    end
    if (fsm_send_byte) begin
    end else if (\$135 ) begin
      \$218  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$219  = mmio_uart_byte_reg;
    if (mmio_uart_tx_wr) begin
      \$219  = mmio_uart_tx_data;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$220  = \$136 [24:0];
    if (\$137 ) begin
      \$220  = 25'h0000000;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$221  = heartbeat_blink;
    if (\$137 ) begin
      \$221  = \$138 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$222  = demo_ctr;
    if (dbg_boot_complete) begin
      (* full_case = 32'd1 *)
      if (\$140 ) begin
        \$222  = 24'h000000;
      end else begin
        \$222  = \$143 [23:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$223  = demo_phase;
    if (dbg_boot_complete) begin
      if (\$140 ) begin
        (* full_case = 32'd1 *)
        if (\$141 ) begin
          \$223  = 3'h0;
        end else begin
          \$223  = \$142 [2:0];
        end
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$224  = boot_delay;
    if (\$144 ) begin
      \$224  = \$145 [3:0];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$225  = boot_triggered;
    if (\$144 ) begin
      if (\$146 ) begin
        \$225  = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$226  = startup_ctr;
    casez (debug_fsm_state)
      6'h00:
          \$226  = \$147 [27:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$227  = debug_fsm_state;
    casez (debug_fsm_state)
      6'h00:
          if (\$148 ) begin
            \$227  = 6'h01;
          end
      6'h01:
          if (dbg_boot_complete) begin
            \$227  = 6'h02;
          end
      6'h02:
          if (\$149 ) begin
            (* full_case = 32'd1 *)
            if (\$150 ) begin
            end else begin
              \$227  = 6'h03;
            end
          end
      6'h03:
          if (\$152 ) begin
            (* full_case = 32'd1 *)
            if (\$153 ) begin
            end else begin
              \$227  = 6'h04;
            end
          end
      6'h04:
          if (\$155 ) begin
            \$227  = 6'h05;
          end
      6'h05:
          if (\$156 ) begin
            \$227  = 6'h06;
          end
      6'h06:
          if (\$157 ) begin
            if (\$158 ) begin
              \$227  = 6'h07;
            end
          end
      6'h08:
          if (\$160 ) begin
            \$227  = 6'h09;
          end
      6'h09:
          if (\$162 ) begin
            \$227  = 6'h0a;
          end else if (\$163 ) begin
            (* full_case = 32'd1 *)
            if (\$164 ) begin
            end else begin
              \$227  = 6'h0b;
            end
          end
      6'h0b:
          if (btn_hold_done) begin
            \$227  = 6'h02;
          end else if (\$167 ) begin
            \$227  = 6'h0a;
          end else if (btn_press) begin
            \$227  = 6'h0c;
          end
      6'h07:
          \$227  = 6'h0d;
      6'h0d:
          if (dbg_fault_valid) begin
            \$227  = 6'h0e;
          end else if (halt_valid) begin
            \$227  = 6'h0f;
          end else if (\$169 ) begin
            \$227  = 6'h0a;
          end else if (btn_hold_done) begin
            \$227  = 6'h0b;
          end else if (btn_press) begin
            \$227  = 6'h02;
          end
      6'h0e:
          if (\$171 ) begin
            \$227  = 6'h0a;
          end else if (btn_press) begin
            \$227  = 6'h0b;
          end
      6'h0c:
          if (step_complete) begin
            \$227  = 6'h10;
          end
      6'h10:
          if (\$172 ) begin
            (* full_case = 32'd1 *)
            if (\$173 ) begin
            end else begin
              \$227  = 6'h11;
            end
          end
      6'h11:
          if (\$175 ) begin
            (* full_case = 32'd1 *)
            if (step_had_fault) begin
              \$227  = 6'h12;
            end else begin
              \$227  = 6'h09;
            end
          end
      6'h12:
          if (\$176 ) begin
            (* full_case = 32'd1 *)
            if (\$177 ) begin
            end else begin
              \$227  = 6'h13;
            end
          end
      6'h13:
          if (\$179 ) begin
            \$227  = 6'h09;
          end
      6'h0f:
          if (\$180 ) begin
            (* full_case = 32'd1 *)
            if (\$181 ) begin
            end else begin
              \$227  = 6'h0b;
            end
          end
      6'h0a:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$183 ) begin
              \$227  = 6'h14;
            end else if (\$184 ) begin
              \$227  = 6'h15;
            end else if (\$185 ) begin
              \$227  = 6'h0d;
            end else begin
              \$227  = 6'h0b;
            end
          end
      6'h14:
          \$227  = 6'h16;
      6'h16:
          if (valid) begin
            \$227  = 6'h17;
          end
      6'h17:
          if (valid) begin
            \$227  = 6'h18;
          end
      6'h18:
          if (valid) begin
            \$227  = 6'h19;
          end
      6'h19:
          if (valid) begin
            \$227  = 6'h1a;
          end
      6'h1a:
          if (valid) begin
            \$227  = 6'h1b;
          end
      6'h1b:
          if (valid) begin
            \$227  = 6'h1c;
          end
      6'h1c:
          if (valid) begin
            \$227  = 6'h1d;
          end
      6'h1d:
          if (valid) begin
            \$227  = 6'h1e;
          end
      6'h1e:
          (* full_case = 32'd1 *)
          if (\$187 ) begin
            \$227  = 6'h1f;
          end else begin
            \$227  = 6'h1a;
          end
      6'h1f:
          if (valid) begin
            \$227  = 6'h20;
          end
      6'h20:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$191 ) begin
              \$227  = 6'h21;
            end else begin
              \$227  = 6'h22;
            end
          end
      6'h21:
          if (\$192 ) begin
            \$227  = 6'h0b;
          end
      6'h22:
          if (\$193 ) begin
            (* full_case = 32'd1 *)
            if (\$194 ) begin
            end else begin
              \$227  = 6'h0b;
            end
          end
      6'h15:
          if (valid) begin
            \$227  = 6'h23;
          end
      6'h23:
          if (valid) begin
            \$227  = 6'h24;
          end
      6'h24:
          if (valid) begin
            \$227  = 6'h25;
          end
      6'h25:
          if (valid) begin
            \$227  = 6'h26;
          end
      6'h26:
          \$227  = 6'h27;
      6'h27:
          \$227  = 6'h28;
      6'h28:
          if (\$196 ) begin
            \$227  = 6'h29;
          end
      6'h29:
          if (\$197 ) begin
            \$227  = 6'h2a;
          end
      6'h2a:
          if (\$198 ) begin
            \$227  = 6'h2b;
          end
      6'h2b:
          if (\$199 ) begin
            (* full_case = 32'd1 *)
            if (\$202 ) begin
              \$227  = 6'h0b;
            end else begin
              \$227  = 6'h26;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$228  = banner_idx;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          if (dbg_boot_complete) begin
            \$228  = 5'h00;
          end
      6'h02:
          if (\$149 ) begin
            if (\$150 ) begin
              \$228  = \$151 [4:0];
            end
          end
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          if (btn_hold_done) begin
            \$228  = 5'h00;
          end
      6'h07:
          /* empty */;
      6'h0d:
          if (dbg_fault_valid) begin
          end else if (halt_valid) begin
          end else if (\$169 ) begin
          end else if (btn_hold_done) begin
          end else if (btn_press) begin
            \$228  = 5'h00;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$229  = halted;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          if (dbg_boot_complete) begin
            \$229  = 1'h1;
          end
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          if (btn_hold_done) begin
            \$229  = 1'h1;
          end
      6'h07:
          \$229  = 1'h0;
      6'h0d:
        begin
          \$229  = 1'h0;
          if (dbg_fault_valid) begin
          end else if (halt_valid) begin
            \$229  = 1'h1;
          end else if (\$169 ) begin
            \$229  = 1'h1;
          end else if (btn_hold_done) begin
            \$229  = 1'h1;
          end else if (btn_press) begin
            \$229  = 1'h0;
          end
        end
      6'h0e:
          \$229  = 1'h1;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          if (valid) begin
            if (\$183 ) begin
            end else if (\$184 ) begin
            end else if (\$185 ) begin
              \$229  = 1'h0;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$230  = banner_ever_sent;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          \$230  = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$231  = callhome_idx;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          if (\$149 ) begin
            (* full_case = 32'd1 *)
            if (\$150 ) begin
            end else begin
              \$231  = 5'h00;
            end
          end
      6'h03:
          if (\$152 ) begin
            if (\$153 ) begin
              \$231  = \$154 [4:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$232  = fault_nia_idx;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          if (\$156 ) begin
            \$232  = 2'h0;
          end
      6'h06:
          if (\$157 ) begin
            (* full_case = 32'd1 *)
            if (\$158 ) begin
            end else begin
              \$232  = \$159 [1:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$233  = pl_active;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          if (\$162 ) begin
            \$233  = 1'h1;
          end
      6'h0b:
          if (btn_hold_done) begin
          end else if (\$167 ) begin
            \$233  = 1'h1;
          end
      6'h07:
          /* empty */;
      6'h0d:
          if (dbg_fault_valid) begin
          end else if (halt_valid) begin
          end else if (\$169 ) begin
            \$233  = 1'h1;
          end
      6'h0e:
          if (\$171 ) begin
            \$233  = 1'h1;
          end
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$183 ) begin
            end else if (\$184 ) begin
            end else if (\$185 ) begin
              \$233  = 1'h0;
            end else begin
              \$233  = 1'h0;
            end
          end
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          if (valid) begin
            if (\$191 ) begin
              \$233  = 1'h0;
            end
          end
      6'h21:
          if (\$192 ) begin
            \$233  = 1'h0;
          end
      6'h22:
          if (\$193 ) begin
            (* full_case = 32'd1 *)
            if (\$194 ) begin
            end else begin
              \$233  = 1'h0;
            end
          end
      6'h15:
          /* empty */;
      6'h23:
          /* empty */;
      6'h24:
          /* empty */;
      6'h25:
          /* empty */;
      6'h26:
          /* empty */;
      6'h27:
          /* empty */;
      6'h28:
          /* empty */;
      6'h29:
          /* empty */;
      6'h2a:
          /* empty */;
      6'h2b:
          if (\$199 ) begin
            if (\$202 ) begin
              \$233  = 1'h0;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$234  = halt_idx;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          if (\$162 ) begin
            \$234  = 3'h0;
          end else if (\$163 ) begin
            (* full_case = 32'd1 *)
            if (\$164 ) begin
              \$234  = \$165 [2:0];
            end else begin
              \$234  = 3'h0;
            end
          end
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          if (dbg_fault_valid) begin
          end else if (halt_valid) begin
            \$234  = 3'h0;
          end
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          if (\$175 ) begin
            (* full_case = 32'd1 *)
            if (step_had_fault) begin
            end else begin
              \$234  = 3'h0;
            end
          end
      6'h12:
          /* empty */;
      6'h13:
          if (\$179 ) begin
            \$234  = 3'h0;
          end
      6'h0f:
          if (\$180 ) begin
            (* full_case = 32'd1 *)
            if (\$181 ) begin
              \$234  = \$182 [2:0];
            end else begin
              \$234  = 3'h0;
            end
          end
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          if (\$192 ) begin
            \$234  = 3'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$235  = stepping;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          if (btn_hold_done) begin
          end else if (\$167 ) begin
          end else if (btn_press) begin
            \$235  = 1'h1;
          end
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            \$235  = 1'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$236  = last_fault_code;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          if (dbg_fault_valid) begin
            \$236  = { 3'h0, fault };
          end
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            if (dbg_fault_valid) begin
              \$236  = { 3'h0, fault };
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$237  = boot_reason;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          if (dbg_fault_valid) begin
            \$237  = 8'h02;
          end
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            if (dbg_fault_valid) begin
              \$237  = 8'h02;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$238  = fault_nia;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          if (dbg_fault_valid) begin
            \$238  = dbg_nia;
          end
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            if (dbg_fault_valid) begin
              \$238  = dbg_nia;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$239  = step_nia;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            \$239  = dbg_nia;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$240  = step_fault;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            \$240  = fault[3:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$241  = step_had_fault;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            \$241  = dbg_fault_valid;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$242  = step_idx;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          if (step_complete) begin
            \$242  = 2'h0;
          end
      6'h10:
          if (\$172 ) begin
            (* full_case = 32'd1 *)
            if (\$173 ) begin
              \$242  = \$174 [1:0];
            end else begin
              \$242  = 2'h0;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$243  = fault_msg_idx;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          if (\$175 ) begin
            if (step_had_fault) begin
              \$243  = 2'h0;
            end
          end
      6'h12:
          if (\$176 ) begin
            (* full_case = 32'd1 *)
            if (\$177 ) begin
              \$243  = \$178 [1:0];
            end else begin
              \$243  = 2'h0;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$244  = pl_addr;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          if (valid) begin
            \$244 [15:8] = \data$123 ;
          end
      6'h17:
          if (valid) begin
            \$244 [7:0] = \data$123 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$245  = pl_total_count;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          if (valid) begin
            \$245 [15:8] = \data$123 ;
          end
      6'h19:
          if (valid) begin
            \$245 [7:0] = \data$123 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$246  = pl_count;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          if (valid) begin
            \$246 [15:8] = \data$123 ;
          end
      6'h19:
          if (valid) begin
            \$246 [7:0] = \data$123 ;
          end
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          (* full_case = 32'd1 *)
          if (\$187 ) begin
            \$246  = 16'h0000;
          end else begin
            \$246  = \$188 [15:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$247  = pl_cur_addr;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          if (valid) begin
            \$247  = pl_addr;
          end
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          \$247  = \$186 [15:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$248  = pl_word;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          if (valid) begin
            \$248 [7:0] = \data$123 ;
          end
      6'h1b:
          if (valid) begin
            \$248 [15:8] = \data$123 ;
          end
      6'h1c:
          if (valid) begin
            \$248 [23:16] = \data$123 ;
          end
      6'h1d:
          if (valid) begin
            \$248 [31:24] = \data$123 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$249  = pl_crc_hi_buf;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          if (valid) begin
            \$249  = \data$123 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$250  = pl_crc_fail;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          if (valid) begin
            \$250  = \$189 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$251  = pl_ack0;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$191 ) begin
            end else begin
              \$251  = pl_addr[15:8];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$252  = pl_ack1;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$191 ) begin
            end else begin
              \$252  = pl_addr[7:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$253  = pl_ack2;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$191 ) begin
            end else begin
              \$253  = pl_total_count[15:8];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$254  = pl_ack3;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$191 ) begin
            end else begin
              \$254  = pl_total_count[7:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$255  = pl_ack_idx;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          if (valid) begin
            (* full_case = 32'd1 *)
            if (\$191 ) begin
            end else begin
              \$255  = 3'h0;
            end
          end
      6'h21:
          /* empty */;
      6'h22:
          if (\$193 ) begin
            if (\$194 ) begin
              \$255  = \$195 [2:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$256  = rb_addr;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          /* empty */;
      6'h22:
          /* empty */;
      6'h15:
          if (valid) begin
            \$256 [15:8] = \data$123 ;
          end
      6'h23:
          if (valid) begin
            \$256 [7:0] = \data$123 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$257  = rb_count;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          /* empty */;
      6'h22:
          /* empty */;
      6'h15:
          /* empty */;
      6'h23:
          /* empty */;
      6'h24:
          if (valid) begin
            \$257 [15:8] = \data$123 ;
          end
      6'h25:
          if (valid) begin
            \$257 [7:0] = \data$123 ;
          end
      6'h26:
          /* empty */;
      6'h27:
          /* empty */;
      6'h28:
          /* empty */;
      6'h29:
          /* empty */;
      6'h2a:
          /* empty */;
      6'h2b:
          if (\$199 ) begin
            \$257  = \$200 [15:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$258  = rb_cur_addr;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          /* empty */;
      6'h22:
          /* empty */;
      6'h15:
          /* empty */;
      6'h23:
          /* empty */;
      6'h24:
          /* empty */;
      6'h25:
          if (valid) begin
            \$258  = rb_addr;
          end
      6'h26:
          /* empty */;
      6'h27:
          /* empty */;
      6'h28:
          /* empty */;
      6'h29:
          /* empty */;
      6'h2a:
          /* empty */;
      6'h2b:
          if (\$199 ) begin
            \$258  = \$201 [15:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$41 ) begin end
    \$259  = rb_word;
    casez (debug_fsm_state)
      6'h00:
          /* empty */;
      6'h01:
          /* empty */;
      6'h02:
          /* empty */;
      6'h03:
          /* empty */;
      6'h04:
          /* empty */;
      6'h05:
          /* empty */;
      6'h06:
          /* empty */;
      6'h08:
          /* empty */;
      6'h09:
          /* empty */;
      6'h0b:
          /* empty */;
      6'h07:
          /* empty */;
      6'h0d:
          /* empty */;
      6'h0e:
          /* empty */;
      6'h0c:
          /* empty */;
      6'h10:
          /* empty */;
      6'h11:
          /* empty */;
      6'h12:
          /* empty */;
      6'h13:
          /* empty */;
      6'h0f:
          /* empty */;
      6'h0a:
          /* empty */;
      6'h14:
          /* empty */;
      6'h16:
          /* empty */;
      6'h17:
          /* empty */;
      6'h18:
          /* empty */;
      6'h19:
          /* empty */;
      6'h1a:
          /* empty */;
      6'h1b:
          /* empty */;
      6'h1c:
          /* empty */;
      6'h1d:
          /* empty */;
      6'h1e:
          /* empty */;
      6'h1f:
          /* empty */;
      6'h20:
          /* empty */;
      6'h21:
          /* empty */;
      6'h22:
          /* empty */;
      6'h15:
          /* empty */;
      6'h23:
          /* empty */;
      6'h24:
          /* empty */;
      6'h25:
          /* empty */;
      6'h26:
          /* empty */;
      6'h27:
          \$259  = mem_rd_data;
    endcase
  end
  assign rx = uart_rx;
  assign addr = dbg_nia[11:2];
  assign imem_addr = dbg_nia;
  assign data = imem_data;
  assign clist_rd_en = 1'h0;
  assign dmem_rd__addr = mem_addr;
  assign dmem_rd__data = mem_rd_data;
  assign mmio_reg_sel = dmem_addr[5:2];
  assign ns_rd_data = { 64'h0000000000000000, mem_rd_data };
  assign clist_rd_data = mem_rd_data;
  assign nia = dbg_nia;
  assign tx = uart_tx;
  assign fault_valid = dbg_fault_valid;
  assign boot_complete = dbg_boot_complete;
  assign gc_start = 1'h0;
  
  assign dbg_fault = fault[3:0];
  assign \clist_rd_data.slot_id  = mem_rd_data[15:0];
  assign \clist_rd_data.gt_seq  = mem_rd_data[24:16];
  assign \clist_rd_data.gt_type  = mem_rd_data[26:25];
  assign \clist_rd_data.dom  = mem_rd_data[27];
  assign \clist_rd_data.perm  = mem_rd_data[30:28];
  assign \clist_rd_data.b_flag  = mem_rd_data[31];
  assign \clist_wr_data.slot_id  = clist_wr_data[15:0];
  assign \clist_wr_data.gt_seq  = clist_wr_data[24:16];
  assign \clist_wr_data.gt_type  = clist_wr_data[26:25];
  assign \clist_wr_data.dom  = clist_wr_data[27];
  assign \clist_wr_data.perm  = clist_wr_data[30:28];
  assign \clist_wr_data.b_flag  = clist_wr_data[31];
  assign \$215 [2] = btn_sync[1];
  assign \$215 [1] = btn_sync[0];
  assign \$215 [0] = push_button;
  assign any_clist_access = clist_wr_en;
endmodule

(* src = "/home/runner/workspace/hardware/boot_rom.py:673" *)
(* generator = "Amaranth" *)
module \top.boot_rom (clk, data, addr);
  reg \$auto$verilog_backend.cc:2355:dump_module$42  = 0;
  (* src = "/home/runner/workspace/hardware/boot_rom.py:669" *)
  input [9:0] addr;
  wire [9:0] addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/boot_rom.py:670" *)
  output [31:0] data;
  reg [31:0] data = 32'd0;
  (* src = "/home/runner/workspace/hardware/boot_rom.py:675" *)
  reg [31:0] rom_comb;
  (* src = "/home/runner/workspace/hardware/boot_rom.py:670" *)
  always @(posedge clk)
    data <= rom_comb;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$42 ) begin end
    (* full_case = 32'd1 *)
    casez (addr)
      10'h000:
          rom_comb = 32'd125796352;
      10'h001:
          rom_comb = 32'd661094401;
      10'h002:
          rom_comb = 32'd385875968;
      10'h100:
          rom_comb = 32'd119209992;
      10'h101:
          rom_comb = 32'd2936537089;
      10'h102:
          rom_comb = 32'd2399764480;
      10'h103:
          rom_comb = 32'd2937586044;
      10'h104:
          rom_comb = 32'd2937077759;
      10'h105:
          rom_comb = 32'd3071344641;
      10'h106:
          rom_comb = 32'd3095429119;
      10'h107:
          rom_comb = 32'd3071901697;
      10'h108:
          rom_comb = 32'd3095429116;
      10'h109:
          rom_comb = 32'd2399240192;
      10'h10a:
          rom_comb = 32'd2937586044;
      10'h10b:
          rom_comb = 32'd2937077759;
      10'h10c:
          rom_comb = 32'd3071344641;
      10'h10d:
          rom_comb = 32'd3095429119;
      10'h10e:
          rom_comb = 32'd3071901697;
      10'h10f:
          rom_comb = 32'd3095429116;
      10'h110:
          rom_comb = 32'd3204481010;
      10'h140:
          rom_comb = 32'd4160751616;
      10'h141:
          rom_comb = 32'd2;
      10'h142:
          rom_comb = 32'd520093696;
      10'h200:
          rom_comb = 32'd3071377408;
      10'h201:
          rom_comb = 32'd3087007759;
      10'h202:
          rom_comb = 32'd3071377409;
      10'h203:
          rom_comb = 32'd3087007762;
      10'h204:
          rom_comb = 32'd3071377410;
      10'h205:
          rom_comb = 32'd3087007764;
      10'h206:
          rom_comb = 32'd3071377411;
      10'h207:
          rom_comb = 32'd3087007797;
      10'h208:
          rom_comb = 32'd3071377412;
      10'h209:
          rom_comb = 32'd3087007835;
      10'h20a:
          rom_comb = 32'd3071377413;
      10'h20b:
          rom_comb = 32'd3087007871;
      10'h20c:
          rom_comb = 32'd3071377414;
      10'h20d:
          rom_comb = 32'd3087007898;
      10'h20e:
          rom_comb = 32'd3071377415;
      10'h20f:
          rom_comb = 32'd3087007897;
      10'h210:
          rom_comb = 32'd2136997888;
      10'h211:
          rom_comb = 32'd2137391104;
      10'h212:
          rom_comb = 32'd2133196800;
      10'h213:
          rom_comb = 32'd2130837504;
      10'h214:
          rom_comb = 32'd520093696;
      10'h215:
          rom_comb = 32'd2271215616;
      10'h216:
          rom_comb = 32'd2133196800;
      10'h217:
          rom_comb = 32'd2130837504;
      10'h218:
          rom_comb = 32'd520093696;
      10'h219:
          rom_comb = 32'd2136997888;
      10'h21a:
          rom_comb = 32'd2133196800;
      10'h21b:
          rom_comb = 32'd2136997888;
      10'h21c:
          rom_comb = 32'd2133721088;
      10'h21d:
          rom_comb = 32'd2136997888;
      10'h21e:
          rom_comb = 32'd1997406208;
      10'h21f:
          rom_comb = 32'd2365587468;
      10'h220:
          rom_comb = 32'd2136997888;
      10'h221:
          rom_comb = 32'd2271608832;
      10'h222:
          rom_comb = 32'd2131623936;
      10'h223:
          rom_comb = 32'd2136997889;
      10'h224:
          rom_comb = 32'd2133721088;
      10'h225:
          rom_comb = 32'd2136997888;
      10'h226:
          rom_comb = 32'd1997406208;
      10'h227:
          rom_comb = 32'd2390786047;
      10'h228:
          rom_comb = 32'd1734377473;
      10'h229:
          rom_comb = 32'd2134245376;
      10'h22a:
          rom_comb = 32'd2136997889;
      10'h22b:
          rom_comb = 32'd2000027648;
      10'h22c:
          rom_comb = 32'd2290090007;
      10'h22d:
          rom_comb = 32'd2137128960;
      10'h22e:
          rom_comb = 32'd2137391104;
      10'h22f:
          rom_comb = 32'd2133196800;
      10'h230:
          rom_comb = 32'd2539651073;
      10'h231:
          rom_comb = 32'd2131099648;
      10'h232:
          rom_comb = 32'd2673901569;
      10'h233:
          rom_comb = 32'd2131623936;
      10'h234:
          rom_comb = 32'd2136997889;
      10'h235:
          rom_comb = 32'd1999503360;
      10'h236:
          rom_comb = 32'd2290090017;
      10'h237:
          rom_comb = 32'd2136997888;
      10'h238:
          rom_comb = 32'd2271608832;
      10'h239:
          rom_comb = 32'd2133196800;
      10'h23a:
          rom_comb = 32'd2130837504;
      10'h23b:
          rom_comb = 32'd520093696;
      10'h23c:
          rom_comb = 32'd2136997888;
      10'h23d:
          rom_comb = 32'd1997406208;
      10'h23e:
          rom_comb = 32'd2290089990;
      10'h23f:
          rom_comb = 32'd2136997888;
      10'h240:
          rom_comb = 32'd2131099648;
      10'h241:
          rom_comb = 32'd520093696;
      10'h242:
          rom_comb = 32'd2136997888;
      10'h243:
          rom_comb = 32'd2133196800;
      10'h244:
          rom_comb = 32'd2136997888;
      10'h245:
          rom_comb = 32'd1996881920;
      10'h246:
          rom_comb = 32'd2365587472;
      10'h247:
          rom_comb = 32'd2136997888;
      10'h248:
          rom_comb = 32'd2271608832;
      10'h249:
          rom_comb = 32'd2131099648;
      10'h24a:
          rom_comb = 32'd2137128961;
      10'h24b:
          rom_comb = 32'd2133196800;
      10'h24c:
          rom_comb = 32'd2136997888;
      10'h24d:
          rom_comb = 32'd1997406208;
      10'h24e:
          rom_comb = 32'd2365587480;
      10'h24f:
          rom_comb = 32'd2136997888;
      10'h250:
          rom_comb = 32'd2271608832;
      10'h251:
          rom_comb = 32'd2131623936;
      10'h252:
          rom_comb = 32'd2137128961;
      10'h253:
          rom_comb = 32'd2133196800;
      10'h254:
          rom_comb = 32'd2136997888;
      10'h255:
          rom_comb = 32'd2133721088;
      10'h256:
          rom_comb = 32'd1996521472;
      10'h257:
          rom_comb = 32'd2374008831;
      10'h258:
          rom_comb = 32'd2271215616;
      10'h259:
          rom_comb = 32'd2131099648;
      10'h25a:
          rom_comb = 32'd2137161729;
      10'h25b:
          rom_comb = 32'd2133721088;
      10'h25c:
          rom_comb = 32'd2136997889;
      10'h25d:
          rom_comb = 32'd1998979072;
      10'h25e:
          rom_comb = 32'd2290090022;
      10'h25f:
          rom_comb = 32'd2136997888;
      10'h260:
          rom_comb = 32'd2271608832;
      10'h261:
          rom_comb = 32'd2133721088;
      10'h262:
          rom_comb = 32'd2130870272;
      10'h263:
          rom_comb = 32'd520093696;
      10'h264:
          rom_comb = 32'd2136997888;
      10'h265:
          rom_comb = 32'd1996881920;
      10'h266:
          rom_comb = 32'd2290089990;
      10'h267:
          rom_comb = 32'd2136997888;
      10'h268:
          rom_comb = 32'd2131099648;
      10'h269:
          rom_comb = 32'd520093696;
      10'h26a:
          rom_comb = 32'd2136997889;
      10'h26b:
          rom_comb = 32'd1996881920;
      10'h26c:
          rom_comb = 32'd2290089996;
      10'h26d:
          rom_comb = 32'd2136997889;
      10'h26e:
          rom_comb = 32'd2131099648;
      10'h26f:
          rom_comb = 32'd520093696;
      10'h270:
          rom_comb = 32'd2673868801;
      10'h271:
          rom_comb = 32'd2133196800;
      10'h272:
          rom_comb = 32'd2136997888;
      10'h273:
          rom_comb = 32'd2133721088;
      10'h274:
          rom_comb = 32'd2136997908;
      10'h275:
          rom_comb = 32'd1999503360;
      10'h276:
          rom_comb = 32'd2365620223;
      10'h277:
          rom_comb = 32'd2136997888;
      10'h278:
          rom_comb = 32'd2134245376;
      10'h279:
          rom_comb = 32'd2134376448;
      10'h27a:
          rom_comb = 32'd2000289792;
      10'h27b:
          rom_comb = 32'd2374008831;
      10'h27c:
          rom_comb = 32'd2271444992;
      10'h27d:
          rom_comb = 32'd2134769664;
      10'h27e:
          rom_comb = 32'd2137194497;
      10'h27f:
          rom_comb = 32'd2134245376;
      10'h280:
          rom_comb = 32'd2137128960;
      10'h281:
          rom_comb = 32'd2137391104;
      10'h282:
          rom_comb = 32'd2135293952;
      10'h283:
          rom_comb = 32'd2674130945;
      10'h284:
          rom_comb = 32'd2135293952;
      10'h285:
          rom_comb = 32'd2133065728;
      10'h286:
          rom_comb = 32'd2137161729;
      10'h287:
          rom_comb = 32'd2133721088;
      10'h288:
          rom_comb = 32'd2130837504;
      10'h289:
          rom_comb = 32'd520093696;
      10'h28a:
          rom_comb = 32'd2136997889;
      10'h28b:
          rom_comb = 32'd2133196800;
      10'h28c:
          rom_comb = 32'd2136997888;
      10'h28d:
          rom_comb = 32'd1997406208;
      10'h28e:
          rom_comb = 32'd2390786047;
      10'h28f:
          rom_comb = 32'd2136997888;
      10'h290:
          rom_comb = 32'd2133721088;
      10'h291:
          rom_comb = 32'd2133852160;
      10'h292:
          rom_comb = 32'd2134507520;
      10'h293:
          rom_comb = 32'd2136997888;
      10'h294:
          rom_comb = 32'd2000551936;
      10'h295:
          rom_comb = 32'd2390786047;
      10'h296:
          rom_comb = 32'd1734574081;
      10'h297:
          rom_comb = 32'd2135293952;
      10'h298:
          rom_comb = 32'd2136997889;
      10'h299:
          rom_comb = 32'd2001076224;
      10'h29a:
          rom_comb = 32'd2290090004;
      10'h29b:
          rom_comb = 32'd2137161728;
      10'h29c:
          rom_comb = 32'd2137391104;
      10'h29d:
          rom_comb = 32'd2133721088;
      10'h29e:
          rom_comb = 32'd2539847681;
      10'h29f:
          rom_comb = 32'd2134245376;
      10'h2a0:
          rom_comb = 32'd2674098177;
      10'h2a1:
          rom_comb = 32'd2134769664;
      10'h2a2:
          rom_comb = 32'd2132967424;
      10'h2a3:
          rom_comb = 32'd2271248385;
      10'h2a4:
          rom_comb = 32'd2131623936;
      10'h2a5:
          rom_comb = 32'd2130837504;
      10'h2a6:
          rom_comb = 32'd520093696;
      10'h2a7:
          rom_comb = 32'd520093696;
      10'h2a8:
          rom_comb = 32'd520093696;
      default:
          rom_comb = 32'd0;
    endcase
  end
  
endmodule

(* src = "/home/runner/workspace/hardware/core.py:164" *)
(* generator = "Amaranth" *)
module \top.core (clk, mem_rd_valid, imem_valid, boot_complete, halt_valid, \port$4577$0 , free_run_start, free_run_nia, boot_start, clist_addr, clist_wr_data, clist_wr_en, \fault$639 , \fault_valid$640 , dmem_addr, dmem_rd_en, dmem_wr_data, dmem_wr_en, ns_addr, ns_rd_en, ns_wr_data, ns_wr_en
, imem_addr, instruction, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$43  = 0;
  wire \$1 ;
  wire \$10 ;
  wire \$100 ;
  wire \$101 ;
  wire \$102 ;
  wire \$103 ;
  wire [31:0] \$104 ;
  wire \$105 ;
  wire \$106 ;
  wire \$107 ;
  wire \$108 ;
  wire \$109 ;
  wire \$11 ;
  wire \$110 ;
  wire \$111 ;
  wire \$112 ;
  wire \$113 ;
  wire \$114 ;
  wire \$115 ;
  wire \$116 ;
  wire \$117 ;
  wire \$118 ;
  wire \$119 ;
  wire \$12 ;
  wire \$120 ;
  wire \$121 ;
  wire \$122 ;
  wire \$123 ;
  wire \$124 ;
  wire \$125 ;
  wire \$126 ;
  wire \$127 ;
  wire \$128 ;
  wire \$129 ;
  wire \$13 ;
  wire \$130 ;
  wire \$131 ;
  wire \$132 ;
  wire \$133 ;
  wire \$134 ;
  wire \$135 ;
  wire [32:0] \$136 ;
  wire \$137 ;
  wire \$138 ;
  wire \$139 ;
  wire \$14 ;
  wire \$140 ;
  wire \$141 ;
  wire \$142 ;
  wire \$143 ;
  wire \$144 ;
  wire \$145 ;
  wire \$146 ;
  wire \$147 ;
  wire \$148 ;
  wire [3:0] \$149 ;
  wire \$15 ;
  wire \$150 ;
  wire \$151 ;
  wire \$152 ;
  wire \$153 ;
  wire \$154 ;
  wire \$155 ;
  wire \$156 ;
  wire \$157 ;
  wire \$158 ;
  wire \$159 ;
  wire \$16 ;
  wire [3:0] \$160 ;
  wire [3:0] \$161 ;
  wire \$162 ;
  wire \$163 ;
  wire \$164 ;
  wire \$165 ;
  wire \$166 ;
  wire \$167 ;
  wire [62:0] \$168 ;
  wire [63:0] \$169 ;
  wire \$17 ;
  wire [5:0] \$170 ;
  wire [6:0] \$171 ;
  wire \$172 ;
  wire [31:0] \$173 ;
  wire \$174 ;
  wire [31:0] \$175 ;
  wire \$176 ;
  wire \$177 ;
  wire \$178 ;
  wire \$179 ;
  wire \$18 ;
  wire [31:0] \$180 ;
  wire [32:0] \$181 ;
  wire [31:0] \$182 ;
  wire \$183 ;
  wire \$184 ;
  wire \$185 ;
  wire [62:0] \$186 ;
  wire [31:0] \$187 ;
  wire [31:0] \$188 ;
  wire [31:0] \$189 ;
  wire \$19 ;
  wire [62:0] \$190 ;
  wire [62:0] \$191 ;
  wire \$192 ;
  wire \$193 ;
  wire \$194 ;
  wire \$195 ;
  wire \$196 ;
  wire \$197 ;
  wire \$198 ;
  wire \$199 ;
  wire \$2 ;
  wire \$20 ;
  wire \$200 ;
  wire \$201 ;
  wire \$202 ;
  wire \$203 ;
  wire \$204 ;
  wire \$205 ;
  wire \$206 ;
  wire \$207 ;
  wire \$208 ;
  wire \$209 ;
  wire \$21 ;
  wire \$210 ;
  wire \$211 ;
  wire \$212 ;
  wire \$213 ;
  wire \$214 ;
  wire \$215 ;
  wire \$216 ;
  wire \$217 ;
  wire \$218 ;
  wire [1:0] \$219 ;
  wire \$22 ;
  wire [15:0] \$220 ;
  wire [15:0] \$221 ;
  wire \$222 ;
  wire \$223 ;
  wire \$224 ;
  wire \$225 ;
  wire [32:0] \$226 ;
  wire \$227 ;
  wire [31:0] \$228 ;
  wire [15:0] \$229 ;
  wire \$23 ;
  wire \$230 ;
  wire \$231 ;
  wire \$232 ;
  wire [62:0] \$233 ;
  wire [32:0] \$234 ;
  wire [32:0] \$235 ;
  wire [31:0] \$236 ;
  wire [32:0] \$237 ;
  wire [33:0] \$238 ;
  wire \$239 ;
  wire \$24 ;
  wire \$240 ;
  wire \$241 ;
  wire \$242 ;
  wire \$243 ;
  wire \$244 ;
  wire [34:0] \$245 ;
  wire [22:0] \$246 ;
  wire [32:0] \$247 ;
  wire [30:0] \$248 ;
  wire [15:0] \$249 ;
  wire \$25 ;
  wire [21:0] \$250 ;
  wire [31:0] \$251 ;
  wire [4:0] \$252 ;
  wire [31:0] \$253 ;
  wire [15:0] \$254 ;
  wire [16:0] \$255 ;
  wire \$256 ;
  wire [16:0] \$257 ;
  wire [32:0] \$258 ;
  wire [32:0] \$259 ;
  wire \$26 ;
  wire [32:0] \$260 ;
  wire [32:0] \$261 ;
  wire \$262 ;
  wire [15:0] \$263 ;
  wire [17:0] \$264 ;
  wire [32:0] \$265 ;
  wire [10:0] \$266 ;
  wire [32:0] \$267 ;
  wire \$268 ;
  wire \$269 ;
  wire \$27 ;
  wire [31:0] \$270 ;
  wire [56:0] \$271 ;
  wire \$272 ;
  wire \$273 ;
  wire \$274 ;
  wire \$275 ;
  wire \$276 ;
  wire \$277 ;
  wire \$278 ;
  wire \$279 ;
  wire \$28 ;
  wire \$280 ;
  wire \$281 ;
  wire \$282 ;
  wire \$283 ;
  wire \$284 ;
  wire \$285 ;
  wire \$286 ;
  wire \$287 ;
  wire \$288 ;
  wire \$289 ;
  wire \$29 ;
  wire \$290 ;
  wire \$291 ;
  wire \$292 ;
  wire \$293 ;
  wire \$294 ;
  wire \$295 ;
  wire \$296 ;
  wire \$297 ;
  wire \$298 ;
  wire \$299 ;
  wire \$3 ;
  wire \$30 ;
  wire \$300 ;
  wire \$301 ;
  wire \$302 ;
  wire \$303 ;
  wire \$304 ;
  wire \$305 ;
  wire \$306 ;
  wire \$307 ;
  wire \$308 ;
  wire \$309 ;
  wire \$31 ;
  wire \$310 ;
  wire \$311 ;
  wire \$312 ;
  wire \$313 ;
  wire \$314 ;
  wire [34:0] \$315 ;
  wire [32:0] \$316 ;
  wire \$317 ;
  wire \$318 ;
  wire \$319 ;
  wire \$32 ;
  wire \$320 ;
  wire \$321 ;
  wire \$322 ;
  wire \$323 ;
  wire \$324 ;
  wire \$325 ;
  wire [21:0] \$326 ;
  wire [24:0] \$327 ;
  wire [32:0] \$328 ;
  wire \$329 ;
  wire \$33 ;
  wire \$330 ;
  wire \$331 ;
  wire \$332 ;
  wire \$333 ;
  wire \$334 ;
  wire \$335 ;
  wire \$336 ;
  wire \$337 ;
  wire \$338 ;
  wire \$339 ;
  wire \$34 ;
  wire \$340 ;
  wire \$341 ;
  wire \$342 ;
  wire \$343 ;
  wire \$344 ;
  wire \$345 ;
  wire \$346 ;
  wire \$347 ;
  wire \$348 ;
  wire \$349 ;
  wire \$35 ;
  wire \$350 ;
  wire \$351 ;
  wire \$352 ;
  wire \$353 ;
  wire \$354 ;
  wire \$355 ;
  wire [15:0] \$356 ;
  wire [15:0] \$357 ;
  wire [31:0] \$358 ;
  wire [31:0] \$359 ;
  wire \$36 ;
  wire \$360 ;
  wire \$361 ;
  wire \$362 ;
  wire \$363 ;
  wire [15:0] \$364 ;
  wire \$365 ;
  wire [15:0] \$366 ;
  wire [16:0] \$367 ;
  wire \$368 ;
  wire [13:0] \$369 ;
  wire \$37 ;
  wire \$370 ;
  wire \$371 ;
  wire [14:0] \$372 ;
  wire [15:0] \$373 ;
  wire \$374 ;
  wire [8:0] \$375 ;
  reg [2:0] \$376 ;
  reg [31:0] \$377 ;
  reg [31:0] \$378 ;
  reg [31:0] \$379 ;
  wire \$38 ;
  reg \$380 ;
  reg \$381 ;
  reg \$382 ;
  reg \$383 ;
  reg [31:0] \$384 ;
  reg \$385 ;
  reg [15:0] \$386 ;
  reg [31:0] \$387 ;
  reg [31:0] \$388 ;
  reg [31:0] \$389 ;
  wire \$39 ;
  reg [3:0] \$390 ;
  reg [31:0] \$391 ;
  reg [14:0] \$392 ;
  reg [12:0] \$393 ;
  reg [7:0] \$394 ;
  reg [13:0] \$395 ;
  reg [7:0] \$396 ;
  reg [14:0] \$397 ;
  reg [31:0] \$398 ;
  reg [31:0] \$399 ;
  wire \$4 ;
  wire \$40 ;
  reg [31:0] \$400 ;
  reg [31:0] \$401 ;
  reg [31:0] \$402 ;
  reg [31:0] \$403 ;
  reg [1:0] \$404 ;
  reg [31:0] \$405 ;
  reg [3:0] \$406 ;
  wire [1:0] \$407 ;
  wire [15:0] \$408 ;
  wire \$41 ;
  wire \$42 ;
  wire \$43 ;
  wire \$44 ;
  wire \$45 ;
  wire \$46 ;
  wire \$47 ;
  wire \$48 ;
  wire \$49 ;
  wire \$5 ;
  wire [3:0] \$50 ;
  wire [3:0] \$51 ;
  wire [3:0] \$52 ;
  wire [3:0] \$53 ;
  wire [3:0] \$54 ;
  wire [3:0] \$55 ;
  wire [3:0] \$56 ;
  wire [3:0] \$57 ;
  wire [3:0] \$58 ;
  wire [3:0] \$59 ;
  wire \$6 ;
  wire [3:0] \$60 ;
  wire \$61 ;
  wire [3:0] \$62 ;
  wire \$63 ;
  wire \$64 ;
  wire \$65 ;
  wire \$66 ;
  wire \$67 ;
  wire \$68 ;
  wire [3:0] \$69 ;
  wire \$7 ;
  wire [3:0] \$70 ;
  wire [3:0] \$71 ;
  wire [3:0] \$72 ;
  wire [3:0] \$73 ;
  wire [3:0] \$74 ;
  wire [3:0] \$75 ;
  wire [3:0] \$76 ;
  wire [3:0] \$77 ;
  wire [3:0] \$78 ;
  wire [3:0] \$79 ;
  wire \$8 ;
  wire [3:0] \$80 ;
  wire [95:0] \$81 ;
  wire [95:0] \$82 ;
  wire [95:0] \$83 ;
  wire [95:0] \$84 ;
  wire [95:0] \$85 ;
  wire [95:0] \$86 ;
  wire [95:0] \$87 ;
  wire [95:0] \$88 ;
  wire [95:0] \$89 ;
  wire \$9 ;
  wire [95:0] \$90 ;
  wire [95:0] \$91 ;
  wire [95:0] \$92 ;
  wire \$93 ;
  wire \$94 ;
  wire \$95 ;
  wire \$96 ;
  wire \$97 ;
  wire \$98 ;
  wire \$99 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$34 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$36 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$38 ;
  wire [13:0] \$auto$rtlil.cc:2739:Not$40 ;
  (* src = "/home/runner/workspace/hardware/core.py:1461" *)
  wire _outform_start;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:29" *)
  wire [15:0] access_index;
  (* src = "/home/runner/workspace/hardware/core.py:1791" *)
  wire [31:0] alloc_aligned_w_noniot;
  (* src = "/home/runner/workspace/hardware/outform.py:98" *)
  wire [31:0] alloc_base;
  (* src = "/home/runner/workspace/hardware/outform.py:96" *)
  wire alloc_done;
  (* src = "/home/runner/workspace/hardware/outform.py:97" *)
  wire alloc_fault;
  (* src = "/home/runner/workspace/hardware/core.py:1802" *)
  wire alloc_fits_ni;
  (* src = "/home/runner/workspace/hardware/core.py:1790" *)
  wire [31:0] alloc_mask_w_noniot;
  (* src = "/home/runner/workspace/hardware/outform.py:95" *)
  wire [4:0] alloc_n;
  (* src = "/home/runner/workspace/hardware/core.py:1803" *)
  wire alloc_n_ok_ni;
  (* src = "/home/runner/workspace/hardware/core.py:1792" *)
  wire [32:0] alloc_new_wm_w_noniot;
  (* src = "/home/runner/workspace/hardware/outform.py:94" *)
  wire alloc_req;
  (* src = "/home/runner/workspace/hardware/core.py:1789" *)
  wire [31:0] alloc_sz_w_noniot;
  (* src = "/home/runner/workspace/hardware/core.py:313" *)
  wire any_unit_busy;
  (* src = "/home/runner/workspace/hardware/core.py:1126" *)
  wire [31:0] arith_imm_sx;
  (* src = "/home/runner/workspace/hardware/core.py:1186" *)
  wire asr_mode;
  (* src = "/home/runner/workspace/hardware/core.py:1193" *)
  wire [31:0] asr_result;
  (* src = "/home/runner/workspace/hardware/core.py:1241" *)
  wire [31:0] bf_mask;
  (* src = "/home/runner/workspace/hardware/core.py:1239" *)
  wire [4:0] bf_offset;
  (* src = "/home/runner/workspace/hardware/core.py:1240" *)
  wire [4:0] bf_width;
  (* src = "/home/runner/workspace/hardware/core.py:309" *)
  reg bfext_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:522" *)
  wire [3:0] bfext_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:522" *)
  wire \bfext_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:522" *)
  wire \bfext_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:522" *)
  wire \bfext_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:522" *)
  wire \bfext_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/core.py:515" *)
  wire [31:0] bfext_result;
  (* src = "/home/runner/workspace/hardware/core.py:508" *)
  wire bfext_start_sig;
  (* src = "/home/runner/workspace/hardware/core.py:310" *)
  reg bfins_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:523" *)
  wire [3:0] bfins_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:523" *)
  wire \bfins_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:523" *)
  wire \bfins_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:523" *)
  wire \bfins_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:523" *)
  wire \bfins_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/core.py:1269" *)
  wire [31:0] bfins_mask_shifted;
  (* src = "/home/runner/workspace/hardware/core.py:516" *)
  wire [31:0] bfins_result;
  (* src = "/home/runner/workspace/hardware/core.py:509" *)
  wire bfins_start_sig;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap0_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap0_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap0_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap0_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap0_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap0_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap0_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap0_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap10_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap10_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap10_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap10_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap10_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap10_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap10_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap10_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap11_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap11_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap11_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap11_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap11_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap11_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap11_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap11_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap12_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap12_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap12_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap12_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap12_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap12_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap12_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap12_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap13_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap13_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap13_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap13_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap13_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap13_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap13_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap13_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  reg boot_cap14_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  reg [31:0] boot_cap14_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap14_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap14_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap14_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap14_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap14_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap14_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap15_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap15_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap15_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap15_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap15_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap15_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap15_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap15_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap1_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap1_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap1_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap1_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap1_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap1_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap1_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap1_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap2_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap2_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap2_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap2_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap2_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap2_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap2_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap2_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap3_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap3_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap3_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap3_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap3_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap3_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap3_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap3_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap4_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap4_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap4_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap4_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap4_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap4_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap4_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap4_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap5_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap5_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap5_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap5_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap5_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap5_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap5_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap5_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap6_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap6_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap6_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap6_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap6_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap6_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap6_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap6_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap7_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap7_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap7_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap7_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap7_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap7_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap7_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap7_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  reg boot_cap8_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  reg [31:0] boot_cap8_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap8_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap8_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap8_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap8_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap8_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap8_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:837" *)
  wire boot_cap9_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [31:0] boot_cap9_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap9_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire \boot_cap9_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [8:0] \boot_cap9_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [1:0] \boot_cap9_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [2:0] \boot_cap9_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:838" *)
  wire [15:0] \boot_cap9_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:631" *)
  reg [3:0] boot_cap_wr_addr;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  reg [95:0] boot_cap_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire [31:0] \boot_cap_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire \boot_cap_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire \boot_cap_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire [8:0] \boot_cap_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire [1:0] \boot_cap_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire [2:0] \boot_cap_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire [15:0] \boot_cap_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire [31:0] \boot_cap_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/core.py:632" *)
  wire [31:0] \boot_cap_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/core.py:630" *)
  reg boot_cap_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:78" *)
  output boot_complete;
  wire boot_complete;
  (* src = "/home/runner/workspace/hardware/core.py:76" *)
  input boot_start;
  wire boot_start;
  (* src = "/home/runner/workspace/hardware/core.py:77" *)
  reg [2:0] boot_state = 3'h0;
  (* init = 3'h0 *)
  (* src = "/home/runner/workspace/hardware/core.py:245" *)
  wire [2:0] boot_state_reg;
  (* src = "/home/runner/workspace/hardware/core.py:306" *)
  reg branch_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:526" *)
  wire [31:0] branch_sx32;
  (* src = "/home/runner/workspace/hardware/core.py:525" *)
  wire branch_taken;
  (* src = "/home/runner/workspace/hardware/ret.py:15" *)
  wire busy;
  (* src = "/home/runner/workspace/hardware/dread.py:38" *)
  wire \busy$19 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:37" *)
  wire \busy$20 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:55" *)
  wire \busy$35 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:20" *)
  wire \busy$40 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:353" *)
  wire \busy$41 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:33" *)
  wire \busy$42 ;
  (* src = "/home/runner/workspace/hardware/call.py:18" *)
  wire call_busy;
  (* src = "/home/runner/workspace/hardware/call.py:21" *)
  wire call_fault;
  (* src = "/home/runner/workspace/hardware/call.py:16" *)
  wire [14:0] call_imm;
  (* src = "/home/runner/workspace/hardware/decoder.py:58" *)
  wire [14:0] \call_imm$320 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:19" *)
  wire [14:0] \call_imm$472 ;
  (* src = "/home/runner/workspace/hardware/decoder.py:57" *)
  wire [14:0] call_mask;
  (* src = "/home/runner/workspace/hardware/call.py:20" *)
  wire call_normal_complete;
  (* src = "/home/runner/workspace/hardware/core.py:939" *)
  wire call_src_is_outform;
  (* src = "/home/runner/workspace/hardware/call.py:13" *)
  wire call_start;
  (* src = "/home/runner/workspace/hardware/core.py:381" *)
  wire call_start_sig;
  (* src = "/home/runner/workspace/hardware/call.py:68" *)
  wire [14:0] caller_pc;
  (* src = "/home/runner/workspace/hardware/decoder.py:56" *)
  wire [14:0] cap_index;
  (* src = "/home/runner/workspace/hardware/core.py:1953" *)
  reg [14:0] cc_off_ni;
  (* src = "/home/runner/workspace/hardware/change.py:15" *)
  wire change_busy;
  (* src = "/home/runner/workspace/hardware/change.py:17" *)
  wire change_fault;
  (* src = "/home/runner/workspace/hardware/change.py:14" *)
  wire [15:0] change_mask;
  (* src = "/home/runner/workspace/hardware/change.py:11" *)
  wire change_start;
  (* src = "/home/runner/workspace/hardware/core.py:1333" *)
  wire change_start_sig;
  (* src = "/home/runner/workspace/hardware/perm_check.py:58" *)
  wire check_domain_purity;
  (* src = "/home/runner/workspace/hardware/perm_check.py:36" *)
  wire check_valid;
  (* src = "/home/runner/workspace/hardware/decoder.py:50" *)
  wire [4:0] church_op;
  (* src = "/home/runner/workspace/hardware/core.py:246" *)
  wire clear_all;
  (* src = "/home/runner/workspace/hardware/registers.py:58" *)
  wire \clear_all$93 ;
  (* src = "/home/runner/workspace/hardware/core.py:70" *)
  output [31:0] clist_addr;
  reg [31:0] clist_addr;
  (* src = "/home/runner/workspace/hardware/core.py:71" *)
  wire clist_rd_en;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  output [31:0] clist_wr_data;
  reg [31:0] clist_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire \clist_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire \clist_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [8:0] \clist_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [1:0] \clist_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [2:0] \clist_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:73" *)
  wire [15:0] \clist_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:74" *)
  output clist_wr_en;
  reg clist_wr_en;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/cload.py:56" *)
  wire cload_busy;
  (* src = "/home/runner/workspace/hardware/ret.py:58" *)
  wire [31:0] cload_e_gt;
  (* src = "/home/runner/workspace/hardware/cload.py:58" *)
  wire cload_fault;
  (* src = "/home/runner/workspace/hardware/cload.py:59" *)
  wire [4:0] cload_fault_type;
  (* src = "/home/runner/workspace/hardware/core.py:315" *)
  reg cload_pending = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/cload.py:55" *)
  wire cload_start;
  (* src = "/home/runner/workspace/hardware/call.py:93" *)
  wire [31:0] code_hi_out;
  (* src = "/home/runner/workspace/hardware/core.py:239" *)
  reg [31:0] code_hi_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:92" *)
  wire [31:0] code_lo_out;
  (* src = "/home/runner/workspace/hardware/core.py:238" *)
  reg [31:0] code_lo_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/ret.py:16" *)
  wire complete;
  (* src = "/home/runner/workspace/hardware/core.py:295" *)
  wire cond_exec_enable;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr0_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr0_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr0_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr0_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr0_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr0_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr0_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr0_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr10_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr10_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr10_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr10_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr10_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr10_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr10_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr10_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr11_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr11_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr11_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr11_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr11_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr11_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr11_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr11_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr12_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr12_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr12_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr12_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr12_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr12_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr12_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr12_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [95:0] cr12_thread;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [95:0] \cr12_thread$335 ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [31:0] \cr12_thread$335.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire \cr12_thread$335.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire \cr12_thread$335.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [8:0] \cr12_thread$335.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [1:0] \cr12_thread$335.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [2:0] \cr12_thread$335.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [15:0] \cr12_thread$335.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [31:0] \cr12_thread$335.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [31:0] \cr12_thread$335.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [95:0] \cr12_thread$351 ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [31:0] \cr12_thread$351.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire \cr12_thread$351.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire \cr12_thread$351.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [8:0] \cr12_thread$351.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [1:0] \cr12_thread$351.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [2:0] \cr12_thread$351.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [15:0] \cr12_thread$351.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [31:0] \cr12_thread$351.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [31:0] \cr12_thread$351.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [95:0] \cr12_thread$447 ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [31:0] \cr12_thread$447.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire \cr12_thread$447.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire \cr12_thread$447.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [8:0] \cr12_thread$447.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [1:0] \cr12_thread$447.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [2:0] \cr12_thread$447.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [15:0] \cr12_thread$447.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [31:0] \cr12_thread$447.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [31:0] \cr12_thread$447.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [31:0] \cr12_thread.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire \cr12_thread.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire \cr12_thread.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [8:0] \cr12_thread.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [1:0] \cr12_thread.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [2:0] \cr12_thread.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [15:0] \cr12_thread.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [31:0] \cr12_thread.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [31:0] \cr12_thread.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr13_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr13_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr13_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr13_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr13_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr13_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr13_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr13_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [95:0] cr14_code;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [95:0] \cr14_code$326 ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [31:0] \cr14_code$326.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire \cr14_code$326.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire \cr14_code$326.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [8:0] \cr14_code$326.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [1:0] \cr14_code$326.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [2:0] \cr14_code$326.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [15:0] \cr14_code$326.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [31:0] \cr14_code$326.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [31:0] \cr14_code$326.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [31:0] \cr14_code.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire \cr14_code.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire \cr14_code.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [8:0] \cr14_code.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [1:0] \cr14_code.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [2:0] \cr14_code.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [15:0] \cr14_code.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [31:0] \cr14_code.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [31:0] \cr14_code.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/core.py:888" *)
  reg [31:0] cr14_gt;
  (* src = "/home/runner/workspace/hardware/core.py:888" *)
  wire \cr14_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:888" *)
  wire \cr14_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:888" *)
  wire [8:0] \cr14_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:888" *)
  wire [1:0] \cr14_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:888" *)
  wire [2:0] \cr14_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:888" *)
  wire [15:0] \cr14_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr14_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr14_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr14_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr14_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr14_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr14_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr14_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr14_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr15_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr15_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr15_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr15_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr15_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr15_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr15_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr15_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:156" *)
  wire cr15_m_flag;
  (* src = "/home/runner/workspace/hardware/registers.py:96" *)
  wire \cr15_m_flag$174 ;
  (* src = "/home/runner/workspace/hardware/change.py:60" *)
  wire cr15_m_flag_in;
  (* src = "/home/runner/workspace/hardware/core.py:154" *)
  wire cr15_m_set;
  (* src = "/home/runner/workspace/hardware/core.py:711" *)
  wire [31:0] cr15_m_set_integrity;
  (* src = "/home/runner/workspace/hardware/core.py:155" *)
  wire cr15_m_writeback_trigger;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [95:0] \cr15_namespace$324 ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [31:0] \cr15_namespace$324.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire \cr15_namespace$324.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire \cr15_namespace$324.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [8:0] \cr15_namespace$324.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [1:0] \cr15_namespace$324.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [2:0] \cr15_namespace$324.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [15:0] \cr15_namespace$324.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [31:0] \cr15_namespace$324.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [31:0] \cr15_namespace$324.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [95:0] \cr15_namespace$357 ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [31:0] \cr15_namespace$357.word0_gt ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire \cr15_namespace$357.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire \cr15_namespace$357.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [8:0] \cr15_namespace$357.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [1:0] \cr15_namespace$357.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [2:0] \cr15_namespace$357.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [15:0] \cr15_namespace$357.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [31:0] \cr15_namespace$357.word1_location ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [31:0] \cr15_namespace$357.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [95:0] \cr15_namespace$379 ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [31:0] \cr15_namespace$379.word0_gt ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire \cr15_namespace$379.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire \cr15_namespace$379.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [8:0] \cr15_namespace$379.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [1:0] \cr15_namespace$379.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [2:0] \cr15_namespace$379.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [15:0] \cr15_namespace$379.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [31:0] \cr15_namespace$379.word1_location ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [31:0] \cr15_namespace$379.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [95:0] \cr15_namespace$448 ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [31:0] \cr15_namespace$448.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire \cr15_namespace$448.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire \cr15_namespace$448.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [8:0] \cr15_namespace$448.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [1:0] \cr15_namespace$448.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [2:0] \cr15_namespace$448.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [15:0] \cr15_namespace$448.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [31:0] \cr15_namespace$448.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [31:0] \cr15_namespace$448.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [95:0] \cr15_namespace$462 ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [31:0] \cr15_namespace$462.word0_gt ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire \cr15_namespace$462.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire \cr15_namespace$462.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [8:0] \cr15_namespace$462.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [1:0] \cr15_namespace$462.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [2:0] \cr15_namespace$462.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [15:0] \cr15_namespace$462.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [31:0] \cr15_namespace$462.word1_location ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [31:0] \cr15_namespace$462.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [95:0] \cr15_namespace$475 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [31:0] \cr15_namespace$475.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire \cr15_namespace$475.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire \cr15_namespace$475.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [8:0] \cr15_namespace$475.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [1:0] \cr15_namespace$475.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [2:0] \cr15_namespace$475.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [15:0] \cr15_namespace$475.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [31:0] \cr15_namespace$475.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [31:0] \cr15_namespace$475.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [95:0] \cr15_namespace$484 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [31:0] \cr15_namespace$484.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire \cr15_namespace$484.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire \cr15_namespace$484.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [8:0] \cr15_namespace$484.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [1:0] \cr15_namespace$484.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [2:0] \cr15_namespace$484.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [15:0] \cr15_namespace$484.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [31:0] \cr15_namespace$484.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [31:0] \cr15_namespace$484.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [95:0] \cr15_namespace$506 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [31:0] \cr15_namespace$506.word0_gt ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire \cr15_namespace$506.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire \cr15_namespace$506.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [8:0] \cr15_namespace$506.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [1:0] \cr15_namespace$506.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [2:0] \cr15_namespace$506.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [15:0] \cr15_namespace$506.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [31:0] \cr15_namespace$506.word1_location ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [31:0] \cr15_namespace$506.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [95:0] \cr15_namespace$665 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace$665.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace$665.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace$665.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace$665.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace$665.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace$665.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace$665.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace$665.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace$665.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr1_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr1_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr1_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr1_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr1_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr1_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr1_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr1_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr2_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr2_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr2_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr2_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr2_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr2_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr2_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr2_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr3_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr3_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr3_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr3_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr3_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr3_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr3_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr3_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr4_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr4_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr4_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr4_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr4_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr4_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr4_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr4_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr5_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr5_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr5_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr5_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr5_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr5_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr5_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr5_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [95:0] cr5_heap;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [95:0] \cr5_heap$332 ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [31:0] \cr5_heap$332.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire \cr5_heap$332.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire \cr5_heap$332.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [8:0] \cr5_heap$332.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [1:0] \cr5_heap$332.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [2:0] \cr5_heap$332.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [15:0] \cr5_heap$332.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [31:0] \cr5_heap$332.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [31:0] \cr5_heap$332.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [95:0] \cr5_heap$350 ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [31:0] \cr5_heap$350.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire \cr5_heap$350.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire \cr5_heap$350.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [8:0] \cr5_heap$350.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [1:0] \cr5_heap$350.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [2:0] \cr5_heap$350.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [15:0] \cr5_heap$350.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [31:0] \cr5_heap$350.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [31:0] \cr5_heap$350.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [31:0] \cr5_heap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire \cr5_heap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire \cr5_heap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [8:0] \cr5_heap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [1:0] \cr5_heap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [2:0] \cr5_heap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [15:0] \cr5_heap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [31:0] \cr5_heap.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [31:0] \cr5_heap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr6_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr6_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr6_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr6_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr6_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr6_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr6_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr6_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr7_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr7_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr7_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr7_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr7_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr7_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr7_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr7_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr8_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr8_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr8_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr8_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr8_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr8_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr8_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr8_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [31:0] cr9_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr9_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr9_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr9_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr9_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr9_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr9_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  wire cr9_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:64" *)
  wire [11:0] cr_b_clear_mask;
  (* src = "/home/runner/workspace/hardware/call.py:85" *)
  wire [11:0] \cr_b_clear_mask$340 ;
  (* src = "/home/runner/workspace/hardware/decoder.py:51" *)
  wire [3:0] cr_dst;
  (* src = "/home/runner/workspace/hardware/save.py:13" *)
  wire [3:0] \cr_dst$375 ;
  (* src = "/home/runner/workspace/hardware/load.py:10" *)
  wire [3:0] \cr_dst$437 ;
  (* src = "/home/runner/workspace/hardware/change.py:26" *)
  wire [3:0] \cr_dst$442 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:16" *)
  wire [3:0] \cr_dst$468 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:351" *)
  wire [3:0] \cr_dst$481 ;
  (* src = "/home/runner/workspace/hardware/registers.py:65" *)
  wire [11:0] cr_null_mask;
  (* src = "/home/runner/workspace/hardware/call.py:86" *)
  wire [11:0] \cr_null_mask$342 ;
  (* src = "/home/runner/workspace/hardware/registers.py:20" *)
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/dwrite.py:47" *)
  wire [3:0] \cr_rd_addr$53 ;
  (* src = "/home/runner/workspace/hardware/dread.py:48" *)
  wire [3:0] \cr_rd_addr$54 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:358" *)
  wire [3:0] \cr_rd_addr$55 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:25" *)
  wire [3:0] \cr_rd_addr$56 ;
  (* src = "/home/runner/workspace/hardware/switch.py:20" *)
  wire [3:0] \cr_rd_addr$57 ;
  (* src = "/home/runner/workspace/hardware/change.py:20" *)
  wire [3:0] \cr_rd_addr$58 ;
  (* src = "/home/runner/workspace/hardware/save.py:20" *)
  wire [3:0] \cr_rd_addr$59 ;
  (* src = "/home/runner/workspace/hardware/ret.py:21" *)
  wire [3:0] \cr_rd_addr$60 ;
  (* src = "/home/runner/workspace/hardware/call.py:24" *)
  wire [3:0] \cr_rd_addr$61 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:33" *)
  wire [3:0] \cr_rd_addr$62 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:17" *)
  wire [3:0] \cr_rd_addr$63 ;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  wire [3:0] \cr_rd_addr$64 ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [95:0] \cr_rd_data$323 ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [31:0] \cr_rd_data$323.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire \cr_rd_data$323.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire \cr_rd_data$323.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [8:0] \cr_rd_data$323.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [1:0] \cr_rd_data$323.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [2:0] \cr_rd_data$323.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [15:0] \cr_rd_data$323.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [31:0] \cr_rd_data$323.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [31:0] \cr_rd_data$323.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [95:0] \cr_rd_data$346 ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [31:0] \cr_rd_data$346.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire \cr_rd_data$346.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire \cr_rd_data$346.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [8:0] \cr_rd_data$346.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [1:0] \cr_rd_data$346.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [2:0] \cr_rd_data$346.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [15:0] \cr_rd_data$346.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [31:0] \cr_rd_data$346.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [31:0] \cr_rd_data$346.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [95:0] \cr_rd_data$362 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [31:0] \cr_rd_data$362.word0_gt ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire \cr_rd_data$362.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire \cr_rd_data$362.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [8:0] \cr_rd_data$362.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [1:0] \cr_rd_data$362.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [2:0] \cr_rd_data$362.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [15:0] \cr_rd_data$362.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [31:0] \cr_rd_data$362.word1_location ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [31:0] \cr_rd_data$362.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [95:0] \cr_rd_data$370 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [31:0] \cr_rd_data$370.word0_gt ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire \cr_rd_data$370.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire \cr_rd_data$370.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [8:0] \cr_rd_data$370.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [1:0] \cr_rd_data$370.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [2:0] \cr_rd_data$370.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [15:0] \cr_rd_data$370.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [31:0] \cr_rd_data$370.word1_location ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [31:0] \cr_rd_data$370.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [95:0] \cr_rd_data$378 ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [31:0] \cr_rd_data$378.word0_gt ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire \cr_rd_data$378.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire \cr_rd_data$378.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [8:0] \cr_rd_data$378.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [1:0] \cr_rd_data$378.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [2:0] \cr_rd_data$378.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [15:0] \cr_rd_data$378.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [31:0] \cr_rd_data$378.word1_location ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [31:0] \cr_rd_data$378.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [95:0] \cr_rd_data$390 ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [31:0] \cr_rd_data$390.word0_gt ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire \cr_rd_data$390.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire \cr_rd_data$390.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [8:0] \cr_rd_data$390.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [1:0] \cr_rd_data$390.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [2:0] \cr_rd_data$390.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [15:0] \cr_rd_data$390.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [31:0] \cr_rd_data$390.word1_location ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [31:0] \cr_rd_data$390.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [95:0] \cr_rd_data$400 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [31:0] \cr_rd_data$400.word0_gt ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire \cr_rd_data$400.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire \cr_rd_data$400.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [8:0] \cr_rd_data$400.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [1:0] \cr_rd_data$400.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [2:0] \cr_rd_data$400.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [15:0] \cr_rd_data$400.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [31:0] \cr_rd_data$400.word1_location ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [31:0] \cr_rd_data$400.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [95:0] \cr_rd_data$446 ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [31:0] \cr_rd_data$446.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire \cr_rd_data$446.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire \cr_rd_data$446.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [8:0] \cr_rd_data$446.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [1:0] \cr_rd_data$446.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [2:0] \cr_rd_data$446.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [15:0] \cr_rd_data$446.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [31:0] \cr_rd_data$446.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [31:0] \cr_rd_data$446.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [95:0] \cr_rd_data$461 ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [31:0] \cr_rd_data$461.word0_gt ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire \cr_rd_data$461.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire \cr_rd_data$461.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [8:0] \cr_rd_data$461.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [1:0] \cr_rd_data$461.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [2:0] \cr_rd_data$461.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [15:0] \cr_rd_data$461.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [31:0] \cr_rd_data$461.word1_location ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [31:0] \cr_rd_data$461.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [95:0] \cr_rd_data$474 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [31:0] \cr_rd_data$474.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire \cr_rd_data$474.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire \cr_rd_data$474.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [8:0] \cr_rd_data$474.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [1:0] \cr_rd_data$474.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [2:0] \cr_rd_data$474.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [15:0] \cr_rd_data$474.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [31:0] \cr_rd_data$474.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [31:0] \cr_rd_data$474.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [95:0] \cr_rd_data$483 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [31:0] \cr_rd_data$483.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire \cr_rd_data$483.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire \cr_rd_data$483.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [8:0] \cr_rd_data$483.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [1:0] \cr_rd_data$483.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [2:0] \cr_rd_data$483.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [15:0] \cr_rd_data$483.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [31:0] \cr_rd_data$483.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [31:0] \cr_rd_data$483.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [95:0] \cr_rd_data$664 ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data$664.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data$664.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data$664.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data$664.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data$664.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data$664.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data$664.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data$664.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data$664.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/core.py:481" *)
  wire [31:0] cr_rd_data_gt;
  (* src = "/home/runner/workspace/hardware/core.py:481" *)
  wire \cr_rd_data_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:481" *)
  wire \cr_rd_data_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:481" *)
  wire [8:0] \cr_rd_data_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:481" *)
  wire [1:0] \cr_rd_data_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:481" *)
  wire [2:0] \cr_rd_data_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:481" *)
  wire [15:0] \cr_rd_data_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/decoder.py:52" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/call.py:14" *)
  wire [3:0] \cr_src$317 ;
  (* src = "/home/runner/workspace/hardware/ret.py:14" *)
  wire [2:0] \cr_src$345 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:12" *)
  wire [3:0] \cr_src$367 ;
  (* src = "/home/runner/workspace/hardware/save.py:12" *)
  wire [3:0] \cr_src$374 ;
  (* src = "/home/runner/workspace/hardware/dread.py:41" *)
  wire [3:0] \cr_src$386 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:40" *)
  wire [3:0] \cr_src$397 ;
  (* src = "/home/runner/workspace/hardware/load.py:9" *)
  wire [3:0] \cr_src$436 ;
  (* src = "/home/runner/workspace/hardware/change.py:12" *)
  wire [3:0] \cr_src$441 ;
  (* src = "/home/runner/workspace/hardware/switch.py:12" *)
  wire [2:0] \cr_src$458 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:15" *)
  wire [3:0] \cr_src$467 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:350" *)
  wire [3:0] \cr_src$480 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:11" *)
  wire [3:0] cr_target;
  (* src = "/home/runner/workspace/hardware/tperm.py:11" *)
  wire [3:0] \cr_target$366 ;
  (* src = "/home/runner/workspace/hardware/registers.py:23" *)
  wire [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:360" *)
  wire [3:0] \cr_wr_addr$138 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:27" *)
  wire [3:0] \cr_wr_addr$139 ;
  (* src = "/home/runner/workspace/hardware/switch.py:22" *)
  wire [3:0] \cr_wr_addr$140 ;
  (* src = "/home/runner/workspace/hardware/change.py:22" *)
  wire [3:0] \cr_wr_addr$141 ;
  (* src = "/home/runner/workspace/hardware/cload.py:65" *)
  wire [3:0] \cr_wr_addr$142 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:40" *)
  wire [3:0] \cr_wr_addr$143 ;
  (* src = "/home/runner/workspace/hardware/ret.py:23" *)
  wire [3:0] \cr_wr_addr$145 ;
  (* src = "/home/runner/workspace/hardware/call.py:26" *)
  wire [3:0] \cr_wr_addr$146 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:36" *)
  wire [3:0] \cr_wr_addr$147 ;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  wire [3:0] \cr_wr_addr$148 ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [95:0] \cr_wr_data$151 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [31:0] \cr_wr_data$151.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire \cr_wr_data$151.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire \cr_wr_data$151.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [8:0] \cr_wr_data$151.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [1:0] \cr_wr_data$151.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [2:0] \cr_wr_data$151.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [15:0] \cr_wr_data$151.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [31:0] \cr_wr_data$151.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [31:0] \cr_wr_data$151.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [95:0] \cr_wr_data$152 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [31:0] \cr_wr_data$152.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire \cr_wr_data$152.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire \cr_wr_data$152.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [8:0] \cr_wr_data$152.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [1:0] \cr_wr_data$152.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [2:0] \cr_wr_data$152.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [15:0] \cr_wr_data$152.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [31:0] \cr_wr_data$152.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [31:0] \cr_wr_data$152.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [95:0] \cr_wr_data$153 ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [31:0] \cr_wr_data$153.word0_gt ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire \cr_wr_data$153.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire \cr_wr_data$153.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [8:0] \cr_wr_data$153.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [1:0] \cr_wr_data$153.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [2:0] \cr_wr_data$153.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [15:0] \cr_wr_data$153.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [31:0] \cr_wr_data$153.word1_location ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [31:0] \cr_wr_data$153.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [95:0] \cr_wr_data$154 ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [31:0] \cr_wr_data$154.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire \cr_wr_data$154.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire \cr_wr_data$154.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [8:0] \cr_wr_data$154.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [1:0] \cr_wr_data$154.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [2:0] \cr_wr_data$154.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [15:0] \cr_wr_data$154.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [31:0] \cr_wr_data$154.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [31:0] \cr_wr_data$154.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [95:0] \cr_wr_data$155 ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [31:0] \cr_wr_data$155.word0_gt ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire \cr_wr_data$155.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire \cr_wr_data$155.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [8:0] \cr_wr_data$155.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [1:0] \cr_wr_data$155.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [2:0] \cr_wr_data$155.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [15:0] \cr_wr_data$155.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [31:0] \cr_wr_data$155.word1_location ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [31:0] \cr_wr_data$155.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [95:0] \cr_wr_data$156 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [31:0] \cr_wr_data$156.word0_gt ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire \cr_wr_data$156.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire \cr_wr_data$156.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [8:0] \cr_wr_data$156.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [1:0] \cr_wr_data$156.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [2:0] \cr_wr_data$156.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [15:0] \cr_wr_data$156.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [31:0] \cr_wr_data$156.word1_location ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [31:0] \cr_wr_data$156.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [95:0] \cr_wr_data$158 ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [31:0] \cr_wr_data$158.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire \cr_wr_data$158.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire \cr_wr_data$158.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [8:0] \cr_wr_data$158.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [1:0] \cr_wr_data$158.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [2:0] \cr_wr_data$158.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [15:0] \cr_wr_data$158.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [31:0] \cr_wr_data$158.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [31:0] \cr_wr_data$158.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [95:0] \cr_wr_data$159 ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [31:0] \cr_wr_data$159.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire \cr_wr_data$159.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire \cr_wr_data$159.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [8:0] \cr_wr_data$159.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [1:0] \cr_wr_data$159.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [2:0] \cr_wr_data$159.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [15:0] \cr_wr_data$159.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [31:0] \cr_wr_data$159.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [31:0] \cr_wr_data$159.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [95:0] \cr_wr_data$160 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [31:0] \cr_wr_data$160.word0_gt ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire \cr_wr_data$160.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire \cr_wr_data$160.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [8:0] \cr_wr_data$160.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [1:0] \cr_wr_data$160.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [2:0] \cr_wr_data$160.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [15:0] \cr_wr_data$160.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [31:0] \cr_wr_data$160.word1_location ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [31:0] \cr_wr_data$160.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [95:0] \cr_wr_data$161 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$161.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$161.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$161.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data$161.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data$161.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data$161.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data$161.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$161.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$161.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  wire cr_wr_en;
  (* src = "/home/runner/workspace/hardware/tperm.py:38" *)
  wire \cr_wr_en$132 ;
  (* src = "/home/runner/workspace/hardware/call.py:28" *)
  wire \cr_wr_en$133 ;
  (* src = "/home/runner/workspace/hardware/ret.py:25" *)
  wire \cr_wr_en$134 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:39" *)
  wire \cr_wr_en$136 ;
  (* src = "/home/runner/workspace/hardware/cload.py:67" *)
  wire \cr_wr_en$137 ;
  (* src = "/home/runner/workspace/hardware/registers.py:25" *)
  wire \cr_wr_en$164 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:29" *)
  wire \cr_wr_en$165 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:362" *)
  wire \cr_wr_en$166 ;
  (* src = "/home/runner/workspace/hardware/change.py:24" *)
  wire \cr_wr_en$167 ;
  (* src = "/home/runner/workspace/hardware/switch.py:24" *)
  wire \cr_wr_en$168 ;
  (* src = "/home/runner/workspace/hardware/core.py:314" *)
  reg cross_domain_ret = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:127" *)
  wire [3:0] dbg_cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [95:0] dbg_cr_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [31:0] \dbg_cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire \dbg_cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire \dbg_cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [8:0] \dbg_cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [1:0] \dbg_cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [2:0] \dbg_cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [15:0] \dbg_cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [31:0] \dbg_cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/core.py:128" *)
  wire [31:0] \dbg_cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/core.py:126" *)
  wire dbg_cr_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:157" *)
  wire [31:0] dbg_m_dr11;
  (* src = "/home/runner/workspace/hardware/core.py:158" *)
  wire [31:0] dbg_m_dr12;
  (* src = "/home/runner/workspace/hardware/core.py:159" *)
  wire [31:0] dbg_m_dr13;
  (* src = "/home/runner/workspace/hardware/core.py:160" *)
  wire [31:0] dbg_m_dr14;
  (* src = "/home/runner/workspace/hardware/core.py:161" *)
  wire [31:0] dbg_m_dr15;
  (* src = "/home/runner/workspace/hardware/core.py:135" *)
  wire dbg_outform_done_inject;
  (* src = "/home/runner/workspace/hardware/core.py:136" *)
  wire [31:0] dbg_outform_result_gt;
  (* src = "/home/runner/workspace/hardware/core.py:57" *)
  output [31:0] dmem_addr;
  reg [31:0] dmem_addr;
  (* src = "/home/runner/workspace/hardware/dread.py:59" *)
  wire [31:0] \dmem_addr$734 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:58" *)
  wire [31:0] \dmem_addr$735 ;
  (* src = "/home/runner/workspace/hardware/core.py:59" *)
  wire [31:0] dmem_rd_data;
  (* src = "/home/runner/workspace/hardware/dread.py:61" *)
  wire [31:0] \dmem_rd_data$391 ;
  (* src = "/home/runner/workspace/hardware/core.py:58" *)
  output dmem_rd_en;
  reg dmem_rd_en;
  (* src = "/home/runner/workspace/hardware/dread.py:60" *)
  wire \dmem_rd_en$719 ;
  (* src = "/home/runner/workspace/hardware/core.py:60" *)
  wire dmem_rd_valid;
  (* src = "/home/runner/workspace/hardware/core.py:61" *)
  output [31:0] dmem_wr_data;
  reg [31:0] dmem_wr_data;
  (* src = "/home/runner/workspace/hardware/dwrite.py:59" *)
  wire [31:0] \dmem_wr_data$738 ;
  (* src = "/home/runner/workspace/hardware/core.py:62" *)
  output dmem_wr_en;
  reg dmem_wr_en;
  (* src = "/home/runner/workspace/hardware/dwrite.py:60" *)
  wire \dmem_wr_en$720 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:50" *)
  wire [31:0] dr1_wr_data;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:49" *)
  wire dr1_wr_en;
  (* src = "/home/runner/workspace/hardware/dread.py:42" *)
  wire [3:0] dr_dst;
  (* src = "/home/runner/workspace/hardware/dwrite.py:51" *)
  wire [3:0] dr_rd_addr;
  (* src = "/home/runner/workspace/hardware/dread.py:52" *)
  wire [3:0] \dr_rd_addr$411 ;
  (* src = "/home/runner/workspace/hardware/registers.py:46" *)
  wire [3:0] dr_rd_addr1;
  (* src = "/home/runner/workspace/hardware/registers.py:48" *)
  wire [3:0] dr_rd_addr2;
  (* src = "/home/runner/workspace/hardware/dwrite.py:55" *)
  wire [3:0] \dr_rd_addr2$410 ;
  (* src = "/home/runner/workspace/hardware/dread.py:53" *)
  wire [31:0] dr_rd_data;
  (* src = "/home/runner/workspace/hardware/dwrite.py:52" *)
  wire [31:0] \dr_rd_data$401 ;
  (* src = "/home/runner/workspace/hardware/change.py:46" *)
  wire [31:0] \dr_rd_data$452 ;
  (* src = "/home/runner/workspace/hardware/registers.py:47" *)
  wire [31:0] dr_rd_data1;
  (* src = "/home/runner/workspace/hardware/registers.py:49" *)
  wire [31:0] dr_rd_data2;
  (* src = "/home/runner/workspace/hardware/dwrite.py:56" *)
  wire [31:0] \dr_rd_data2$403 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:41" *)
  wire [3:0] dr_src;
  (* src = "/home/runner/workspace/hardware/registers.py:50" *)
  reg [3:0] dr_wr_addr;
  (* src = "/home/runner/workspace/hardware/dread.py:55" *)
  wire [3:0] \dr_wr_addr$104 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:45" *)
  wire [3:0] \dr_wr_addr$124 ;
  (* src = "/home/runner/workspace/hardware/registers.py:51" *)
  reg [31:0] dr_wr_data;
  (* src = "/home/runner/workspace/hardware/dread.py:56" *)
  wire [31:0] \dr_wr_data$106 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:46" *)
  wire [31:0] \dr_wr_data$125 ;
  (* src = "/home/runner/workspace/hardware/dread.py:57" *)
  wire dr_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:52" *)
  reg \dr_wr_en$107 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:44" *)
  wire \dr_wr_en$123 ;
  (* src = "/home/runner/workspace/hardware/core.py:1068" *)
  wire dread_start_sig;
  (* src = "/home/runner/workspace/hardware/core.py:1083" *)
  wire dwrite_start_sig;
  (* src = "/home/runner/workspace/hardware/cload.py:61" *)
  wire [31:0] e_gt;
  (* src = "/home/runner/workspace/hardware/core.py:921" *)
  wire [2:0] effective_target;
  (* src = "/home/runner/workspace/hardware/decoder.py:67" *)
  wire [7:0] eloadcall_clist_row;
  (* src = "/home/runner/workspace/hardware/decoder.py:66" *)
  wire [6:0] eloadcall_method_index;
  (* src = "/home/runner/workspace/hardware/core.py:1373" *)
  wire eloadcall_start_sig;
  (* src = "/home/runner/workspace/hardware/decoder.py:37" *)
  wire exec_enable;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:22" *)
  wire fault;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:355" *)
  wire \fault$634 ;
  (* src = "/home/runner/workspace/hardware/dread.py:45" *)
  wire \fault$635 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:44" *)
  wire \fault$636 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:57" *)
  wire \fault$638 ;
  (* src = "/home/runner/workspace/hardware/core.py:84" *)
  output [4:0] \fault$639 ;
  reg [4:0] \fault$639 ;
  (* src = "/home/runner/workspace/hardware/decoder.py:69" *)
  wire [3:0] \fault$641 ;
  (* src = "/home/runner/workspace/hardware/core.py:93" *)
  wire [31:0] fault_cr14;
  (* src = "/home/runner/workspace/hardware/core.py:91" *)
  wire [31:0] fault_gt;
  (* src = "/home/runner/workspace/hardware/core.py:92" *)
  reg [31:0] fault_instr = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/core.py:2224" *)
  wire [31:0] fault_instr_latch;
  (* src = "/home/runner/workspace/hardware/core.py:94" *)
  reg [3:0] fault_stage = 4'h0;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/core.py:2225" *)
  wire [3:0] fault_stage_latch;
  (* src = "/home/runner/workspace/hardware/core.py:2200" *)
  reg [3:0] fault_stage_w;
  (* src = "/home/runner/workspace/hardware/perm_check.py:55" *)
  wire [3:0] fault_type;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:15" *)
  wire [3:0] \fault_type$643 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:23" *)
  wire [3:0] \fault_type$644 ;
  (* src = "/home/runner/workspace/hardware/call.py:22" *)
  wire [4:0] \fault_type$645 ;
  (* src = "/home/runner/workspace/hardware/ret.py:18" *)
  wire [4:0] \fault_type$646 ;
  (* src = "/home/runner/workspace/hardware/save.py:18" *)
  wire [3:0] \fault_type$647 ;
  (* src = "/home/runner/workspace/hardware/load.py:15" *)
  wire [4:0] \fault_type$648 ;
  (* src = "/home/runner/workspace/hardware/change.py:18" *)
  wire [4:0] \fault_type$649 ;
  (* src = "/home/runner/workspace/hardware/switch.py:18" *)
  wire [3:0] \fault_type$650 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:23" *)
  wire [3:0] \fault_type$651 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:356" *)
  wire [3:0] \fault_type$652 ;
  (* src = "/home/runner/workspace/hardware/dread.py:46" *)
  wire [4:0] \fault_type$653 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:45" *)
  wire [4:0] \fault_type$654 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:58" *)
  wire [4:0] \fault_type$656 ;
  (* src = "/home/runner/workspace/hardware/decoder.py:70" *)
  wire fault_valid;
  (* src = "/home/runner/workspace/hardware/perm_check.py:56" *)
  wire \fault_valid$624 ;
  (* src = "/home/runner/workspace/hardware/ret.py:17" *)
  wire \fault_valid$628 ;
  (* src = "/home/runner/workspace/hardware/core.py:85" *)
  output \fault_valid$640 ;
  reg \fault_valid$640 ;
  (* src = "/home/runner/workspace/hardware/core.py:240" *)
  reg fence_pending_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:296" *)
  wire fetch_bounds_fault;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire [3:0] flags;
  (* src = "/home/runner/workspace/hardware/core.py:100" *)
  wire [3:0] \flags$208 ;
  (* src = "/home/runner/workspace/hardware/core.py:100" *)
  wire \flags$208.C ;
  (* src = "/home/runner/workspace/hardware/core.py:100" *)
  wire \flags$208.N ;
  (* src = "/home/runner/workspace/hardware/core.py:100" *)
  wire \flags$208.V ;
  (* src = "/home/runner/workspace/hardware/core.py:100" *)
  wire \flags$208.Z ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire [3:0] \flags$454 ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags$454.C ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags$454.N ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags$454.V ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags$454.Z ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire [3:0] \flags$9 ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags$9.C ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags$9.N ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags$9.V ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags$9.Z ;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.C ;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.N ;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.V ;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.Z ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  reg [3:0] flags_in;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.C ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.N ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.V ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.Z ;
  (* src = "/home/runner/workspace/hardware/registers.py:56" *)
  reg flags_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:97" *)
  input [31:0] free_run_nia;
  wire [31:0] free_run_nia;
  (* src = "/home/runner/workspace/hardware/core.py:96" *)
  input free_run_start;
  wire free_run_start;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:26" *)
  wire [31:0] garbage_count;
  (* src = "/home/runner/workspace/hardware/mload.py:66" *)
  wire gbit_reset_done;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:13" *)
  wire gc_busy;
  (* src = "/home/runner/workspace/hardware/core.py:81" *)
  wire \gc_busy$80 ;
  (* src = "/home/runner/workspace/hardware/core.py:82" *)
  wire [31:0] gc_garbage_count;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:11" *)
  wire gc_mark_en;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:10" *)
  wire gc_start;
  (* src = "/home/runner/workspace/hardware/core.py:80" *)
  wire \gc_start$73 ;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:12" *)
  wire gc_sweep_en;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [31:0] gt_in;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire \gt_in.b_flag ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire \gt_in.dom ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [8:0] \gt_in.gt_seq ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [1:0] \gt_in.gt_type ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [2:0] \gt_in.perm ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [15:0] \gt_in.slot_id ;
  (* src = "/home/runner/workspace/hardware/outform.py:85" *)
  wire [31:0] gt_raw;
  (* src = "/home/runner/workspace/hardware/core.py:86" *)
  output halt_valid;
  wire halt_valid;
  (* src = "/home/runner/workspace/hardware/core.py:304" *)
  reg iadd_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:518" *)
  wire [3:0] iadd_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:518" *)
  wire \iadd_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:518" *)
  wire \iadd_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:518" *)
  wire \iadd_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:518" *)
  wire \iadd_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/core.py:511" *)
  wire [32:0] iadd_result;
  (* src = "/home/runner/workspace/hardware/core.py:504" *)
  wire iadd_start_sig;
  (* src = "/home/runner/workspace/hardware/change.py:47" *)
  output [31:0] imem_addr;
  reg [31:0] imem_addr = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:54" *)
  wire [31:0] imem_data;
  (* src = "/home/runner/workspace/hardware/core.py:55" *)
  input imem_valid;
  wire imem_valid;
  (* src = "/home/runner/workspace/hardware/dread.py:43" *)
  wire [14:0] imm;
  (* src = "/home/runner/workspace/hardware/dwrite.py:42" *)
  wire [14:0] \imm$399 ;
  (* src = "/home/runner/workspace/hardware/decoder.py:53" *)
  wire [14:0] immediate;
  (* src = "/home/runner/workspace/hardware/call.py:15" *)
  wire [15:0] index;
  (* src = "/home/runner/workspace/hardware/save.py:14" *)
  wire [15:0] \index$376 ;
  (* src = "/home/runner/workspace/hardware/load.py:11" *)
  wire [15:0] \index$438 ;
  (* src = "/home/runner/workspace/hardware/change.py:13" *)
  wire [15:0] \index$444 ;
  (* src = "/home/runner/workspace/hardware/switch.py:14" *)
  wire [15:0] \index$460 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:17" *)
  wire [15:0] \index$469 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:352" *)
  wire [15:0] \index$482 ;
  (* src = "/home/runner/workspace/hardware/decoder.py:34" *)
  wire instr_valid;
  (* src = "/home/runner/workspace/hardware/core.py:54" *)
  input [31:0] instruction;
  wire [31:0] instruction;
  (* src = "/home/runner/workspace/hardware/church_outform.py:34" *)
  wire intercept_start;
  (* src = "/home/runner/workspace/hardware/core.py:1422" *)
  wire [1:0] irq_dispatch_reason;
  (* src = "/home/runner/workspace/hardware/core.py:1423" *)
  wire [15:0] irq_dispatch_slot;
  (* src = "/home/runner/workspace/hardware/core.py:1421" *)
  wire irq_dispatch_start;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:31" *)
  wire [1:0] irq_reason;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:32" *)
  wire [15:0] irq_slot;
  (* src = "/home/runner/workspace/hardware/decoder.py:46" *)
  wire is_bfext_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:47" *)
  wire is_bfins_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:43" *)
  wire is_branch_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:38" *)
  wire is_church_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:39" *)
  wire is_dread_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:40" *)
  wire is_dwrite_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:41" *)
  wire is_iadd_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:42" *)
  wire is_isub_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:48" *)
  wire is_mcmp_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:44" *)
  wire is_shl_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:45" *)
  wire is_shr_op;
  (* src = "/home/runner/workspace/hardware/core.py:305" *)
  reg isub_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:519" *)
  wire [3:0] isub_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:519" *)
  wire \isub_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:519" *)
  wire \isub_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:519" *)
  wire \isub_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:519" *)
  wire \isub_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/core.py:512" *)
  wire [32:0] isub_result;
  (* src = "/home/runner/workspace/hardware/core.py:505" *)
  wire isub_start_sig;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/ret.py:42" *)
  wire lambda_active;
  (* src = "/home/runner/workspace/hardware/core.py:242" *)
  reg lambda_active_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:12" *)
  wire lambda_busy;
  (* src = "/home/runner/workspace/hardware/ret.py:44" *)
  wire lambda_clear;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:13" *)
  wire lambda_complete;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:14" *)
  wire lambda_fault;
  (* src = "/home/runner/workspace/hardware/ret.py:43" *)
  reg [31:0] lambda_pc = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/core.py:243" *)
  wire [31:0] lambda_pc_reg;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:10" *)
  wire lambda_start;
  (* src = "/home/runner/workspace/hardware/core.py:368" *)
  wire lambda_start_sig;
  (* src = "/home/runner/workspace/hardware/call.py:108" *)
  wire lazy_load_irq;
  (* src = "/home/runner/workspace/hardware/call.py:109" *)
  wire [15:0] lazy_load_ns_slot;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:49" *)
  wire lazy_resolve_irq;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:380" *)
  wire \lazy_resolve_irq$502 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:381" *)
  wire [15:0] lazy_resolve_slot;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:50" *)
  wire [15:0] \lazy_resolve_slot$499 ;
  (* src = "/home/runner/workspace/hardware/load.py:12" *)
  wire load_busy;
  (* src = "/home/runner/workspace/hardware/load.py:14" *)
  wire load_fault;
  (* src = "/home/runner/workspace/hardware/load.py:8" *)
  wire load_start;
  (* src = "/home/runner/workspace/hardware/core.py:1321" *)
  wire load_start_sig;
  (* src = "/home/runner/workspace/hardware/core.py:1192" *)
  wire [31:0] lsr_result;
  (* src = "/home/runner/workspace/hardware/core.py:1877" *)
  reg [14:0] lsz_c_ni;
  (* src = "/home/runner/workspace/hardware/registers.py:72" *)
  reg m_clear_en;
  (* src = "/home/runner/workspace/hardware/registers.py:89" *)
  wire [31:0] m_dr11;
  (* src = "/home/runner/workspace/hardware/registers.py:90" *)
  wire [31:0] m_dr12;
  (* src = "/home/runner/workspace/hardware/registers.py:91" *)
  wire [31:0] m_dr13;
  (* src = "/home/runner/workspace/hardware/registers.py:92" *)
  wire [31:0] m_dr14;
  (* src = "/home/runner/workspace/hardware/registers.py:93" *)
  wire [31:0] m_dr15;
  (* src = "/home/runner/workspace/hardware/change.py:27" *)
  wire m_elevated;
  (* src = "/home/runner/workspace/hardware/registers.py:73" *)
  wire m_flag_restore_en;
  (* src = "/home/runner/workspace/hardware/change.py:61" *)
  wire \m_flag_restore_en$186 ;
  (* src = "/home/runner/workspace/hardware/registers.py:74" *)
  wire m_flag_restore_val;
  (* src = "/home/runner/workspace/hardware/change.py:62" *)
  wire \m_flag_restore_val$188 ;
  (* src = "/home/runner/workspace/hardware/registers.py:80" *)
  wire [31:0] m_set_dr11;
  (* src = "/home/runner/workspace/hardware/registers.py:81" *)
  wire [31:0] m_set_dr12;
  (* src = "/home/runner/workspace/hardware/registers.py:82" *)
  wire [31:0] m_set_dr13;
  (* src = "/home/runner/workspace/hardware/registers.py:83" *)
  wire [31:0] m_set_dr14;
  (* src = "/home/runner/workspace/hardware/registers.py:84" *)
  wire [31:0] m_set_dr15;
  (* src = "/home/runner/workspace/hardware/registers.py:71" *)
  reg m_set_en;
  (* src = "/home/runner/workspace/hardware/call.py:17" *)
  wire [15:0] mask;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:18" *)
  wire [15:0] \mask$471 ;
  (* src = "/home/runner/workspace/hardware/core.py:311" *)
  reg mcmp_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:524" *)
  wire [3:0] mcmp_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:524" *)
  wire \mcmp_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:524" *)
  wire \mcmp_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:524" *)
  wire \mcmp_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:524" *)
  wire \mcmp_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/core.py:517" *)
  wire [32:0] mcmp_result;
  (* src = "/home/runner/workspace/hardware/core.py:510" *)
  wire mcmp_start_sig;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/cload.py:69" *)
  wire [31:0] \mem_addr$740 ;
  (* src = "/home/runner/workspace/hardware/call.py:46" *)
  wire [31:0] mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/save.py:28" *)
  wire [31:0] \mem_rd_addr$733 ;
  (* src = "/home/runner/workspace/hardware/ret.py:49" *)
  wire [31:0] \mem_rd_addr$743 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:38" *)
  wire [31:0] \mem_rd_addr$746 ;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ret.py:51" *)
  wire [31:0] \mem_rd_data$352 ;
  (* src = "/home/runner/workspace/hardware/cload.py:71" *)
  wire [31:0] \mem_rd_data$358 ;
  (* src = "/home/runner/workspace/hardware/save.py:30" *)
  wire [31:0] \mem_rd_data$381 ;
  (* src = "/home/runner/workspace/hardware/change.py:34" *)
  wire [31:0] \mem_rd_data$449 ;
  (* src = "/home/runner/workspace/hardware/switch.py:29" *)
  wire [31:0] \mem_rd_data$463 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:34" *)
  wire [31:0] \mem_rd_data$476 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:367" *)
  wire [31:0] \mem_rd_data$485 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:40" *)
  wire [31:0] \mem_rd_data$507 ;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  wire [31:0] \mem_rd_data$666 ;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/call.py:47" *)
  wire \mem_rd_en$715 ;
  (* src = "/home/runner/workspace/hardware/save.py:29" *)
  wire \mem_rd_en$718 ;
  (* src = "/home/runner/workspace/hardware/cload.py:70" *)
  wire \mem_rd_en$721 ;
  (* src = "/home/runner/workspace/hardware/ret.py:50" *)
  wire \mem_rd_en$723 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:39" *)
  wire \mem_rd_en$725 ;
  (* src = "/home/runner/workspace/hardware/mload.py:61" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ret.py:52" *)
  wire \mem_rd_valid$353 ;
  (* src = "/home/runner/workspace/hardware/cload.py:72" *)
  wire \mem_rd_valid$359 ;
  (* src = "/home/runner/workspace/hardware/save.py:31" *)
  wire \mem_rd_valid$382 ;
  (* src = "/home/runner/workspace/hardware/change.py:35" *)
  wire \mem_rd_valid$450 ;
  (* src = "/home/runner/workspace/hardware/switch.py:30" *)
  wire \mem_rd_valid$464 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:35" *)
  wire \mem_rd_valid$477 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:368" *)
  wire \mem_rd_valid$486 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:41" *)
  wire \mem_rd_valid$508 ;
  (* src = "/home/runner/workspace/hardware/mload.py:61" *)
  wire \mem_rd_valid$667 ;
  (* src = "/home/runner/workspace/hardware/call.py:52" *)
  wire [31:0] mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/save.py:23" *)
  wire [31:0] \mem_wr_addr$731 ;
  (* src = "/home/runner/workspace/hardware/outform.py:100" *)
  wire [31:0] \mem_wr_addr$741 ;
  (* src = "/home/runner/workspace/hardware/ret.py:54" *)
  wire [31:0] \mem_wr_addr$744 ;
  (* src = "/home/runner/workspace/hardware/mload.py:63" *)
  wire [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/call.py:53" *)
  wire [31:0] \mem_wr_data$730 ;
  (* src = "/home/runner/workspace/hardware/save.py:24" *)
  wire [31:0] \mem_wr_data$732 ;
  (* src = "/home/runner/workspace/hardware/outform.py:101" *)
  wire [31:0] \mem_wr_data$742 ;
  (* src = "/home/runner/workspace/hardware/ret.py:55" *)
  wire [31:0] \mem_wr_data$745 ;
  (* src = "/home/runner/workspace/hardware/save.py:26" *)
  wire mem_wr_done;
  (* src = "/home/runner/workspace/hardware/change.py:39" *)
  wire \mem_wr_done$451 ;
  (* src = "/home/runner/workspace/hardware/mload.py:62" *)
  wire mem_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:54" *)
  wire \mem_wr_en$716 ;
  (* src = "/home/runner/workspace/hardware/save.py:25" *)
  wire \mem_wr_en$717 ;
  (* src = "/home/runner/workspace/hardware/outform.py:102" *)
  wire \mem_wr_en$722 ;
  (* src = "/home/runner/workspace/hardware/ret.py:56" *)
  wire \mem_wr_en$724 ;
  (* src = "/home/runner/workspace/hardware/call.py:99" *)
  wire [31:0] mgt_gt_word;
  (* src = "/home/runner/workspace/hardware/call.py:101" *)
  wire [31:0] mgt_ns_authority;
  (* src = "/home/runner/workspace/hardware/call.py:102" *)
  wire [31:0] mgt_ns_integrity;
  (* src = "/home/runner/workspace/hardware/call.py:100" *)
  wire [31:0] mgt_ns_location;
  (* src = "/home/runner/workspace/hardware/call.py:103" *)
  wire [31:0] mgt_ns_seals;
  (* src = "/home/runner/workspace/hardware/call.py:98" *)
  wire mgt_set_trigger;
  (* src = "/home/runner/workspace/hardware/outform.py:105" *)
  wire [31:0] mint_base;
  (* src = "/home/runner/workspace/hardware/core.py:1822" *)
  reg [31:0] mint_base_reg_ni = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:326" *)
  wire mint_busy;
  (* src = "/home/runner/workspace/hardware/outform.py:104" *)
  wire mint_call;
  (* src = "/home/runner/workspace/hardware/core.py:1831" *)
  reg [14:0] mint_cc_base_reg_ni = 15'h0000;
  (* src = "/home/runner/workspace/hardware/core.py:1824" *)
  reg [7:0] mint_cc_reg_ni = 8'h00;
  (* src = "/home/runner/workspace/hardware/core.py:328" *)
  reg [31:0] mint_clist_addr_d;
  (* src = "/home/runner/workspace/hardware/core.py:331" *)
  reg [31:0] mint_clist_addr_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:1840" *)
  wire [31:0] mint_clist_slot_base_ni;
  (* src = "/home/runner/workspace/hardware/core.py:338" *)
  reg [31:0] mint_clist_wr_data_d;
  (* src = "/home/runner/workspace/hardware/core.py:327" *)
  reg mint_clist_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:1827" *)
  reg [31:0] mint_copy_data_reg_ni = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:1826" *)
  reg [7:0] mint_copy_idx_reg_ni = 8'h00;
  (* src = "/home/runner/workspace/hardware/core.py:1823" *)
  reg [12:0] mint_cw_reg_ni = 13'h0000;
  (* src = "/home/runner/workspace/hardware/core.py:334" *)
  reg [31:0] mint_dmem_addr;
  (* src = "/home/runner/workspace/hardware/core.py:333" *)
  reg mint_dmem_rd_en;
  (* src = "/home/runner/workspace/hardware/outform.py:107" *)
  wire mint_done;
  (* src = "/home/runner/workspace/hardware/core.py:1854" *)
  reg mint_done_comb_ni;
  (* src = "/home/runner/workspace/hardware/core.py:329" *)
  wire [31:0] mint_e_gt_d;
  (* src = "/home/runner/workspace/hardware/outform.py:108" *)
  wire mint_fault;
  (* src = "/home/runner/workspace/hardware/core.py:1855" *)
  reg mint_fault_comb_ni;
  (* src = "/home/runner/workspace/hardware/core.py:1828" *)
  reg [31:0] mint_hdr_reg_ni = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:1851" *)
  wire [31:0] mint_integrity_ni;
  (* src = "/home/runner/workspace/hardware/core.py:332" *)
  reg [14:0] mint_lump_size_reg = 15'h0000;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] mint_noniot_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/core.py:336" *)
  reg [31:0] mint_ns_addr;
  (* src = "/home/runner/workspace/hardware/core.py:1834" *)
  wire [31:0] mint_ns_entry_base_ni;
  (* src = "/home/runner/workspace/hardware/core.py:337" *)
  reg [31:0] mint_ns_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:335" *)
  reg mint_ns_wr_en;
  (* src = "/home/runner/workspace/hardware/outform.py:109" *)
  reg [31:0] mint_result_gt;
  (* src = "/home/runner/workspace/hardware/core.py:1825" *)
  reg [13:0] mint_scan_idx_reg_ni = 14'h0000;
  (* src = "/home/runner/workspace/hardware/core.py:1841" *)
  wire [16:0] mint_slot_id_p3_ni;
  (* src = "/home/runner/workspace/hardware/core.py:330" *)
  reg [15:0] mint_slot_id_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/core.py:1848" *)
  wire [31:0] mint_w2_ni;
  (* src = "/home/runner/workspace/hardware/load.py:25" *)
  wire mload_busy;
  (* src = "/home/runner/workspace/hardware/call.py:32" *)
  wire [3:0] mload_cr_dst;
  (* src = "/home/runner/workspace/hardware/ret.py:32" *)
  wire [3:0] \mload_cr_dst$684 ;
  (* src = "/home/runner/workspace/hardware/load.py:19" *)
  wire [3:0] \mload_cr_dst$691 ;
  (* src = "/home/runner/workspace/hardware/call.py:31" *)
  wire [3:0] mload_cr_src;
  (* src = "/home/runner/workspace/hardware/ret.py:31" *)
  wire [3:0] \mload_cr_src$683 ;
  (* src = "/home/runner/workspace/hardware/load.py:18" *)
  wire [3:0] \mload_cr_src$690 ;
  (* src = "/home/runner/workspace/hardware/call.py:34" *)
  wire mload_direct;
  (* src = "/home/runner/workspace/hardware/ret.py:34" *)
  wire \mload_direct$686 ;
  (* src = "/home/runner/workspace/hardware/load.py:21" *)
  wire \mload_direct$693 ;
  (* src = "/home/runner/workspace/hardware/call.py:35" *)
  wire [31:0] mload_direct_gt;
  (* src = "/home/runner/workspace/hardware/ret.py:35" *)
  wire [31:0] \mload_direct_gt$687 ;
  (* src = "/home/runner/workspace/hardware/load.py:22" *)
  wire [31:0] \mload_direct_gt$694 ;
  (* src = "/home/runner/workspace/hardware/call.py:38" *)
  wire mload_done;
  (* src = "/home/runner/workspace/hardware/ret.py:38" *)
  wire \mload_done$702 ;
  (* src = "/home/runner/workspace/hardware/load.py:26" *)
  wire \mload_done$706 ;
  (* src = "/home/runner/workspace/hardware/call.py:39" *)
  wire mload_fault;
  (* src = "/home/runner/workspace/hardware/ret.py:39" *)
  wire \mload_fault$703 ;
  (* src = "/home/runner/workspace/hardware/load.py:27" *)
  wire \mload_fault$707 ;
  (* src = "/home/runner/workspace/hardware/call.py:40" *)
  wire [4:0] mload_fault_type;
  (* src = "/home/runner/workspace/hardware/ret.py:40" *)
  wire [4:0] \mload_fault_type$704 ;
  (* src = "/home/runner/workspace/hardware/load.py:28" *)
  wire [4:0] \mload_fault_type$708 ;
  (* src = "/home/runner/workspace/hardware/call.py:33" *)
  wire [15:0] mload_index;
  (* src = "/home/runner/workspace/hardware/ret.py:33" *)
  wire [15:0] \mload_index$685 ;
  (* src = "/home/runner/workspace/hardware/load.py:20" *)
  wire [15:0] \mload_index$692 ;
  (* src = "/home/runner/workspace/hardware/call.py:36" *)
  wire mload_m_elevated;
  (* src = "/home/runner/workspace/hardware/ret.py:36" *)
  wire \mload_m_elevated$688 ;
  (* src = "/home/runner/workspace/hardware/load.py:23" *)
  wire \mload_m_elevated$695 ;
  (* src = "/home/runner/workspace/hardware/call.py:30" *)
  wire mload_start;
  (* src = "/home/runner/workspace/hardware/ret.py:30" *)
  wire \mload_start$682 ;
  (* src = "/home/runner/workspace/hardware/load.py:17" *)
  wire \mload_start$689 ;
  (* src = "/home/runner/workspace/hardware/core.py:318" *)
  reg mwin_busy;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  reg [95:0] mwin_cr_wr_data;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire [31:0] \mwin_cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire \mwin_cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire \mwin_cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire [8:0] \mwin_cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire [1:0] \mwin_cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire [2:0] \mwin_cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire [15:0] \mwin_cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire [31:0] \mwin_cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/core.py:320" *)
  wire [31:0] \mwin_cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/core.py:319" *)
  reg mwin_cr_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:2049" *)
  wire [8:0] mwin_dr11_gt_seq;
  (* src = "/home/runner/workspace/hardware/core.py:2030" *)
  reg [31:0] mwin_dr11_lat = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:2038" *)
  wire mwin_dr11_valid;
  (* src = "/home/runner/workspace/hardware/core.py:2031" *)
  reg [31:0] mwin_dr12_lat = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:2050" *)
  wire [8:0] mwin_dr13_gt_seq;
  (* src = "/home/runner/workspace/hardware/core.py:2032" *)
  reg [31:0] mwin_dr13_lat = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:2033" *)
  reg [31:0] mwin_dr14_lat = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:2034" *)
  reg [31:0] mwin_dr15_lat = 32'd0;
  (* src = "/home/runner/workspace/hardware/core.py:323" *)
  reg mwin_fault_valid;
  (* src = "/home/runner/workspace/hardware/core.py:2070" *)
  wire [31:0] mwin_fnv_mul;
  (* src = "/home/runner/workspace/hardware/core.py:2069" *)
  wire [31:0] mwin_fnv_xor;
  (* src = "/home/runner/workspace/hardware/core.py:2051" *)
  wire mwin_gtseq_ok;
  (* src = "/home/runner/workspace/hardware/core.py:2042" *)
  wire [31:0] mwin_integrity_computed;
  (* src = "/home/runner/workspace/hardware/core.py:2044" *)
  wire mwin_integrity_ok;
  (* src = "/home/runner/workspace/hardware/core.py:322" *)
  wire mwin_m_clear_en;
  (* src = "/home/runner/workspace/hardware/core.py:321" *)
  wire mwin_m_set_en;
  (* src = "/home/runner/workspace/hardware/core.py:2063" *)
  wire [31:0] mwin_seal_computed;
  (* src = "/home/runner/workspace/hardware/core.py:2064" *)
  wire [24:0] mwin_seal_masked;
  (* src = "/home/runner/workspace/hardware/core.py:2065" *)
  wire mwin_seal_ok;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [1:0] mwin_state = 2'h0;
  (* src = "/home/runner/workspace/hardware/core.py:2023" *)
  wire mwin_trigger;
  (* src = "/home/runner/workspace/hardware/core.py:369" *)
  wire nested_lambda_fault;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/core.py:99" *)
  wire [31:0] nia;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/change.py:47" *)
  wire [31:0] \nia$453 ;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/core.py:226" *)
  wire [31:0] nia_reg;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:20" *)
  wire nia_set;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:374" *)
  wire \nia_set$763 ;
  (* src = "/home/runner/workspace/hardware/ret.py:27" *)
  wire \nia_set$764 ;
  (* src = "/home/runner/workspace/hardware/call.py:42" *)
  wire \nia_set$765 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:41" *)
  wire \nia_set$766 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:52" *)
  wire \nia_set$767 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:21" *)
  wire [31:0] nia_value;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:375" *)
  wire [31:0] \nia_value$770 ;
  (* src = "/home/runner/workspace/hardware/ret.py:28" *)
  wire [31:0] \nia_value$771 ;
  (* src = "/home/runner/workspace/hardware/call.py:43" *)
  wire [31:0] \nia_value$772 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:42" *)
  wire [31:0] \nia_value$773 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:53" *)
  wire [31:0] \nia_value$774 ;
  (* src = "/home/runner/workspace/hardware/core.py:64" *)
  output [31:0] ns_addr;
  reg [31:0] ns_addr;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:16" *)
  wire [31:0] \ns_addr$754 ;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:23" *)
  wire [15:0] ns_end_index;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:18" *)
  wire [95:0] ns_rd_data;
  (* src = "/home/runner/workspace/hardware/core.py:66" *)
  wire [95:0] \ns_rd_data$79 ;
  (* src = "/home/runner/workspace/hardware/core.py:65" *)
  output ns_rd_en;
  reg ns_rd_en;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:17" *)
  wire \ns_rd_en$755 ;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:22" *)
  wire [15:0] ns_start_index;
  (* src = "/home/runner/workspace/hardware/core.py:67" *)
  output [95:0] ns_wr_data;
  reg [95:0] ns_wr_data;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:19" *)
  wire [95:0] \ns_wr_data$756 ;
  (* src = "/home/runner/workspace/hardware/core.py:68" *)
  output ns_wr_en;
  reg ns_wr_en;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:20" *)
  wire \ns_wr_en$757 ;
  (* src = "/home/runner/workspace/hardware/outform.py:80" *)
  wire outform_busy;
  (* src = "/home/runner/workspace/hardware/core.py:108" *)
  wire \outform_busy$533 ;
  (* src = "/home/runner/workspace/hardware/mload.py:79" *)
  wire [31:0] outform_clist_addr;
  (* src = "/home/runner/workspace/hardware/core.py:114" *)
  wire [31:0] outform_clist_addr_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:47" *)
  wire [31:0] outform_clist_addr_out;
  (* src = "/home/runner/workspace/hardware/outform.py:81" *)
  wire outform_done;
  (* src = "/home/runner/workspace/hardware/mload.py:81" *)
  wire outform_done_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:49" *)
  wire \outform_done_in$544 ;
  (* src = "/home/runner/workspace/hardware/outform.py:82" *)
  wire outform_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:82" *)
  wire outform_fault_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:50" *)
  wire \outform_fault_in$546 ;
  (* src = "/home/runner/workspace/hardware/outform.py:83" *)
  wire [4:0] outform_fault_type;
  (* src = "/home/runner/workspace/hardware/mload.py:83" *)
  wire [4:0] outform_fault_type_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:51" *)
  wire [4:0] \outform_fault_type_in$547 ;
  (* src = "/home/runner/workspace/hardware/core.py:147" *)
  wire outform_fsm_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:77" *)
  wire [31:0] outform_gt_raw;
  (* src = "/home/runner/workspace/hardware/core.py:115" *)
  wire [31:0] outform_gt_raw_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:45" *)
  wire [31:0] outform_gt_raw_out;
  (* src = "/home/runner/workspace/hardware/core.py:1470" *)
  reg outform_mode2_active = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:107" *)
  wire [31:0] outform_result_gt;
  (* src = "/home/runner/workspace/hardware/core.py:106" *)
  wire [7:0] outform_rx_data;
  (* src = "/home/runner/workspace/hardware/core.py:105" *)
  wire outform_rx_valid;
  (* src = "/home/runner/workspace/hardware/mload.py:78" *)
  wire [15:0] outform_slot_id;
  (* src = "/home/runner/workspace/hardware/core.py:113" *)
  wire [15:0] outform_slot_id_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:46" *)
  wire [15:0] outform_slot_id_out;
  (* src = "/home/runner/workspace/hardware/outform.py:79" *)
  wire outform_start;
  (* src = "/home/runner/workspace/hardware/core.py:112" *)
  wire outform_start_in;
  (* src = "/home/runner/workspace/hardware/mload.py:76" *)
  wire outform_start_out;
  (* src = "/home/runner/workspace/hardware/church_outform.py:44" *)
  wire \outform_start_out$513 ;
  (* src = "/home/runner/workspace/hardware/core.py:104" *)
  wire outform_tx_ack;
  (* src = "/home/runner/workspace/hardware/core.py:103" *)
  wire [7:0] outform_tx_data;
  (* src = "/home/runner/workspace/hardware/core.py:102" *)
  wire outform_tx_valid;
  (* src = "/home/runner/workspace/hardware/core.py:415" *)
  wire [31:0] perm_gt_sig;
  (* src = "/home/runner/workspace/hardware/core.py:415" *)
  wire \perm_gt_sig.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:415" *)
  wire \perm_gt_sig.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:415" *)
  wire [8:0] \perm_gt_sig.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:415" *)
  wire [1:0] \perm_gt_sig.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:415" *)
  wire [2:0] \perm_gt_sig.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:415" *)
  wire [15:0] \perm_gt_sig.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:386" *)
  wire [15:0] pet_name_rd_addr;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:57" *)
  wire [15:0] \pet_name_rd_addr$489 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:58" *)
  wire pet_name_rd_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:387" *)
  wire \pet_name_rd_data$492 ;
  input [31:0] \port$4577$0 ;
  wire [31:0] \port$4577$0 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:13" *)
  wire [3:0] preset;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:71" *)
  wire [15:0] rd_addr;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:72" *)
  wire rd_data;
  (* src = "/home/runner/workspace/hardware/ret.py:19" *)
  wire reboot_request;
  (* src = "/home/runner/workspace/hardware/core.py:418" *)
  reg [5:0] required_perms;
  (* src = "/home/runner/workspace/hardware/perm_check.py:35" *)
  wire [5:0] \required_perms$69 ;
  (* src = "/home/runner/workspace/hardware/outform.py:111" *)
  wire [31:0] result_gt;
  (* src = "/home/runner/workspace/hardware/church_outform.py:52" *)
  wire [31:0] result_gt_in;
  (* src = "/home/runner/workspace/hardware/core.py:382" *)
  wire ret_start_sig;
  (* src = "/home/runner/workspace/hardware/ret.py:13" *)
  wire return_start;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap0_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap0_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap0_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap0_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap0_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap0_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap0_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap0_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap10_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap10_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap10_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap10_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap10_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap10_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap10_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap10_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap11_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap11_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap11_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap11_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap11_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap11_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap11_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap11_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap12_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap12_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap12_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap12_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap12_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap12_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap12_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap12_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap13_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap13_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap13_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap13_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap13_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap13_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap13_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap13_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap14_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap14_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap14_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap14_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap14_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap14_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap14_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap14_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap15_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap15_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap15_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap15_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap15_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap15_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap15_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap15_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap1_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap1_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap1_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap1_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap1_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap1_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap1_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap1_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap2_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap2_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap2_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap2_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap2_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap2_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap2_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap2_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap3_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap3_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap3_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap3_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap3_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap3_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap3_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap3_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap4_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap4_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap4_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap4_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap4_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap4_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap4_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap4_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap5_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap5_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap5_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap5_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap5_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap5_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap5_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap5_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap6_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap6_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap6_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap6_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap6_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap6_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap6_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap6_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  wire rt_cap7_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [31:0] rt_cap7_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap7_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap7_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap7_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap7_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap7_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap7_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap8_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap8_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap8_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap8_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap8_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap8_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap8_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap8_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/core.py:908" *)
  reg rt_cap9_wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  reg [31:0] rt_cap9_wr_gt;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap9_wr_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire \rt_cap9_wr_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [8:0] \rt_cap9_wr_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [1:0] \rt_cap9_wr_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [2:0] \rt_cap9_wr_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:909" *)
  wire [15:0] \rt_cap9_wr_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/outform.py:92" *)
  wire [7:0] rx_data;
  (* src = "/home/runner/workspace/hardware/outform.py:91" *)
  wire rx_valid;
  (* src = "/home/runner/workspace/hardware/save.py:15" *)
  wire save_busy;
  (* src = "/home/runner/workspace/hardware/save.py:17" *)
  wire save_fault;
  (* src = "/home/runner/workspace/hardware/save.py:11" *)
  wire save_start;
  (* src = "/home/runner/workspace/hardware/core.py:1052" *)
  wire save_start_sig;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:22" *)
  wire [31:0] saved_nia;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:376" *)
  wire [31:0] \saved_nia$509 ;
  (* src = "/home/runner/workspace/hardware/core.py:1897" *)
  reg [14:0] scan_end_c_ni;
  (* src = "/home/runner/workspace/hardware/core.py:1179" *)
  wire [4:0] shift_amt;
  (* src = "/home/runner/workspace/hardware/core.py:307" *)
  reg shl_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:1204" *)
  wire shl_c_bit;
  (* src = "/home/runner/workspace/hardware/core.py:1206" *)
  wire [5:0] shl_c_shift;
  (* src = "/home/runner/workspace/hardware/core.py:520" *)
  wire [3:0] shl_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:520" *)
  wire \shl_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:520" *)
  wire \shl_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:520" *)
  wire \shl_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:520" *)
  wire \shl_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/core.py:513" *)
  wire [31:0] shl_result;
  (* src = "/home/runner/workspace/hardware/core.py:506" *)
  wire shl_start_sig;
  (* src = "/home/runner/workspace/hardware/core.py:308" *)
  reg shr_busy_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/core.py:1203" *)
  wire shr_c_bit;
  (* src = "/home/runner/workspace/hardware/core.py:1205" *)
  wire [4:0] shr_c_shift;
  (* src = "/home/runner/workspace/hardware/core.py:521" *)
  wire [3:0] shr_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:521" *)
  wire \shr_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:521" *)
  wire \shr_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:521" *)
  wire \shr_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:521" *)
  wire \shr_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/core.py:514" *)
  wire [31:0] shr_result;
  (* src = "/home/runner/workspace/hardware/core.py:1190" *)
  wire [63:0] shr_src_sx;
  (* src = "/home/runner/workspace/hardware/core.py:507" *)
  wire shr_start_sig;
  (* src = "/home/runner/workspace/hardware/outform.py:86" *)
  wire [15:0] slot_id;
  (* src = "/home/runner/workspace/hardware/church_outform.py:35" *)
  wire [3:0] src_cr;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [95:0] src_cr_data;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [31:0] \src_cr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire \src_cr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire \src_cr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [8:0] \src_cr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [1:0] \src_cr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [2:0] \src_cr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [15:0] \src_cr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [31:0] \src_cr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [31:0] \src_cr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:18" *)
  wire stack_has_frame;
  (* src = "/home/runner/workspace/hardware/dread.py:37" *)
  wire start;
  (* src = "/home/runner/workspace/hardware/dwrite.py:36" *)
  wire \start$396 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:14" *)
  wire \start$466 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:349" *)
  wire \start$479 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:30" *)
  wire \start$503 ;
  (* src = "/home/runner/workspace/hardware/mload.py:44" *)
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  reg [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  reg [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  reg sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  reg [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:47" *)
  wire [4:0] sub_fault_type;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  reg [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  reg sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  reg sub_start;
  (* src = "/home/runner/workspace/hardware/switch.py:15" *)
  wire switch_busy;
  (* src = "/home/runner/workspace/hardware/core.py:912" *)
  wire switch_change_active;
  (* src = "/home/runner/workspace/hardware/switch.py:17" *)
  wire switch_fault;
  (* src = "/home/runner/workspace/hardware/core.py:918" *)
  wire [31:0] switch_src_gt;
  (* src = "/home/runner/workspace/hardware/core.py:918" *)
  wire \switch_src_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:918" *)
  wire \switch_src_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:918" *)
  wire [8:0] \switch_src_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:918" *)
  wire [1:0] \switch_src_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:918" *)
  wire [2:0] \switch_src_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:918" *)
  wire [15:0] \switch_src_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:11" *)
  wire switch_start;
  (* src = "/home/runner/workspace/hardware/core.py:1358" *)
  wire switch_start_sig;
  (* src = "/home/runner/workspace/hardware/decoder.py:61" *)
  wire [3:0] switch_target;
  (* src = "/home/runner/workspace/hardware/switch.py:13" *)
  wire [2:0] target;
  (* src = "/home/runner/workspace/hardware/core.py:857" *)
  reg [31:0] thrd_gt;
  (* src = "/home/runner/workspace/hardware/core.py:857" *)
  wire \thrd_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/core.py:857" *)
  wire \thrd_gt.dom ;
  (* src = "/home/runner/workspace/hardware/core.py:857" *)
  wire [8:0] \thrd_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/core.py:857" *)
  wire [1:0] \thrd_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/core.py:857" *)
  wire [2:0] \thrd_gt.perm ;
  (* src = "/home/runner/workspace/hardware/core.py:857" *)
  wire [15:0] \thrd_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:71" *)
  wire [31:0] thread_base;
  (* src = "/home/runner/workspace/hardware/call.py:80" *)
  wire [31:0] thread_hdr;
  (* src = "/home/runner/workspace/hardware/change.py:54" *)
  wire [31:0] thread_hdr_out;
  (* src = "/home/runner/workspace/hardware/core.py:142" *)
  wire timer_alarm;
  (* src = "/home/runner/workspace/hardware/tperm.py:20" *)
  wire tperm_busy;
  (* src = "/home/runner/workspace/hardware/tperm.py:21" *)
  wire tperm_complete;
  (* src = "/home/runner/workspace/hardware/tperm.py:22" *)
  wire tperm_fault;
  (* src = "/home/runner/workspace/hardware/core.py:594" *)
  reg [3:0] tperm_flags_sig;
  (* src = "/home/runner/workspace/hardware/core.py:594" *)
  wire \tperm_flags_sig.C ;
  (* src = "/home/runner/workspace/hardware/core.py:594" *)
  wire \tperm_flags_sig.N ;
  (* src = "/home/runner/workspace/hardware/core.py:594" *)
  wire \tperm_flags_sig.V ;
  (* src = "/home/runner/workspace/hardware/core.py:594" *)
  wire \tperm_flags_sig.Z ;
  (* src = "/home/runner/workspace/hardware/decoder.py:55" *)
  wire [3:0] tperm_preset;
  (* src = "/home/runner/workspace/hardware/tperm.py:10" *)
  wire tperm_start;
  (* src = "/home/runner/workspace/hardware/core.py:380" *)
  wire tperm_start_sig;
  (* src = "/home/runner/workspace/hardware/tperm.py:31" *)
  wire tperm_z_result;
  (* src = "/home/runner/workspace/hardware/outform.py:90" *)
  wire tx_ack;
  (* src = "/home/runner/workspace/hardware/outform.py:89" *)
  wire [7:0] tx_data;
  (* src = "/home/runner/workspace/hardware/outform.py:88" *)
  wire tx_valid;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:28" *)
  wire valid_key_access;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] \w0_rot$570 ;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] \w0_rot$602 ;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] \w1_masked$569 ;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] \w1_masked$600 ;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] \w1_rot$572 ;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] \w1_rot$604 ;
  (* src = "/home/runner/workspace/hardware/core.py:1788" *)
  reg [31:0] watermark_reg_noniot = 32'd256;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:75" *)
  reg [5:0] wr_addr;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:76" *)
  reg wr_data;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:74" *)
  reg wr_en;
  (* src = "/home/runner/workspace/hardware/core.py:1390" *)
  wire xloadlambda_start_sig;
  (* src = "/home/runner/workspace/hardware/core.py:243" *)
  always @(posedge clk)
    lambda_pc <= \$384 ;
  (* src = "/home/runner/workspace/hardware/core.py:304" *)
  always @(posedge clk)
    iadd_busy_reg <= \$340 ;
  (* src = "/home/runner/workspace/hardware/core.py:305" *)
  always @(posedge clk)
    isub_busy_reg <= \$342 ;
  (* src = "/home/runner/workspace/hardware/core.py:307" *)
  always @(posedge clk)
    shl_busy_reg <= \$344 ;
  (* src = "/home/runner/workspace/hardware/core.py:308" *)
  always @(posedge clk)
    shr_busy_reg <= \$346 ;
  (* src = "/home/runner/workspace/hardware/core.py:309" *)
  always @(posedge clk)
    bfext_busy_reg <= \$348 ;
  (* src = "/home/runner/workspace/hardware/core.py:310" *)
  always @(posedge clk)
    bfins_busy_reg <= \$350 ;
  (* src = "/home/runner/workspace/hardware/core.py:311" *)
  always @(posedge clk)
    mcmp_busy_reg <= \$352 ;
  (* src = "/home/runner/workspace/hardware/core.py:306" *)
  always @(posedge clk)
    branch_busy_reg <= \$354 ;
  (* src = "/home/runner/workspace/hardware/core.py:1470" *)
  always @(posedge clk)
    outform_mode2_active <= \$385 ;
  (* src = "/home/runner/workspace/hardware/core.py:330" *)
  always @(posedge clk)
    mint_slot_id_reg <= \$386 ;
  (* src = "/home/runner/workspace/hardware/core.py:331" *)
  always @(posedge clk)
    mint_clist_addr_reg <= \$387 ;
  (* src = "/home/runner/workspace/hardware/core.py:1788" *)
  always @(posedge clk)
    watermark_reg_noniot <= \$388 ;
  (* src = "/home/runner/workspace/hardware/core.py:1822" *)
  always @(posedge clk)
    mint_base_reg_ni <= \$389 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    mint_noniot_state <= \$390 ;
  (* src = "/home/runner/workspace/hardware/core.py:1828" *)
  always @(posedge clk)
    mint_hdr_reg_ni <= \$391 ;
  (* src = "/home/runner/workspace/hardware/core.py:332" *)
  always @(posedge clk)
    mint_lump_size_reg <= \$392 ;
  (* src = "/home/runner/workspace/hardware/core.py:1823" *)
  always @(posedge clk)
    mint_cw_reg_ni <= \$393 ;
  (* src = "/home/runner/workspace/hardware/core.py:1824" *)
  always @(posedge clk)
    mint_cc_reg_ni <= \$394 ;
  (* src = "/home/runner/workspace/hardware/core.py:1825" *)
  always @(posedge clk)
    mint_scan_idx_reg_ni <= \$395 ;
  (* src = "/home/runner/workspace/hardware/core.py:1826" *)
  always @(posedge clk)
    mint_copy_idx_reg_ni <= \$396 ;
  (* src = "/home/runner/workspace/hardware/core.py:1831" *)
  always @(posedge clk)
    mint_cc_base_reg_ni <= \$397 ;
  (* src = "/home/runner/workspace/hardware/core.py:1827" *)
  always @(posedge clk)
    mint_copy_data_reg_ni <= \$398 ;
  (* src = "/home/runner/workspace/hardware/core.py:2030" *)
  always @(posedge clk)
    mwin_dr11_lat <= \$399 ;
  (* src = "/home/runner/workspace/hardware/core.py:2031" *)
  always @(posedge clk)
    mwin_dr12_lat <= \$400 ;
  (* src = "/home/runner/workspace/hardware/core.py:2032" *)
  always @(posedge clk)
    mwin_dr13_lat <= \$401 ;
  (* src = "/home/runner/workspace/hardware/core.py:2033" *)
  always @(posedge clk)
    mwin_dr14_lat <= \$402 ;
  (* src = "/home/runner/workspace/hardware/core.py:2034" *)
  always @(posedge clk)
    mwin_dr15_lat <= \$403 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    mwin_state <= \$404 ;
  (* src = "/home/runner/workspace/hardware/core.py:2224" *)
  always @(posedge clk)
    fault_instr <= \$405 ;
  (* src = "/home/runner/workspace/hardware/core.py:2225" *)
  always @(posedge clk)
    fault_stage <= \$406 ;
  assign boot_complete = boot_state == (* src = "/home/runner/workspace/hardware/core.py:250" *) 3'h6;
  assign clear_all = boot_state == (* src = "/home/runner/workspace/hardware/core.py:251" *) 1'h1;
  assign instr_valid = imem_valid & (* src = "/home/runner/workspace/hardware/core.py:273" *) boot_complete;
  assign \$1  = boot_complete & (* src = "/home/runner/workspace/hardware/core.py:300" *) exec_enable;
  assign \$2  = ~ (* src = "/home/runner/workspace/hardware/core.py:300" *) fetch_bounds_fault;
  assign cond_exec_enable = \$1  & (* src = "/home/runner/workspace/hardware/core.py:300" *) \$2 ;
  assign \$3  = tperm_busy | (* src = "/home/runner/workspace/hardware/core.py:341" *) call_busy;
  assign \$4  = \$3  | (* src = "/home/runner/workspace/hardware/core.py:341" *) busy;
  assign \$5  = \$4  | (* src = "/home/runner/workspace/hardware/core.py:341" *) save_busy;
  assign \$6  = \$5  | (* src = "/home/runner/workspace/hardware/core.py:341" *) load_busy;
  assign \$7  = \$6  | (* src = "/home/runner/workspace/hardware/core.py:341" *) \busy$19 ;
  assign \$8  = \$7  | (* src = "/home/runner/workspace/hardware/core.py:341" *) \busy$20 ;
  assign \$9  = \$8  | (* src = "/home/runner/workspace/hardware/core.py:341" *) iadd_busy_reg;
  assign \$10  = \$9  | (* src = "/home/runner/workspace/hardware/core.py:341" *) isub_busy_reg;
  assign \$11  = \$10  | (* src = "/home/runner/workspace/hardware/core.py:341" *) branch_busy_reg;
  assign \$12  = \$11  | (* src = "/home/runner/workspace/hardware/core.py:341" *) shl_busy_reg;
  assign \$13  = \$12  | (* src = "/home/runner/workspace/hardware/core.py:341" *) shr_busy_reg;
  assign \$14  = \$13  | (* src = "/home/runner/workspace/hardware/core.py:341" *) bfext_busy_reg;
  assign \$15  = \$14  | (* src = "/home/runner/workspace/hardware/core.py:341" *) bfins_busy_reg;
  assign \$16  = \$15  | (* src = "/home/runner/workspace/hardware/core.py:341" *) mcmp_busy_reg;
  assign \$17  = \$16  | (* src = "/home/runner/workspace/hardware/core.py:341" *) cload_busy;
  assign \$18  = \$17  | (* src = "/home/runner/workspace/hardware/core.py:341" *) cload_pending;
  assign \$19  = \$18  | (* src = "/home/runner/workspace/hardware/core.py:341" *) fence_pending_reg;
  assign \$20  = \$19  | (* src = "/home/runner/workspace/hardware/core.py:341" *) outform_busy;
  assign \$21  = \$20  | (* src = "/home/runner/workspace/hardware/core.py:341" *) mint_busy;
  assign \$22  = \$21  | (* src = "/home/runner/workspace/hardware/core.py:341" *) mwin_busy;
  assign \$23  = \$22  | (* src = "/home/runner/workspace/hardware/core.py:341" *) \busy$35 ;
  assign \$24  = lambda_busy | (* src = "/home/runner/workspace/hardware/core.py:355" *) gc_busy;
  assign \$25  = \$24  | (* src = "/home/runner/workspace/hardware/core.py:355" *) change_busy;
  assign \$26  = \$25  | (* src = "/home/runner/workspace/hardware/core.py:355" *) switch_busy;
  assign \$27  = \$26  | (* src = "/home/runner/workspace/hardware/core.py:355" *) \busy$40 ;
  assign \$28  = \$27  | (* src = "/home/runner/workspace/hardware/core.py:355" *) \busy$41 ;
  assign \$29  = \$28  | (* src = "/home/runner/workspace/hardware/core.py:355" *) \busy$42 ;
  assign any_unit_busy = \$23  | (* src = "/home/runner/workspace/hardware/core.py:354" *) \$29 ;
  assign \$30  = boot_complete & (* src = "/home/runner/workspace/hardware/core.py:365" *) imem_valid;
  assign \$31  = ! (* src = "/home/runner/workspace/hardware/core.py:365" *) instruction;
  assign \$32  = \$30  & (* src = "/home/runner/workspace/hardware/core.py:365" *) \$31 ;
  assign \$33  = ~ (* src = "/home/runner/workspace/hardware/core.py:365" *) any_unit_busy;
  assign halt_valid = \$32  & (* src = "/home/runner/workspace/hardware/core.py:365" *) \$33 ;
  assign \$34  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:372" *) is_church_op;
  assign \$35  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:372" *) 3'h7;
  assign \$36  = \$34  & (* src = "/home/runner/workspace/hardware/core.py:372" *) \$35 ;
  assign \$37  = ~ (* src = "/home/runner/workspace/hardware/core.py:372" *) any_unit_busy;
  assign \$38  = \$36  & (* src = "/home/runner/workspace/hardware/core.py:372" *) \$37 ;
  assign \$39  = \$38  & (* src = "/home/runner/workspace/hardware/core.py:372" *) lambda_active_reg;
  assign \$40  = instruction[22:19] != (* src = "/home/runner/workspace/hardware/core.py:373" *) 3'h6;
  assign nested_lambda_fault = \$39  & (* src = "/home/runner/workspace/hardware/core.py:372" *) \$40 ;
  assign \$41  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:376" *) is_church_op;
  assign \$42  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:376" *) 3'h7;
  assign \$43  = \$41  & (* src = "/home/runner/workspace/hardware/core.py:376" *) \$42 ;
  assign \$44  = ~ (* src = "/home/runner/workspace/hardware/core.py:376" *) any_unit_busy;
  assign \$45  = \$43  & (* src = "/home/runner/workspace/hardware/core.py:376" *) \$44 ;
  assign \$46  = instruction[22:19] != (* src = "/home/runner/workspace/hardware/core.py:377" *) 3'h6;
  assign \$47  = lambda_active_reg & (* src = "/home/runner/workspace/hardware/core.py:377" *) \$46 ;
  assign \$48  = ~ (* src = "/home/runner/workspace/hardware/core.py:377" *) \$47 ;
  assign lambda_start_sig = \$45  & (* src = "/home/runner/workspace/hardware/core.py:376" *) \$48 ;
  assign \$49  = lambda_start_sig | (* src = "/home/runner/workspace/hardware/core.py:395" *) lambda_busy;
  assign \$50  = \busy$20  ? (* src = "/home/runner/workspace/hardware/core.py:388" *) \cr_rd_addr$53  : instruction[18:15];
  assign \$51  = \busy$19  ? (* src = "/home/runner/workspace/hardware/core.py:387" *) \cr_rd_addr$54  : \$50 ;
  assign \$52  = \busy$41  ? (* src = "/home/runner/workspace/hardware/core.py:386" *) \cr_rd_addr$55  : \$51 ;
  assign \$53  = \busy$40  ? (* src = "/home/runner/workspace/hardware/core.py:385" *) \cr_rd_addr$56  : \$52 ;
  assign \$54  = switch_busy ? (* src = "/home/runner/workspace/hardware/core.py:391" *) \cr_rd_addr$57  : \$53 ;
  assign \$55  = change_busy ? (* src = "/home/runner/workspace/hardware/core.py:390" *) \cr_rd_addr$58  : \$54 ;
  assign \$56  = save_busy ? (* src = "/home/runner/workspace/hardware/core.py:399" *) \cr_rd_addr$59  : \$55 ;
  assign \$57  = busy ? (* src = "/home/runner/workspace/hardware/core.py:398" *) \cr_rd_addr$60  : \$56 ;
  assign \$58  = call_busy ? (* src = "/home/runner/workspace/hardware/core.py:397" *) \cr_rd_addr$61  : \$57 ;
  assign \$59  = tperm_busy ? (* src = "/home/runner/workspace/hardware/core.py:396" *) \cr_rd_addr$62  : \$58 ;
  assign \$60  = \$49  ? (* src = "/home/runner/workspace/hardware/core.py:395" *) \cr_rd_addr$63  : \$59 ;
  assign cr_rd_addr = sub_busy ? (* src = "/home/runner/workspace/hardware/core.py:394" *) \cr_rd_addr$64  : \$60 ;
  assign \$61  = instruction[18:15] == (* src = "/home/runner/workspace/hardware/core.py:421" *) 3'h6;
  assign \$62  = \$61  ? (* src = "/home/runner/workspace/hardware/core.py:421" *) 4'h0 : 4'h8;
  assign \$63  = cr_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/core.py:429" *) 2'h3;
  assign \$64  = cr_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/core.py:430" *) 2'h2;
  assign \$65  = \$63  | (* src = "/home/runner/workspace/hardware/core.py:429" *) \$64 ;
  assign check_valid = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:454" *) is_church_op;
  assign \$66  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:456" *) is_church_op;
  assign \$67  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:456" *) 3'h6;
  assign check_domain_purity = \$66  & (* src = "/home/runner/workspace/hardware/core.py:456" *) \$67 ;
  assign \$68  = ~ (* src = "/home/runner/workspace/hardware/core.py:598" *) tperm_z_result;
  assign \$69  = \busy$41  ? (* src = "/home/runner/workspace/hardware/core.py:636" *) \cr_wr_addr$138  : 4'h0;
  assign \$70  = \busy$40  ? (* src = "/home/runner/workspace/hardware/core.py:635" *) \cr_wr_addr$139  : \$69 ;
  assign \$71  = switch_busy ? (* src = "/home/runner/workspace/hardware/core.py:642" *) \cr_wr_addr$140  : \$70 ;
  assign \$72  = change_busy ? (* src = "/home/runner/workspace/hardware/core.py:641" *) \cr_wr_addr$141  : \$71 ;
  assign \$73  = \cr_wr_en$137  ? (* src = "/home/runner/workspace/hardware/core.py:640" *) \cr_wr_addr$142  : \$72 ;
  assign \$74  = \cr_wr_en$136  ? (* src = "/home/runner/workspace/hardware/core.py:656" *) \cr_wr_addr$143  : \$73 ;
  assign \$77  = \cr_wr_en$133  ? (* src = "/home/runner/workspace/hardware/core.py:669" *) \cr_wr_addr$146  : \$76 ;
  assign \$78  = \cr_wr_en$132  ? (* src = "/home/runner/workspace/hardware/core.py:668" *) \cr_wr_addr$147  : \$77 ;
  assign \$79  = cr_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:667" *) \cr_wr_addr$148  : \$78 ;
  assign \$80  = boot_cap_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:666" *) boot_cap_wr_addr : \$79 ;
  assign cr_wr_addr = mwin_cr_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:665" *) 4'hf : \$80 ;
  assign \$81  = \busy$41  ? (* src = "/home/runner/workspace/hardware/core.py:638" *) \cr_wr_data$151  : 96'h000000000000000000000000;
  assign \$82  = \busy$40  ? (* src = "/home/runner/workspace/hardware/core.py:637" *) \cr_wr_data$152  : \$81 ;
  assign \$83  = switch_busy ? (* src = "/home/runner/workspace/hardware/core.py:646" *) \cr_wr_data$153  : \$82 ;
  assign \$84  = change_busy ? (* src = "/home/runner/workspace/hardware/core.py:645" *) \cr_wr_data$154  : \$83 ;
  assign \$85  = \cr_wr_en$137  ? (* src = "/home/runner/workspace/hardware/core.py:644" *) \cr_wr_data$155  : \$84 ;
  assign \$86  = \cr_wr_en$136  ? (* src = "/home/runner/workspace/hardware/core.py:657" *) \cr_wr_data$156  : \$85 ;
  assign \$89  = \cr_wr_en$133  ? (* src = "/home/runner/workspace/hardware/core.py:678" *) \cr_wr_data$159  : \$88 ;
  assign \$90  = \cr_wr_en$132  ? (* src = "/home/runner/workspace/hardware/core.py:677" *) \cr_wr_data$160  : \$89 ;
  assign \$91  = cr_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:676" *) \cr_wr_data$161  : \$90 ;
  assign \$92  = boot_cap_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:675" *) boot_cap_wr_data : \$91 ;
  assign cr_wr_data = mwin_cr_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:674" *) mwin_cr_wr_data : \$92 ;
  assign \$93  = mwin_cr_wr_en | (* src = "/home/runner/workspace/hardware/core.py:683" *) boot_cap_wr_en;
  assign \$94  = \$93  | (* src = "/home/runner/workspace/hardware/core.py:683" *) cr_wr_en;
  assign \$95  = \$94  | (* src = "/home/runner/workspace/hardware/core.py:683" *) \cr_wr_en$132 ;
  assign \$96  = \$95  | (* src = "/home/runner/workspace/hardware/core.py:683" *) \cr_wr_en$133 ;
  assign \$98  = \cr_wr_en$165  | (* src = "/home/runner/workspace/hardware/core.py:639" *) \cr_wr_en$166 ;
  assign \$99  = \$98  | (* src = "/home/runner/workspace/hardware/core.py:648" *) \cr_wr_en$137 ;
  assign \$100  = \$99  | (* src = "/home/runner/workspace/hardware/core.py:648" *) \cr_wr_en$167 ;
  assign \$101  = \$100  | (* src = "/home/runner/workspace/hardware/core.py:648" *) \cr_wr_en$168 ;
  assign \$102  = \$101  | (* src = "/home/runner/workspace/hardware/core.py:658" *) \cr_wr_en$136 ;
  assign \cr_wr_en$164  = \$97  | (* src = "/home/runner/workspace/hardware/core.py:683" *) \$103 ;
  assign \$104  = { cr15_namespace[56:32], cr15_namespace[63:57] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign m_set_dr11 = mgt_set_trigger ? (* src = "/home/runner/workspace/hardware/core.py:720" *) mgt_gt_word : cr15_namespace[31:0];
  assign m_set_dr12 = mgt_set_trigger ? (* src = "/home/runner/workspace/hardware/core.py:724" *) mgt_ns_location : cr15_namespace[63:32];
  assign m_set_dr13 = mgt_set_trigger ? (* src = "/home/runner/workspace/hardware/core.py:728" *) mgt_ns_authority : cr15_namespace[95:64];
  assign m_set_dr14 = mgt_set_trigger ? (* src = "/home/runner/workspace/hardware/core.py:732" *) mgt_ns_integrity : cr15_m_set_integrity;
  assign m_set_dr15 = mgt_set_trigger ? (* src = "/home/runner/workspace/hardware/core.py:736" *) mgt_ns_seals : 32'd0;
  assign \$105  = boot_complete & (* src = "/home/runner/workspace/hardware/core.py:914" *) cond_exec_enable;
  assign \$106  = \$105  & (* src = "/home/runner/workspace/hardware/core.py:914" *) is_church_op;
  assign \$107  = ~ (* src = "/home/runner/workspace/hardware/core.py:914" *) any_unit_busy;
  assign \$108  = \$106  & (* src = "/home/runner/workspace/hardware/core.py:914" *) \$107 ;
  assign \$109  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:915" *) 3'h5;
  assign \$110  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:915" *) 3'h4;
  assign \$111  = \$109  | (* src = "/home/runner/workspace/hardware/core.py:915" *) \$110 ;
  assign switch_change_active = \$108  & (* src = "/home/runner/workspace/hardware/core.py:914" *) \$111 ;
  assign \$112  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:922" *) 3'h4;
  assign effective_target = \$112  ? (* src = "/home/runner/workspace/hardware/core.py:922" *) 3'h0 : instruction[2:0];
  assign \$113  = ! (* src = "/home/runner/workspace/hardware/core.py:926" *) effective_target;
  assign \$114  = effective_target == (* src = "/home/runner/workspace/hardware/core.py:926" *) 1'h1;
  assign \$115  = effective_target == (* src = "/home/runner/workspace/hardware/core.py:926" *) 2'h2;
  assign \$116  = effective_target == (* src = "/home/runner/workspace/hardware/core.py:926" *) 2'h3;
  assign \$117  = effective_target == (* src = "/home/runner/workspace/hardware/core.py:926" *) 3'h4;
  assign \$118  = effective_target == (* src = "/home/runner/workspace/hardware/core.py:926" *) 3'h5;
  assign \$119  = effective_target == (* src = "/home/runner/workspace/hardware/core.py:926" *) 3'h6;
  assign \$120  = effective_target == (* src = "/home/runner/workspace/hardware/core.py:926" *) 3'h7;
  assign cr8_gt_wr_en = boot_cap8_wr_en | (* src = "/home/runner/workspace/hardware/core.py:931" *) rt_cap8_wr_en;
  assign cr8_gt_wr_data = boot_cap8_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:932" *) boot_cap8_wr_gt : rt_cap8_wr_gt;
  assign cr14_gt_wr_en = boot_cap14_wr_en | (* src = "/home/runner/workspace/hardware/core.py:931" *) rt_cap14_wr_en;
  assign cr14_gt_wr_data = boot_cap14_wr_en ? (* src = "/home/runner/workspace/hardware/core.py:932" *) boot_cap14_wr_gt : rt_cap14_wr_gt;
  assign call_src_is_outform = cr_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/core.py:941" *) 2'h2;
  assign \$121  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:947" *) is_church_op;
  assign \$122  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:947" *) 2'h2;
  assign \$123  = \$121  & (* src = "/home/runner/workspace/hardware/core.py:947" *) \$122 ;
  assign \$124  = ~ (* src = "/home/runner/workspace/hardware/core.py:948" *) any_unit_busy;
  assign \$125  = \$123  & (* src = "/home/runner/workspace/hardware/core.py:947" *) \$124 ;
  assign \$126  = ~ (* src = "/home/runner/workspace/hardware/core.py:948" *) call_src_is_outform;
  assign call_start_sig = \$125  & (* src = "/home/runner/workspace/hardware/core.py:947" *) \$126 ;
  assign \$127  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:954" *) is_church_op;
  assign \$128  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:954" *) 2'h2;
  assign \$129  = \$127  & (* src = "/home/runner/workspace/hardware/core.py:954" *) \$128 ;
  assign \$130  = ~ (* src = "/home/runner/workspace/hardware/core.py:955" *) any_unit_busy;
  assign \$131  = \$129  & (* src = "/home/runner/workspace/hardware/core.py:954" *) \$130 ;
  assign intercept_start = \$131  & (* src = "/home/runner/workspace/hardware/core.py:954" *) call_src_is_outform;
  assign \$132  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:985" *) is_church_op;
  assign \$133  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:985" *) 2'h3;
  assign \$134  = \$132  & (* src = "/home/runner/workspace/hardware/core.py:985" *) \$133 ;
  assign \$135  = ~ (* src = "/home/runner/workspace/hardware/core.py:985" *) any_unit_busy;
  assign ret_start_sig = \$134  & (* src = "/home/runner/workspace/hardware/core.py:985" *) \$135 ;
  assign \$136  = imem_addr + (* src = "/home/runner/workspace/hardware/core.py:1029" *) 3'h4;
  assign \$137  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1036" *) is_church_op;
  assign \$138  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:1036" *) 3'h6;
  assign \$139  = \$137  & (* src = "/home/runner/workspace/hardware/core.py:1036" *) \$138 ;
  assign \$140  = ~ (* src = "/home/runner/workspace/hardware/core.py:1036" *) any_unit_busy;
  assign tperm_start_sig = \$139  & (* src = "/home/runner/workspace/hardware/core.py:1036" *) \$140 ;
  assign \$141  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1054" *) is_church_op;
  assign \$142  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:1054" *) 1'h1;
  assign \$143  = \$141  & (* src = "/home/runner/workspace/hardware/core.py:1054" *) \$142 ;
  assign \$144  = ~ (* src = "/home/runner/workspace/hardware/core.py:1054" *) any_unit_busy;
  assign save_start_sig = \$143  & (* src = "/home/runner/workspace/hardware/core.py:1054" *) \$144 ;
  assign \$145  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1070" *) is_dread_op;
  assign \$146  = ~ (* src = "/home/runner/workspace/hardware/core.py:1070" *) any_unit_busy;
  assign dread_start_sig = \$145  & (* src = "/home/runner/workspace/hardware/core.py:1070" *) \$146 ;
  assign \$147  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1085" *) is_dwrite_op;
  assign \$148  = ~ (* src = "/home/runner/workspace/hardware/core.py:1085" *) any_unit_busy;
  assign dwrite_start_sig = \$147  & (* src = "/home/runner/workspace/hardware/core.py:1085" *) \$148 ;
  assign \$149  = bfins_start_sig ? (* src = "/home/runner/workspace/hardware/core.py:1101" *) instruction[22:19] : 4'h0;
  assign dr_rd_addr2 = \busy$20  ? (* src = "/home/runner/workspace/hardware/core.py:1100" *) dr_rd_addr : \$149 ;
  assign \$150  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1115" *) is_iadd_op;
  assign \$151  = ~ (* src = "/home/runner/workspace/hardware/core.py:1115" *) any_unit_busy;
  assign iadd_start_sig = \$150  & (* src = "/home/runner/workspace/hardware/core.py:1115" *) \$151 ;
  assign \$152  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1116" *) is_isub_op;
  assign \$153  = ~ (* src = "/home/runner/workspace/hardware/core.py:1116" *) any_unit_busy;
  assign isub_start_sig = \$152  & (* src = "/home/runner/workspace/hardware/core.py:1116" *) \$153 ;
  assign \$154  = iadd_start_sig | (* src = "/home/runner/workspace/hardware/core.py:1137" *) isub_start_sig;
  assign \$155  = \$154  | (* src = "/home/runner/workspace/hardware/core.py:1137" *) shl_start_sig;
  assign \$156  = \$155  | (* src = "/home/runner/workspace/hardware/core.py:1137" *) shr_start_sig;
  assign \$157  = \$156  | (* src = "/home/runner/workspace/hardware/core.py:1137" *) bfext_start_sig;
  assign \$158  = \$157  | (* src = "/home/runner/workspace/hardware/core.py:1137" *) bfins_start_sig;
  assign \$159  = \$158  | (* src = "/home/runner/workspace/hardware/core.py:1137" *) mcmp_start_sig;
  assign \$160  = \$159  ? (* src = "/home/runner/workspace/hardware/core.py:1137" *) instruction[18:15] : 4'h0;
  assign \$161  = \busy$20  ? (* src = "/home/runner/workspace/hardware/core.py:1136" *) \dr_rd_addr2$410  : \$160 ;
  assign dr_rd_addr1 = \busy$19  ? (* src = "/home/runner/workspace/hardware/core.py:1135" *) \dr_rd_addr$411  : \$161 ;
  assign iadd_result = dr_rd_data + (* src = "/home/runner/workspace/hardware/core.py:1145" *) { instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14:0] };
  assign isub_result = dr_rd_data - (* src = "/home/runner/workspace/hardware/core.py:1146" *) { instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14:0] };
  assign \$162  = ! (* src = "/home/runner/workspace/hardware/core.py:1153" *) iadd_result[31:0];
  assign \$163  = ! (* src = "/home/runner/workspace/hardware/core.py:1157" *) isub_result[31:0];
  assign \$164  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1171" *) is_shl_op;
  assign \$165  = ~ (* src = "/home/runner/workspace/hardware/core.py:1171" *) any_unit_busy;
  assign shl_start_sig = \$164  & (* src = "/home/runner/workspace/hardware/core.py:1171" *) \$165 ;
  assign \$166  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1172" *) is_shr_op;
  assign \$167  = ~ (* src = "/home/runner/workspace/hardware/core.py:1172" *) any_unit_busy;
  assign shr_start_sig = \$166  & (* src = "/home/runner/workspace/hardware/core.py:1172" *) \$167 ;
  assign \$168  = dr_rd_data << (* src = "/home/runner/workspace/hardware/core.py:1183" *) instruction[4:0];
  assign lsr_result = dr_rd_data >> (* src = "/home/runner/workspace/hardware/core.py:1195" *) instruction[4:0];
  assign \$169  = { dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data } >> (* src = "/home/runner/workspace/hardware/core.py:1196" *) instruction[4:0];
  assign shr_result = instruction[5] ? (* src = "/home/runner/workspace/hardware/core.py:1197" *) \$169 [31:0] : lsr_result;
  assign \$170  = instruction[4:0] - (* src = "/home/runner/workspace/hardware/core.py:1208" *) 1'h1;
  assign \$171  = 6'h20 - (* src = "/home/runner/workspace/hardware/core.py:1209" *) instruction[4:0];
  assign \$172  = ! (* src = "/home/runner/workspace/hardware/core.py:1210" *) instruction[4:0];
  assign \$173  = dr_rd_data >> (* src = "/home/runner/workspace/hardware/core.py:1211" *) \$170 [4:0];
  assign shr_c_bit = \$172  ? (* src = "/home/runner/workspace/hardware/core.py:1210" *) 1'h0 : \$173 [0];
  assign \$174  = ! (* src = "/home/runner/workspace/hardware/core.py:1212" *) instruction[4:0];
  assign \$175  = dr_rd_data >> (* src = "/home/runner/workspace/hardware/core.py:1213" *) \$171 [5:0];
  assign shl_c_bit = \$174  ? (* src = "/home/runner/workspace/hardware/core.py:1212" *) 1'h0 : \$175 [0];
  assign \$176  = ! (* src = "/home/runner/workspace/hardware/core.py:1220" *) \$168 [31:0];
  assign \$177  = ! (* src = "/home/runner/workspace/hardware/core.py:1224" *) shr_result;
  assign \$178  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1236" *) is_bfext_op;
  assign \$179  = ~ (* src = "/home/runner/workspace/hardware/core.py:1236" *) any_unit_busy;
  assign bfext_start_sig = \$178  & (* src = "/home/runner/workspace/hardware/core.py:1236" *) \$179 ;
  assign \$180  = 1'h1 << (* src = "/home/runner/workspace/hardware/core.py:1245" *) instruction[9:5];
  assign \$181  = \$180  - (* src = "/home/runner/workspace/hardware/core.py:1245" *) 1'h1;
  assign \$182  = dr_rd_data >> (* src = "/home/runner/workspace/hardware/core.py:1246" *) instruction[4:0];
  assign bfext_result = \$182  & (* src = "/home/runner/workspace/hardware/core.py:1246" *) \$181 [31:0];
  assign \$183  = ! (* src = "/home/runner/workspace/hardware/core.py:1252" *) bfext_result;
  assign \$184  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1266" *) is_bfins_op;
  assign \$185  = ~ (* src = "/home/runner/workspace/hardware/core.py:1266" *) any_unit_busy;
  assign bfins_start_sig = \$184  & (* src = "/home/runner/workspace/hardware/core.py:1266" *) \$185 ;
  assign \$186  = \$181 [31:0] << (* src = "/home/runner/workspace/hardware/core.py:1271" *) instruction[4:0];
  assign \$187  = ~ (* src = "/home/runner/workspace/hardware/core.py:1273" *) \$186 [31:0];
  assign \$188  = \dr_rd_data$401  & (* src = "/home/runner/workspace/hardware/core.py:1273" *) \$187 ;
  assign \$189  = dr_rd_data & (* src = "/home/runner/workspace/hardware/core.py:1274" *) \$181 [31:0];
  assign \$190  = \$189  << (* src = "/home/runner/workspace/hardware/core.py:1274" *) instruction[4:0];
  assign \$191  = { 31'h00000000, \$188  } | (* src = "/home/runner/workspace/hardware/core.py:1273" *) \$190 ;
  assign \$192  = ! (* src = "/home/runner/workspace/hardware/core.py:1281" *) \$191 [31:0];
  assign \$193  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1292" *) is_mcmp_op;
  assign \$194  = ~ (* src = "/home/runner/workspace/hardware/core.py:1292" *) any_unit_busy;
  assign mcmp_start_sig = \$193  & (* src = "/home/runner/workspace/hardware/core.py:1292" *) \$194 ;
  assign mcmp_result = dr_rd_data - (* src = "/home/runner/workspace/hardware/core.py:1295" *) { instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14:0] };
  assign \$195  = ! (* src = "/home/runner/workspace/hardware/core.py:1300" *) mcmp_result[31:0];
  assign \$196  = boot_complete & (* src = "/home/runner/workspace/hardware/core.py:1313" *) exec_enable;
  assign \$197  = \$196  & (* src = "/home/runner/workspace/hardware/core.py:1313" *) is_branch_op;
  assign \$198  = ~ (* src = "/home/runner/workspace/hardware/core.py:1313" *) any_unit_busy;
  assign branch_taken = \$197  & (* src = "/home/runner/workspace/hardware/core.py:1313" *) \$198 ;
  assign \$199  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1323" *) is_church_op;
  assign \$200  = ! (* src = "/home/runner/workspace/hardware/core.py:1323" *) instruction[31:27];
  assign \$201  = \$199  & (* src = "/home/runner/workspace/hardware/core.py:1323" *) \$200 ;
  assign \$202  = ~ (* src = "/home/runner/workspace/hardware/core.py:1323" *) any_unit_busy;
  assign load_start_sig = \$201  & (* src = "/home/runner/workspace/hardware/core.py:1323" *) \$202 ;
  assign \$203  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1335" *) is_church_op;
  assign \$204  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:1335" *) 3'h4;
  assign \$205  = \$203  & (* src = "/home/runner/workspace/hardware/core.py:1335" *) \$204 ;
  assign \$206  = ~ (* src = "/home/runner/workspace/hardware/core.py:1335" *) any_unit_busy;
  assign change_start_sig = \$205  & (* src = "/home/runner/workspace/hardware/core.py:1335" *) \$206 ;
  assign m_elevated = boot_state != (* src = "/home/runner/workspace/hardware/core.py:1341" *) 3'h6;
  assign \$207  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1360" *) is_church_op;
  assign \$208  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:1360" *) 3'h5;
  assign \$209  = \$207  & (* src = "/home/runner/workspace/hardware/core.py:1360" *) \$208 ;
  assign \$210  = ~ (* src = "/home/runner/workspace/hardware/core.py:1360" *) any_unit_busy;
  assign switch_start_sig = \$209  & (* src = "/home/runner/workspace/hardware/core.py:1360" *) \$210 ;
  assign \$211  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1375" *) is_church_op;
  assign \$212  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:1375" *) 4'h8;
  assign \$213  = \$211  & (* src = "/home/runner/workspace/hardware/core.py:1375" *) \$212 ;
  assign \$214  = ~ (* src = "/home/runner/workspace/hardware/core.py:1375" *) any_unit_busy;
  assign eloadcall_start_sig = \$213  & (* src = "/home/runner/workspace/hardware/core.py:1375" *) \$214 ;
  assign \$215  = cond_exec_enable & (* src = "/home/runner/workspace/hardware/core.py:1392" *) is_church_op;
  assign \$216  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/core.py:1392" *) 4'h9;
  assign \$217  = \$215  & (* src = "/home/runner/workspace/hardware/core.py:1392" *) \$216 ;
  assign \$218  = ~ (* src = "/home/runner/workspace/hardware/core.py:1392" *) any_unit_busy;
  assign xloadlambda_start_sig = \$217  & (* src = "/home/runner/workspace/hardware/core.py:1392" *) \$218 ;
  assign rd_addr = \busy$40  ? (* src = "/home/runner/workspace/hardware/core.py:1410" *) \pet_name_rd_addr$489  : pet_name_rd_addr;
  assign \$219  = lazy_load_irq ? (* src = "/home/runner/workspace/hardware/core.py:1431" *) 2'h1 : 2'h2;
  assign \$220  = lazy_resolve_irq ? (* src = "/home/runner/workspace/hardware/core.py:1437" *) \pet_name_rd_addr$489  : pet_name_rd_addr;
  assign \$221  = lazy_load_irq ? (* src = "/home/runner/workspace/hardware/core.py:1436" *) lazy_load_ns_slot : \$220 ;
  assign \$223  = \$222  | (* src = "/home/runner/workspace/hardware/core.py:1441" *) lazy_resolve_irq;
  assign \$224  = \$223  | (* src = "/home/runner/workspace/hardware/core.py:1441" *) \lazy_resolve_irq$502 ;
  assign \$225  = ~ (* src = "/home/runner/workspace/hardware/core.py:1443" *) \busy$42 ;
  assign irq_dispatch_start = \$224  & (* src = "/home/runner/workspace/hardware/core.py:1441" *) \$225 ;
  assign \$226  = imem_addr + (* src = "/home/runner/workspace/hardware/core.py:1453" *) 3'h4;
  assign _outform_start = \$227  | (* src = "/home/runner/workspace/hardware/core.py:1463" *) \outform_start_out$513 ;
  assign \$228  = \outform_start_out$513  ? (* src = "/home/runner/workspace/hardware/core.py:1480" *) outform_gt_raw_out : outform_gt_raw;
  assign \$229  = \outform_start_out$513  ? (* src = "/home/runner/workspace/hardware/core.py:1485" *) outform_slot_id_out : outform_slot_id;
  assign \$230  = ~ (* src = "/home/runner/workspace/hardware/core.py:1497" *) outform_mode2_active;
  assign outform_done_in = outform_done & (* src = "/home/runner/workspace/hardware/core.py:1497" *) \$230 ;
  assign \$231  = ~ (* src = "/home/runner/workspace/hardware/core.py:1498" *) outform_mode2_active;
  assign outform_fault_in = outform_fault & (* src = "/home/runner/workspace/hardware/core.py:1498" *) \$231 ;
  assign \outform_done_in$544  = \$232  & (* src = "/home/runner/workspace/hardware/core.py:1501" *) outform_mode2_active;
  assign \outform_fault_in$546  = outform_fault & (* src = "/home/runner/workspace/hardware/core.py:1503" *) outform_mode2_active;
  assign \$233  = 1'h1 << (* src = "/home/runner/workspace/hardware/core.py:1794" *) alloc_n;
  assign \$234  = \$233 [31:0] - (* src = "/home/runner/workspace/hardware/core.py:1795" *) 1'h1;
  assign \$235  = watermark_reg_noniot + (* src = "/home/runner/workspace/hardware/core.py:1797" *) \$234 [31:0];
  assign \$236  = ~ (* src = "/home/runner/workspace/hardware/core.py:1797" *) \$234 [31:0];
  assign \$237  = \$235  & (* src = "/home/runner/workspace/hardware/core.py:1797" *) { 1'h0, \$236  };
  assign \$238  = \$237 [31:0] + (* src = "/home/runner/workspace/hardware/core.py:1800" *) \$233 [31:0];
  assign alloc_fits_ni = \$238 [32:0] <= (* src = "/home/runner/workspace/hardware/core.py:1804" *) 12'h800;
  assign \$239  = alloc_n >= (* src = "/home/runner/workspace/hardware/core.py:1806" *) 3'h6;
  assign \$240  = alloc_n <= (* src = "/home/runner/workspace/hardware/core.py:1806" *) 4'he;
  assign alloc_n_ok_ni = \$239  & (* src = "/home/runner/workspace/hardware/core.py:1806" *) \$240 ;
  assign \$241  = alloc_req & (* src = "/home/runner/workspace/hardware/core.py:1811" *) alloc_fits_ni;
  assign alloc_done = \$241  & (* src = "/home/runner/workspace/hardware/core.py:1811" *) alloc_n_ok_ni;
  assign \$242  = ~ (* src = "/home/runner/workspace/hardware/core.py:1814" *) alloc_fits_ni;
  assign \$243  = ~ (* src = "/home/runner/workspace/hardware/core.py:1814" *) alloc_n_ok_ni;
  assign \$244  = \$242  | (* src = "/home/runner/workspace/hardware/core.py:1814" *) \$243 ;
  assign alloc_fault = alloc_req & (* src = "/home/runner/workspace/hardware/core.py:1814" *) \$244 ;
  assign \$247  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/core.py:1836" *) \$246 ;
  assign mint_slot_id_p3_ni = mint_slot_id_reg + (* src = "/home/runner/workspace/hardware/core.py:1842" *) 2'h3;
  assign \$249  = mint_lump_size_reg - (* src = "/home/runner/workspace/hardware/core.py:1849" *) 1'h1;
  assign \$251  = { mint_base_reg_ni[24:0], mint_base_reg_ni[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { \w1_masked$569 [18:0], \w1_masked$569 [31:19] };
  assign \$252  = mint_hdr_reg_ni[26:23] + (* src = "/home/runner/workspace/hardware/core.py:1878" *) 3'h6;
  assign \$253  = 1'h1 << (* src = "/home/runner/workspace/hardware/core.py:1878" *) \$252 ;
  assign \$254  = mint_lump_size_reg - (* src = "/home/runner/workspace/hardware/core.py:1898" *) mint_cc_reg_ni;
  assign \$255  = $signed(\$254 ) - (* src = "/home/runner/workspace/hardware/core.py:1898" *) $signed(2'h1);
  assign \$256  = mint_scan_idx_reg_ni > (* src = "/home/runner/workspace/hardware/core.py:1899" *) scan_end_c_ni;
  assign \$258  = mint_base_reg_ni + (* src = "/home/runner/workspace/hardware/core.py:1906" *) \$257 ;
  assign \$259  = \$247 [31:0] + (* src = "/home/runner/workspace/hardware/core.py:1925" *) 3'h4;
  assign \$260  = \$247 [31:0] + (* src = "/home/runner/workspace/hardware/core.py:1933" *) 4'h8;
  assign \$261  = \$247 [31:0] + (* src = "/home/runner/workspace/hardware/core.py:1941" *) 4'hc;
  assign \$262  = mint_copy_idx_reg_ni >= (* src = "/home/runner/workspace/hardware/core.py:1950" *) mint_cc_reg_ni;
  assign \$263  = mint_cc_base_reg_ni + (* src = "/home/runner/workspace/hardware/core.py:1954" *) mint_copy_idx_reg_ni;
  assign \$265  = mint_base_reg_ni + (* src = "/home/runner/workspace/hardware/core.py:1958" *) \$264 ;
  assign \$267  = { mint_slot_id_p3_ni, 8'h00 } + (* src = "/home/runner/workspace/hardware/core.py:1971" *) \$266 ;
  assign mint_busy = ~ (* src = "/home/runner/workspace/hardware/core.py:1999" *) \$286 ;
  assign \$268  = call_normal_complete | (* src = "/home/runner/workspace/hardware/core.py:2025" *) complete;
  assign mwin_trigger = \$269  & (* src = "/home/runner/workspace/hardware/core.py:2025" *) cr15_m_flag;
  assign mwin_dr11_valid = | (* src = "/home/runner/workspace/hardware/core.py:2039" *) dbg_m_dr11[26:25];
  assign \$270  = { mwin_dr12_lat[24:0], mwin_dr12_lat[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { \w1_masked$600 [18:0], \w1_masked$600 [31:19] };
  assign mwin_integrity_ok = mwin_integrity_computed == (* src = "/home/runner/workspace/hardware/core.py:2045" *) mwin_dr14_lat;
  assign mwin_gtseq_ok = mwin_dr11_lat[24:16] == (* src = "/home/runner/workspace/hardware/core.py:2055" *) mwin_dr13_lat[29:21];
  assign \$271  = mwin_fnv_xor * (* src = "/home/runner/workspace/hardware/core.py:2072" *) 25'h1000193;
  assign mwin_seal_computed = \$271 [31:0] ^ (* src = "/home/runner/workspace/hardware/core.py:2074" *) mwin_dr13_lat;
  assign mwin_seal_ok = mwin_seal_computed[24:0] == (* src = "/home/runner/workspace/hardware/core.py:2076" *) mwin_dr15_lat[24:0];
  assign \$273  = mwin_integrity_ok & (* src = "/home/runner/workspace/hardware/core.py:2109" *) mwin_gtseq_ok;
  assign \$274  = \$273  & (* src = "/home/runner/workspace/hardware/core.py:2109" *) mwin_seal_ok;
  assign \$275  = ~ (* src = "/home/runner/workspace/hardware/core.py:2147" *) any_unit_busy;
  assign \$276  = boot_complete & (* src = "/home/runner/workspace/hardware/core.py:2147" *) \$275 ;
  assign \$277  = code_lo_reg != (* src = "/home/runner/workspace/hardware/core.py:2148" *) code_hi_reg;
  assign \$278  = \$276  & (* src = "/home/runner/workspace/hardware/core.py:2147" *) \$277 ;
  assign \$279  = imem_addr < (* src = "/home/runner/workspace/hardware/core.py:2149" *) code_lo_reg;
  assign \$280  = imem_addr >= (* src = "/home/runner/workspace/hardware/core.py:2149" *) code_hi_reg;
  assign \$281  = \$279  | (* src = "/home/runner/workspace/hardware/core.py:2149" *) \$280 ;
  assign fetch_bounds_fault = \$278  & (* src = "/home/runner/workspace/hardware/core.py:2147" *) \$281 ;
  assign \$282  = ~ (* src = "/home/runner/workspace/hardware/core.py:2187" *) outform_mode2_active;
  assign \$283  = outform_fault & (* src = "/home/runner/workspace/hardware/core.py:2187" *) \$282 ;
  assign \$284  = mem_rd_en | (* src = "/home/runner/workspace/hardware/core.py:2300" *) mem_wr_en;
  assign \$285  = \dmem_addr$735  == (* src = "/home/runner/workspace/hardware/core.py:2342" *) 32'd4294967096;
  assign \$286  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) mint_noniot_state;
  assign \$287  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$288  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$289  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$290  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$291  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$292  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$293  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$294  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$295  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$296  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$297  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign \$298  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$299  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$300  = mint_noniot_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'he;
  assign \$301  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) mwin_state;
  assign \$302  = mwin_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$303  = mwin_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$304  = \fault_valid$640  & (* src = "/home/runner/workspace/hardware/core.py:741" *) boot_complete;
  assign \$305  = reboot_request | (* src = "/home/runner/workspace/hardware/core.py:741" *) \$304 ;
  assign \$306  = ~ (* src = "/home/runner/workspace/hardware/core.py:761" *) fetch_bounds_fault;
  assign \$307  = branch_taken & (* src = "/home/runner/workspace/hardware/core.py:761" *) \$306 ;
  assign \$308  = boot_complete & (* src = "/home/runner/workspace/hardware/core.py:767" *) instr_valid;
  assign \$309  = ~ (* src = "/home/runner/workspace/hardware/core.py:767" *) any_unit_busy;
  assign \$310  = \$308  & (* src = "/home/runner/workspace/hardware/core.py:767" *) \$309 ;
  assign \$311  = ~ (* src = "/home/runner/workspace/hardware/core.py:768" *) fetch_bounds_fault;
  assign \$312  = \$310  & (* src = "/home/runner/workspace/hardware/core.py:767" *) \$311 ;
  assign \$313  = ~ (* src = "/home/runner/workspace/hardware/core.py:768" *) intercept_start;
  assign \$314  = \$312  & (* src = "/home/runner/workspace/hardware/core.py:767" *) \$313 ;
  assign \$315  = imem_addr + (* src = "/home/runner/workspace/hardware/core.py:765" *) { instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14:0], 2'h0 };
  assign \$316  = imem_addr + (* src = "/home/runner/workspace/hardware/core.py:775" *) 3'h4;
  assign \$317  = reboot_request | (* src = "/home/runner/workspace/hardware/core.py:792" *) clear_all;
  assign \$318  = complete & (* src = "/home/runner/workspace/hardware/core.py:799" *) cross_domain_ret;
  assign \$319  = ~ (* src = "/home/runner/workspace/hardware/core.py:804" *) cross_domain_ret;
  assign \$320  = complete & (* src = "/home/runner/workspace/hardware/core.py:804" *) \$319 ;
  assign \$321  = \cr_wr_addr$142  == (* src = "/home/runner/workspace/hardware/core.py:807" *) 4'he;
  assign \$322  = \cr_wr_en$137  & (* src = "/home/runner/workspace/hardware/core.py:807" *) \$321 ;
  assign \$323  = nia_set | (* src = "/home/runner/workspace/hardware/core.py:821" *) \nia_set$766 ;
  assign \$324  = \$323  | (* src = "/home/runner/workspace/hardware/core.py:821" *) \nia_set$763 ;
  assign \$325  = \$324  | (* src = "/home/runner/workspace/hardware/core.py:821" *) \nia_set$767 ;
  assign \$326  = \cr_wr_data$155 [84:64] + (* src = "/home/runner/workspace/hardware/core.py:817" *) 1'h1;
  assign \$328  = \cr_wr_data$155 [63:32] + (* src = "/home/runner/workspace/hardware/core.py:816" *) \$327 ;
  assign \$329  = ~ (* src = "/home/runner/workspace/hardware/core.py:1000" *) lambda_active_reg;
  assign \$330  = ~ (* src = "/home/runner/workspace/hardware/core.py:1002" *) \fault_valid$628 ;
  assign \$331  = complete & (* src = "/home/runner/workspace/hardware/core.py:1002" *) \$330 ;
  assign \$332  = ~ (* src = "/home/runner/workspace/hardware/core.py:1002" *) reboot_request;
  assign \$333  = \$331  & (* src = "/home/runner/workspace/hardware/core.py:1002" *) \$332 ;
  assign \$334  = \$333  & (* src = "/home/runner/workspace/hardware/core.py:1002" *) cross_domain_ret;
  assign \$335  = ~ (* src = "/home/runner/workspace/hardware/core.py:1020" *) call_fault;
  assign \$336  = call_normal_complete & (* src = "/home/runner/workspace/hardware/core.py:1020" *) \$335 ;
  assign \$337  = ~ (* src = "/home/runner/workspace/hardware/core.py:1022" *) lambda_fault;
  assign \$338  = lambda_complete & (* src = "/home/runner/workspace/hardware/core.py:1022" *) \$337 ;
  assign \$339  = ~ (* src = "/home/runner/workspace/hardware/core.py:1121" *) iadd_busy_reg;
  assign \$340  = iadd_start_sig & (* src = "/home/runner/workspace/hardware/core.py:1121" *) \$339 ;
  assign \$341  = ~ (* src = "/home/runner/workspace/hardware/core.py:1122" *) isub_busy_reg;
  assign \$342  = isub_start_sig & (* src = "/home/runner/workspace/hardware/core.py:1122" *) \$341 ;
  assign \$343  = ~ (* src = "/home/runner/workspace/hardware/core.py:1175" *) shl_busy_reg;
  assign \$344  = shl_start_sig & (* src = "/home/runner/workspace/hardware/core.py:1175" *) \$343 ;
  assign \$345  = ~ (* src = "/home/runner/workspace/hardware/core.py:1176" *) shr_busy_reg;
  assign \$346  = shr_start_sig & (* src = "/home/runner/workspace/hardware/core.py:1176" *) \$345 ;
  assign \$347  = ~ (* src = "/home/runner/workspace/hardware/core.py:1237" *) bfext_busy_reg;
  assign \$348  = bfext_start_sig & (* src = "/home/runner/workspace/hardware/core.py:1237" *) \$347 ;
  assign \$349  = ~ (* src = "/home/runner/workspace/hardware/core.py:1267" *) bfins_busy_reg;
  assign \$350  = bfins_start_sig & (* src = "/home/runner/workspace/hardware/core.py:1267" *) \$349 ;
  assign \$351  = ~ (* src = "/home/runner/workspace/hardware/core.py:1293" *) mcmp_busy_reg;
  assign \$352  = mcmp_start_sig & (* src = "/home/runner/workspace/hardware/core.py:1293" *) \$351 ;
  assign \$353  = ~ (* src = "/home/runner/workspace/hardware/core.py:1315" *) branch_busy_reg;
  assign \$354  = branch_taken & (* src = "/home/runner/workspace/hardware/core.py:1315" *) \$353 ;
  assign \$355  = outform_done | (* src = "/home/runner/workspace/hardware/core.py:1473" *) outform_fault;
  assign \$356  = \outform_start_out$513  ? (* src = "/home/runner/workspace/hardware/core.py:1517" *) outform_slot_id_out : outform_slot_id;
  assign \$358  = \outform_start_out$513  ? (* src = "/home/runner/workspace/hardware/core.py:1530" *) 32'd0 : outform_clist_addr;
  assign \$360  = alloc_req & (* src = "/home/runner/workspace/hardware/core.py:1818" *) alloc_fits_ni;
  assign \$361  = \$360  & (* src = "/home/runner/workspace/hardware/core.py:1818" *) alloc_n_ok_ni;
  assign \$362  = mint_hdr_reg_ni[31:27] != (* src = "/home/runner/workspace/hardware/core.py:1879" *) 5'h1f;
  assign \$363  = mint_hdr_reg_ni[26:23] > (* src = "/home/runner/workspace/hardware/core.py:1881" *) 4'h8;
  assign \$364  = lsz_c_ni - (* src = "/home/runner/workspace/hardware/core.py:1883" *) 2'h2;
  assign \$365  = $signed({ 1'h0, mint_hdr_reg_ni[7:0] }) > (* src = "/home/runner/workspace/hardware/core.py:1883" *) $signed(\$364 );
  assign \$366  = lsz_c_ni - (* src = "/home/runner/workspace/hardware/core.py:1885" *) mint_hdr_reg_ni[7:0];
  assign \$367  = $signed(\$366 ) - (* src = "/home/runner/workspace/hardware/core.py:1885" *) $signed(3'h2);
  assign \$368  = $signed({ 1'h0, mint_hdr_reg_ni[22:10] }) > (* src = "/home/runner/workspace/hardware/core.py:1885" *) $signed(\$367 );
  assign \$369  = mint_hdr_reg_ni[22:10] + (* src = "/home/runner/workspace/hardware/core.py:1892" *) 1'h1;
  assign \$370  = mint_scan_idx_reg_ni > (* src = "/home/runner/workspace/hardware/core.py:1899" *) scan_end_c_ni;
  assign \$371  = | (* src = "/home/runner/workspace/hardware/core.py:1909" *) mem_rd_data;
  assign \$372  = mint_scan_idx_reg_ni + (* src = "/home/runner/workspace/hardware/core.py:1912" *) 1'h1;
  assign \$373  = mint_lump_size_reg - (* src = "/home/runner/workspace/hardware/core.py:1946" *) mint_cc_reg_ni;
  assign \$374  = mint_copy_idx_reg_ni >= (* src = "/home/runner/workspace/hardware/core.py:1950" *) mint_cc_reg_ni;
  assign \$375  = mint_copy_idx_reg_ni + (* src = "/home/runner/workspace/hardware/core.py:1976" *) 1'h1;
  (* src = "/home/runner/workspace/hardware/core.py:245" *)
  always @(posedge clk)
    boot_state <= \$376 ;
  (* src = "/home/runner/workspace/hardware/core.py:226" *)
  always @(posedge clk)
    imem_addr <= \$377 ;
  (* src = "/home/runner/workspace/hardware/core.py:238" *)
  always @(posedge clk)
    code_lo_reg <= \$378 ;
  (* src = "/home/runner/workspace/hardware/core.py:239" *)
  always @(posedge clk)
    code_hi_reg <= \$379 ;
  (* src = "/home/runner/workspace/hardware/core.py:240" *)
  always @(posedge clk)
    fence_pending_reg <= \$380 ;
  (* src = "/home/runner/workspace/hardware/core.py:314" *)
  always @(posedge clk)
    cross_domain_ret <= \$381 ;
  (* src = "/home/runner/workspace/hardware/core.py:315" *)
  always @(posedge clk)
    cload_pending <= \$382 ;
  (* src = "/home/runner/workspace/hardware/core.py:242" *)
  always @(posedge clk)
    lambda_active_reg <= \$383 ;
  assign \$auto$rtlil.cc:2739:Not$34  = ~ { \$104 [31:30], \$104 [28:25], \$104 [23], \$104 [21], \$104 [19:18], \$104 [16:15], \$104 [13:9], \$104 [7:5], \$104 [3:0] };
  assign \$auto$rtlil.cc:2739:Not$36  = ~ { \$251 [31:30], \$251 [28:25], \$251 [23], \$251 [21], \$251 [19:18], \$251 [16:15], \$251 [13:9], \$251 [7:5], \$251 [3:0] };
  assign \$auto$rtlil.cc:2739:Not$38  = ~ { \$270 [31:30], \$270 [28:25], \$270 [23], \$270 [21], \$270 [19:18], \$270 [16:15], \$270 [13:9], \$270 [7:5], \$270 [3:0] };
  assign \$auto$rtlil.cc:2739:Not$40  = ~ { mwin_dr12_lat[31], mwin_dr12_lat[24], mwin_dr12_lat[20:18], mwin_dr12_lat[15], mwin_dr12_lat[12:10], mwin_dr12_lat[8:6], mwin_dr12_lat[2], mwin_dr12_lat[0] };
  (* src = "/home/runner/workspace/hardware/core.py:178" *)
  \top.core.u_call  u_call (
    .clk(clk),
    .call_busy(call_busy),
    .call_fault(call_fault),
    .call_normal_complete(call_normal_complete),
    .call_start(call_start_sig),
    .caller_pc(imem_addr[16:2]),
    .code_hi_out(code_hi_out),
    .code_lo_out(code_lo_out),
    .cr12_thread(cr12_thread),
    .cr14_code(cr14_code),
    .cr15_namespace(cr15_namespace),
    .cr5_heap(cr5_heap),
    .cr_b_clear_mask(cr_b_clear_mask),
    .cr_null_mask(cr_null_mask),
    .cr_rd_addr(\cr_rd_addr$61 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$146 ),
    .cr_wr_data(\cr_wr_data$159 ),
    .cr_wr_en(\cr_wr_en$133 ),
    .fault_type(\fault_type$645 ),
    .lazy_load_irq(lazy_load_irq),
    .lazy_load_ns_slot(lazy_load_ns_slot),
    .mem_rd_addr(mem_rd_addr),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$715 ),
    .mem_rd_valid(mem_rd_valid),
    .mem_wr_addr(mem_wr_addr),
    .mem_wr_data(\mem_wr_data$730 ),
    .mem_wr_en(\mem_wr_en$716 ),
    .mgt_gt_lat(mgt_gt_word),
    .mgt_ns_authority(mgt_ns_authority),
    .mgt_ns_integrity(mgt_ns_integrity),
    .mgt_ns_location(mgt_ns_location),
    .mgt_ns_seals(mgt_ns_seals),
    .mgt_set_trigger(mgt_set_trigger),
    .mload_done(mload_done),
    .mload_dst(mload_cr_dst),
    .mload_fault(mload_fault),
    .mload_fault_type(\fault_type$648 ),
    .mload_index(mload_index),
    .mload_src(mload_cr_src),
    .mload_start(mload_start),
    .nia_computed(\nia_value$772 ),
    .\port$5930$0 (instruction[18:0]),
    .thread_hdr(thread_hdr)
  );
  (* src = "/home/runner/workspace/hardware/core.py:211" *)
  \top.core.u_change  u_change (
    .clk(clk),
    .change_busy(change_busy),
    .change_fault(change_fault),
    .change_start(change_start_sig),
    .cr12_thread(cr12_thread),
    .cr15_m_flag_in(cr15_m_flag),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$58 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$141 ),
    .cr_wr_data(\cr_wr_data$154 ),
    .cr_wr_en(\cr_wr_en$167 ),
    .dr_rd_data(dr_rd_data),
    .fault_type(\fault_type$649 ),
    .flags(flags),
    .m_elevated(m_elevated),
    .m_flag_restore_en(m_flag_restore_en),
    .m_flag_restore_val(m_flag_restore_val),
    .mem_rd_data(mem_rd_data),
    .mem_rd_valid(mem_rd_valid),
    .nia(imem_addr),
    .\port$5930$0 (instruction[22:0]),
    .thread_hdr_reg(thread_hdr)
  );
  (* src = "/home/runner/workspace/hardware/core.py:220" *)
  \top.core.u_cload  u_cload (
    .clk(clk),
    .cload_busy(cload_busy),
    .cload_fault(cload_fault),
    .cload_fault_type(cload_fault_type),
    .cload_start(cload_pending),
    .cr15_namespace(cr15_namespace),
    .cr_wr_addr(\cr_wr_addr$142 ),
    .cr_wr_data(\cr_wr_data$155 ),
    .cr_wr_en(\cr_wr_en$137 ),
    .e_gt(e_gt),
    .mem_addr(\mem_addr$740 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$721 ),
    .\mem_rd_valid$12 (mem_rd_valid)
  );
  (* src = "/home/runner/workspace/hardware/core.py:176" *)
  \top.core.u_decoder  u_decoder (
    .exec_enable(exec_enable),
    .fault(\fault$641 ),
    .fault_valid(fault_valid),
    .flags(flags),
    .instr_valid(instr_valid),
    .instruction(instruction),
    .is_bfext_op(is_bfext_op),
    .is_bfins_op(is_bfins_op),
    .is_branch_op(is_branch_op),
    .is_church_op(is_church_op),
    .is_dread_op(is_dread_op),
    .is_dwrite_op(is_dwrite_op),
    .is_iadd_op(is_iadd_op),
    .is_isub_op(is_isub_op),
    .is_mcmp_op(is_mcmp_op),
    .is_shl_op(is_shl_op),
    .is_shr_op(is_shr_op)
  );
  (* src = "/home/runner/workspace/hardware/core.py:218" *)
  \top.core.u_dread  u_dread (
    .clk(clk),
    .busy(\busy$19 ),
    .cr_rd_addr(\cr_rd_addr$54 ),
    .cr_rd_data(cr_rd_data),
    .dmem_addr(\dmem_addr$734 ),
    .dmem_rd_data(mem_rd_data),
    .dmem_rd_en(\dmem_rd_en$719 ),
    .dr_rd_addr(\dr_rd_addr$411 ),
    .dr_rd_data(dr_rd_data),
    .dr_wr_addr(\dr_wr_addr$104 ),
    .dr_wr_data(\dr_wr_data$106 ),
    .dr_wr_en(dr_wr_en),
    .fault(\fault$635 ),
    .fault_type(\fault_type$653 ),
    .\port$5930$0 (instruction[22:0]),
    .start(dread_start_sig)
  );
  (* src = "/home/runner/workspace/hardware/core.py:219" *)
  \top.core.u_dwrite  u_dwrite (
    .clk(clk),
    .busy(\busy$20 ),
    .cr_rd_addr(\cr_rd_addr$53 ),
    .cr_rd_data(cr_rd_data),
    .dmem_addr(\dmem_addr$735 ),
    .dmem_wr_data(\dmem_wr_data$738 ),
    .dmem_wr_en(\dmem_wr_en$720 ),
    .dr_rd_addr(dr_rd_addr),
    .dr_rd_addr2(\dr_rd_addr2$410 ),
    .dr_rd_data(\dr_rd_data$401 ),
    .dr_rd_data2(dr_rd_data),
    .fault(\fault$636 ),
    .fault_type(\fault_type$654 ),
    .\port$5930$0 (instruction[22:0]),
    .start(dwrite_start_sig)
  );
  (* src = "/home/runner/workspace/hardware/core.py:213" *)
  \top.core.u_eloadcall  u_eloadcall (
    .clk(clk),
    .busy(\busy$40 ),
    .complete(\nia_set$766 ),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$56 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$139 ),
    .cr_wr_data(\cr_wr_data$152 ),
    .cr_wr_en(\cr_wr_en$165 ),
    .fault(fault),
    .fault_type(\fault_type$651 ),
    .lazy_resolve_irq(lazy_resolve_irq),
    .lazy_resolve_slot(\pet_name_rd_addr$489 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_valid(mem_rd_valid),
    .nia_computed(\nia_value$773 ),
    .pet_name_rd_data(pet_name_rd_data),
    .\port$5930$0 (instruction[22:0]),
    .start(eloadcall_start_sig)
  );
  (* src = "/home/runner/workspace/hardware/core.py:209" *)
  \top.core.u_gc_unit  u_gc_unit (
    .clk(clk),
    .g_bit_reset(valid_key_access),
    .garbage_count(gc_garbage_count),
    .gc_busy(gc_busy),
    .ns_addr(\ns_addr$754 ),
    .ns_rd_en(\ns_rd_en$755 ),
    .ns_wr_data(\ns_wr_data$756 ),
    .ns_wr_en(\ns_wr_en$757 ),
    .\port$4577$0 (\port$4577$0 )
  );
  (* src = "/home/runner/workspace/hardware/core.py:215" *)
  \top.core.u_irq_dispatch  u_irq_dispatch (
    .clk(clk),
    .busy(\busy$42 ),
    .complete(\nia_set$767 ),
    .cr15_namespace(cr15_namespace),
    .dr1_wr_en(dr1_wr_en),
    .dr_wr_en(\dr_wr_en$123 ),
    .irq_reason(irq_dispatch_reason),
    .irq_slot(irq_dispatch_slot),
    .mem_rd_addr(\mem_rd_addr$746 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$725 ),
    .mem_rd_valid(mem_rd_valid),
    .nia_value(\nia_value$774 ),
    .reason_lat(\$407 ),
    .slot_lat(\$408 ),
    .start(irq_dispatch_start)
  );
  (* src = "/home/runner/workspace/hardware/core.py:210" *)
  \top.core.u_lambda  u_lambda (
    .clk(clk),
    .cr_rd_addr(\cr_rd_addr$63 ),
    .cr_rd_data(cr_rd_data),
    .cr_target(instruction[22:19]),
    .fault_type(\fault_type$643 ),
    .lambda_busy(lambda_busy),
    .lambda_complete(lambda_complete),
    .lambda_fault(lambda_fault),
    .lambda_start(lambda_start_sig),
    .nia_set(nia_set),
    .nia_value(nia_value)
  );
  (* src = "/home/runner/workspace/hardware/core.py:182" *)
  \top.core.u_load  u_load (
    .clk(clk),
    .fault_type(\fault_type$648 ),
    .load_busy(load_busy),
    .load_fault(load_fault),
    .load_start(load_start_sig),
    .mload_busy(sub_busy),
    .mload_done(mload_done),
    .mload_fault(mload_fault),
    .mload_m_elevated(\mload_m_elevated$695 ),
    .mload_start(\mload_start$689 ),
    .\port$5930$0 (instruction[22:0])
  );
  (* src = "/home/runner/workspace/hardware/core.py:221" *)
  \top.core.u_outform  u_outform (
    .clk(clk),
    .alloc_base(\$245 [31:0]),
    .alloc_done(alloc_done),
    .alloc_fault(alloc_fault),
    .alloc_n(alloc_n),
    .alloc_req(alloc_req),
    .gt_raw(gt_raw),
    .mem_wr_addr(\mem_wr_addr$741 ),
    .mem_wr_data(\mem_wr_data$742 ),
    .mem_wr_en(\mem_wr_en$722 ),
    .mint_base(mint_base),
    .mint_call(mint_call),
    .mint_done(mint_done_comb_ni),
    .mint_fault(mint_fault_comb_ni),
    .mint_result_gt(mint_result_gt),
    .outform_busy(outform_busy),
    .outform_done(outform_done),
    .outform_fault(outform_fault),
    .outform_fault_type(outform_fault_type_in),
    .outform_start(_outform_start),
    .result_gt(outform_result_gt),
    .slot_id(slot_id),
    .tx_byte(outform_tx_data),
    .tx_valid(outform_tx_valid)
  );
  (* src = "/home/runner/workspace/hardware/core.py:224" *)
  \top.core.u_outform_fsm  u_outform_fsm (
    .clk(clk),
    .busy(\busy$35 ),
    .cr_wr_addr(\cr_wr_addr$143 ),
    .cr_wr_data(\cr_wr_data$156 ),
    .cr_wr_en(\cr_wr_en$136 ),
    .fault(\fault$638 ),
    .fault_type(\fault_type$656 ),
    .intercept_start(intercept_start),
    .outform_done_in(\outform_done_in$544 ),
    .outform_fault_in(\outform_fault_in$546 ),
    .outform_fault_type_in(outform_fault_type_in),
    .outform_gt_raw_out(outform_gt_raw_out),
    .outform_slot_id_out(outform_slot_id_out),
    .outform_start_out(\outform_start_out$513 ),
    .result_gt_in(result_gt_in),
    .src_cr(instruction[18:15]),
    .src_cr_data(cr_rd_data)
  );
  (* src = "/home/runner/workspace/hardware/core.py:177" *)
  \top.core.u_perm_check  u_perm_check (
    .check_valid(check_valid),
    .fault_type(fault_type),
    .fault_valid(\fault_valid$624 ),
    .gt_in(cr_rd_data[31:0]),
    .required_perms(required_perms)
  );
  (* src = "/home/runner/workspace/hardware/core.py:216" *)
  \top.core.u_pet_name_mem  u_pet_name_mem (
    .clk(clk),
    .rd_addr(rd_addr),
    .rd_data(pet_name_rd_data),
    .wr_addr(wr_addr),
    .wr_data(wr_data),
    .wr_en(wr_en)
  );
  (* src = "/home/runner/workspace/hardware/core.py:175" *)
  \top.core.u_registers  u_registers (
    .clk(clk),
    .clear_all(clear_all),
    .cr0_gt_wr_data(32'd0),
    .cr0_gt_wr_en(1'h0),
    .cr10_gt_wr_data(cr10_gt_wr_data),
    .cr10_gt_wr_en(cr10_gt_wr_en),
    .cr11_gt_wr_data(cr11_gt_wr_data),
    .cr11_gt_wr_en(cr11_gt_wr_en),
    .cr12(cr12_thread),
    .cr12_gt_wr_data(cr12_gt_wr_data),
    .cr12_gt_wr_en(cr12_gt_wr_en),
    .cr13_gt_wr_data(cr13_gt_wr_data),
    .cr13_gt_wr_en(cr13_gt_wr_en),
    .cr14(cr14_code),
    .cr14_gt_wr_data(cr14_gt_wr_data),
    .cr14_gt_wr_en(cr14_gt_wr_en),
    .cr15(cr15_namespace),
    .cr15_gt_wr_data(cr15_gt_wr_data),
    .cr15_gt_wr_en(cr15_gt_wr_en),
    .cr15_m_flag(cr15_m_flag),
    .cr1_gt_wr_data(32'd0),
    .cr1_gt_wr_en(1'h0),
    .cr2_gt_wr_data(32'd0),
    .cr2_gt_wr_en(1'h0),
    .cr3_gt_wr_data(32'd0),
    .cr3_gt_wr_en(1'h0),
    .cr4_gt_wr_data(32'd0),
    .cr4_gt_wr_en(1'h0),
    .cr5(cr5_heap),
    .cr5_gt_wr_data(32'd0),
    .cr5_gt_wr_en(1'h0),
    .cr6_gt_wr_data(32'd0),
    .cr6_gt_wr_en(1'h0),
    .cr7_gt_wr_data(32'd0),
    .cr7_gt_wr_en(1'h0),
    .cr8_gt_wr_data(cr8_gt_wr_data),
    .cr8_gt_wr_en(cr8_gt_wr_en),
    .cr9_gt_wr_data(cr9_gt_wr_data),
    .cr9_gt_wr_en(cr9_gt_wr_en),
    .cr_b_clear_mask(cr_b_clear_mask),
    .cr_null_mask(cr_null_mask),
    .cr_rd_addr(cr_rd_addr),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(cr_wr_addr),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(\cr_wr_en$164 ),
    .dr_rd_addr1(dr_rd_addr1),
    .dr_rd_addr2(dr_rd_addr2),
    .dr_rd_data1(dr_rd_data),
    .dr_rd_data2(\dr_rd_data$401 ),
    .dr_wr_addr(dr_wr_addr),
    .dr_wr_data(dr_wr_data),
    .dr_wr_en(\dr_wr_en$107 ),
    .flags(flags),
    .flags_in(flags_in),
    .flags_wr_en(flags_wr_en),
    .m_clear_en(m_clear_en),
    .m_dr11(dbg_m_dr11),
    .m_dr12(dbg_m_dr12),
    .m_dr13(dbg_m_dr13),
    .m_dr14(dbg_m_dr14),
    .m_dr15(dbg_m_dr15),
    .m_flag_restore_en(m_flag_restore_en),
    .m_flag_restore_val(m_flag_restore_val),
    .m_set_dr11(m_set_dr11),
    .m_set_dr12(m_set_dr12),
    .m_set_dr13(m_set_dr13),
    .m_set_dr14(m_set_dr14),
    .m_set_dr15(m_set_dr15),
    .m_set_en(m_set_en)
  );
  (* src = "/home/runner/workspace/hardware/core.py:179" *)
  \top.core.u_return  u_return (
    .clk(clk),
    .busy(busy),
    .cload_e_gt(e_gt),
    .complete(complete),
    .cr12_thread(cr12_thread),
    .cr5_heap(cr5_heap),
    .cr_rd_addr(\cr_rd_addr$60 ),
    .cr_rd_data(cr_rd_data),
    .cr_src(instruction[17:15]),
    .fault_type(\fault_type$646 ),
    .fault_valid(\fault_valid$628 ),
    .lambda_active(lambda_active_reg),
    .lambda_clear(lambda_clear),
    .lambda_pc(lambda_pc),
    .mem_rd_addr(\mem_rd_addr$743 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$723 ),
    .mem_rd_valid(mem_rd_valid),
    .mem_wr_addr(\mem_wr_addr$744 ),
    .mem_wr_data(\mem_wr_data$745 ),
    .mem_wr_en(\mem_wr_en$724 ),
    .nia_set(\nia_set$764 ),
    .nia_value(\nia_value$771 ),
    .reboot_request(reboot_request),
    .return_start(ret_start_sig)
  );
  (* src = "/home/runner/workspace/hardware/core.py:181" *)
  \top.core.u_save  u_save (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$59 ),
    .cr_rd_data(cr_rd_data),
    .fault_type(\fault_type$647 ),
    .mem_rd_addr(\mem_rd_addr$733 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$718 ),
    .mem_rd_valid(mem_rd_valid),
    .mem_wr_addr(\mem_wr_addr$731 ),
    .mem_wr_data(\mem_wr_data$732 ),
    .mem_wr_en(\mem_wr_en$717 ),
    .\port$5930$0 (instruction[22:0]),
    .save_busy(save_busy),
    .save_fault(save_fault),
    .save_start(save_start_sig)
  );
  (* src = "/home/runner/workspace/hardware/core.py:184" *)
  \top.core.u_shared_mload  u_shared_mload (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$64 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$148 ),
    .cr_wr_data(\cr_wr_data$161 ),
    .cr_wr_en(cr_wr_en),
    .gbit_reset_done(valid_key_access),
    .mem_addr(mem_addr),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(mem_rd_en),
    .\mem_rd_valid$23 (mem_rd_valid),
    .mem_wr_data(mem_wr_data),
    .mem_wr_en(mem_wr_en),
    .outform_clist_addr(outform_clist_addr),
    .outform_done_in(outform_done_in),
    .outform_fault_in(outform_fault_in),
    .outform_fault_type_in(outform_fault_type_in),
    .outform_gt_raw(outform_gt_raw),
    .outform_slot_id(outform_slot_id),
    .outform_start_out(outform_start_out),
    .sub_busy(sub_busy),
    .sub_cr_dst(sub_cr_dst),
    .sub_cr_src(sub_cr_src),
    .sub_direct(sub_direct),
    .sub_direct_gt(sub_direct_gt),
    .sub_done(mload_done),
    .sub_fault(mload_fault),
    .sub_fault_type(\fault_type$648 ),
    .sub_index(sub_index),
    .sub_m_elevated(sub_m_elevated),
    .sub_start(sub_start)
  );
  (* src = "/home/runner/workspace/hardware/core.py:212" *)
  \top.core.u_switch  u_switch (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$57 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$140 ),
    .cr_wr_data(\cr_wr_data$153 ),
    .cr_wr_en(\cr_wr_en$168 ),
    .fault_type(\fault_type$650 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_valid(mem_rd_valid),
    .\port$5930$0 (instruction[17:0]),
    .switch_busy(switch_busy),
    .switch_fault(switch_fault),
    .switch_start(switch_start_sig)
  );
  (* src = "/home/runner/workspace/hardware/core.py:180" *)
  \top.core.u_tperm  u_tperm (
    .clk(clk),
    .cr_rd_addr(\cr_rd_addr$62 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$147 ),
    .cr_wr_data(\cr_wr_data$160 ),
    .cr_wr_en(\cr_wr_en$132 ),
    .fault_type(\fault_type$644 ),
    .\port$5930$15 (instruction[22:15]),
    .preset(instruction[3:0]),
    .tperm_busy(tperm_busy),
    .tperm_complete(tperm_complete),
    .tperm_fault(tperm_fault),
    .tperm_start(tperm_start_sig),
    .tperm_z_result(tperm_z_result)
  );
  (* src = "/home/runner/workspace/hardware/core.py:214" *)
  \top.core.u_xloadlambda  u_xloadlambda (
    .clk(clk),
    .busy(\busy$41 ),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$55 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$138 ),
    .cr_wr_data(\cr_wr_data$151 ),
    .cr_wr_en(\cr_wr_en$166 ),
    .fault(\fault$634 ),
    .fault_type(\fault_type$652 ),
    .lazy_resolve_irq(\lazy_resolve_irq$502 ),
    .lazy_resolve_slot(pet_name_rd_addr),
    .mem_rd_data(mem_rd_data),
    .mem_rd_valid(mem_rd_valid),
    .nia_set(\nia_set$763 ),
    .nia_value(\nia_value$770 ),
    .pet_name_rd_data(pet_name_rd_data),
    .\port$5930$0 (instruction[22:0]),
    .start(xloadlambda_start_sig)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$384  = lambda_pc;
    if (clear_all) begin
      \$384  = 32'd0;
    end else if (lambda_clear) begin
    end else if (\$336 ) begin
    end else if (\$338 ) begin
      \$384  = \$136 [31:0];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$385  = outform_mode2_active;
    if (\outform_start_out$513 ) begin
      \$385  = 1'h1;
    end else if (\$355 ) begin
      \$385  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$386  = mint_slot_id_reg;
    if (_outform_start) begin
      \$386  = \$357 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$387  = mint_clist_addr_reg;
    if (_outform_start) begin
      \$387  = \$359 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$388  = watermark_reg_noniot;
    if (\$361 ) begin
      \$388  = \$238 [31:0];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$389  = mint_base_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          if (mint_call) begin
            \$389  = mint_base;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$390  = mint_noniot_state;
    casez (mint_noniot_state)
      4'h0:
          if (mint_call) begin
            \$390  = 4'h1;
          end
      4'h1:
          \$390  = 4'h2;
      4'h2:
          \$390  = 4'h3;
      4'h3:
          (* full_case = 32'd1 *)
          if (\$362 ) begin
            \$390  = 4'h4;
          end else if (\$363 ) begin
            \$390  = 4'h4;
          end else if (\$365 ) begin
            \$390  = 4'h4;
          end else if (\$368 ) begin
            \$390  = 4'h4;
          end else begin
            \$390  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$370 ) begin
            \$390  = 4'h6;
          end else begin
            if (\$371 ) begin
              \$390  = 4'h4;
            end
          end
      4'h6:
          \$390  = 4'h7;
      4'h7:
          \$390  = 4'h8;
      4'h8:
          \$390  = 4'h9;
      4'h9:
          \$390  = 4'ha;
      4'ha:
          (* full_case = 32'd1 *)
          if (\$374 ) begin
            \$390  = 4'hb;
          end else begin
            \$390  = 4'hc;
          end
      4'hc:
          \$390  = 4'hd;
      4'hd:
          \$390  = 4'ha;
      4'hb:
          \$390  = 4'he;
      4'he:
          \$390  = 4'h0;
      4'h4:
          \$390  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$391  = mint_hdr_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          \$391  = mem_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$392  = mint_lump_size_reg;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          (* full_case = 32'd1 *)
          if (\$362 ) begin
          end else if (\$363 ) begin
          end else if (\$365 ) begin
          end else if (\$368 ) begin
          end else begin
            \$392  = lsz_c_ni;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$393  = mint_cw_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          (* full_case = 32'd1 *)
          if (\$362 ) begin
          end else if (\$363 ) begin
          end else if (\$365 ) begin
          end else if (\$368 ) begin
          end else begin
            \$393  = mint_hdr_reg_ni[22:10];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$394  = mint_cc_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          (* full_case = 32'd1 *)
          if (\$362 ) begin
          end else if (\$363 ) begin
          end else if (\$365 ) begin
          end else if (\$368 ) begin
          end else begin
            \$394  = mint_hdr_reg_ni[7:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$395  = mint_scan_idx_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          (* full_case = 32'd1 *)
          if (\$362 ) begin
          end else if (\$363 ) begin
          end else if (\$365 ) begin
          end else if (\$368 ) begin
          end else begin
            \$395  = \$369 ;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$370 ) begin
          end else begin
            (* full_case = 32'd1 *)
            if (\$371 ) begin
            end else begin
              \$395  = \$372 [13:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$396  = mint_copy_idx_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          if (\$370 ) begin
            \$396  = 8'h00;
          end
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          /* empty */;
      4'hd:
          \$396  = \$375 [7:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$397  = mint_cc_base_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          \$397  = \$373 [14:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$398  = mint_copy_data_reg_ni;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          \$398  = mem_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$399  = mwin_dr11_lat;
    casez (mwin_state)
      2'h0:
          if (mwin_trigger) begin
            \$399  = dbg_m_dr11;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$400  = mwin_dr12_lat;
    casez (mwin_state)
      2'h0:
          if (mwin_trigger) begin
            \$400  = dbg_m_dr12;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$401  = mwin_dr13_lat;
    casez (mwin_state)
      2'h0:
          if (mwin_trigger) begin
            \$401  = dbg_m_dr13;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$402  = mwin_dr14_lat;
    casez (mwin_state)
      2'h0:
          if (mwin_trigger) begin
            \$402  = dbg_m_dr14;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$403  = mwin_dr15_lat;
    casez (mwin_state)
      2'h0:
          if (mwin_trigger) begin
            \$403  = dbg_m_dr15;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$404  = mwin_state;
    casez (mwin_state)
      2'h0:
          if (mwin_trigger) begin
            (* full_case = 32'd1 *)
            if (mwin_dr11_valid) begin
              \$404  = 2'h1;
            end else begin
              \$404  = 2'h2;
            end
          end
      2'h1:
          \$404  = 2'h0;
      2'h2:
          \$404  = 2'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$405  = fault_instr;
    if (\fault_valid$640 ) begin
      \$405  = instruction;
    end else if (clear_all) begin
      \$405  = 32'd0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$406  = fault_stage;
    if (\fault_valid$640 ) begin
      \$406  = fault_stage_w;
    end else if (clear_all) begin
      \$406  = 4'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    casez (instruction[31:27])
      5'h00:
          required_perms = { 2'h0, \$62  };
      5'h01:
          required_perms = 6'h00;
      5'h02:
          (* full_case = 32'd1 *)
          if (\$65 ) begin
            required_perms = 6'h00;
          end else begin
            required_perms = 6'h20;
          end
      5'h05:
          required_perms = 6'h08;
      5'h04:
          required_perms = 6'h00;
      5'h07:
          required_perms = 6'h04;
      5'h08:
          required_perms = 6'h00;
      5'h09:
          required_perms = 6'h00;
      default:
          required_perms = 6'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    clist_addr = 32'd0;
    if (mint_clist_wr_en) begin
      clist_addr = mint_clist_addr_d;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    clist_wr_data = cr_rd_data[31:0];
    if (mint_clist_wr_en) begin
      clist_wr_data = mint_clist_wr_data_d;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    clist_wr_en = 1'h0;
    if (mint_clist_wr_en) begin
      clist_wr_en = 1'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    flags_in = 4'h0;
    if (dr_wr_en) begin
    end else if (iadd_start_sig) begin
      flags_in = iadd_flags_sig;
    end else if (isub_start_sig) begin
      flags_in = isub_flags_sig;
    end else if (shl_start_sig) begin
      flags_in = shl_flags_sig;
    end else if (shr_start_sig) begin
      flags_in = shr_flags_sig;
    end else if (bfext_start_sig) begin
      flags_in = bfext_flags_sig;
    end else if (bfins_start_sig) begin
      flags_in = bfins_flags_sig;
    end else if (mcmp_start_sig) begin
      flags_in = mcmp_flags_sig;
    end else if (tperm_complete) begin
      flags_in = tperm_flags_sig;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    flags_wr_en = 1'h0;
    if (dr_wr_en) begin
    end else if (iadd_start_sig) begin
      flags_wr_en = 1'h1;
    end else if (isub_start_sig) begin
      flags_wr_en = 1'h1;
    end else if (shl_start_sig) begin
      flags_wr_en = 1'h1;
    end else if (shr_start_sig) begin
      flags_wr_en = 1'h1;
    end else if (bfext_start_sig) begin
      flags_wr_en = 1'h1;
    end else if (bfins_start_sig) begin
      flags_wr_en = 1'h1;
    end else if (mcmp_start_sig) begin
      flags_wr_en = 1'h1;
    end else if (tperm_complete) begin
      flags_wr_en = 1'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    dr_wr_addr = 4'h0;
    (* full_case = 32'd1 *)
    if (dr_wr_en) begin
      dr_wr_addr = \dr_wr_addr$104 ;
    end else if (iadd_start_sig) begin
      dr_wr_addr = instruction[22:19];
    end else if (isub_start_sig) begin
      dr_wr_addr = instruction[22:19];
    end else if (shl_start_sig) begin
      dr_wr_addr = instruction[22:19];
    end else if (shr_start_sig) begin
      dr_wr_addr = instruction[22:19];
    end else if (bfext_start_sig) begin
      dr_wr_addr = instruction[22:19];
    end else if (bfins_start_sig) begin
      dr_wr_addr = instruction[22:19];
    end else if (mcmp_start_sig) begin
      dr_wr_addr = 4'h0;
    end else if (tperm_complete) begin
    end else begin
      dr_wr_addr = 4'h0;
    end
    if (\dr_wr_en$123 ) begin
      dr_wr_addr = 4'h0;
    end
    if (dr1_wr_en) begin
      dr_wr_addr = 4'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    dr_wr_data = 32'd0;
    (* full_case = 32'd1 *)
    if (dr_wr_en) begin
      dr_wr_data = \dr_wr_data$106 ;
    end else if (iadd_start_sig) begin
      dr_wr_data = iadd_result[31:0];
    end else if (isub_start_sig) begin
      dr_wr_data = isub_result[31:0];
    end else if (shl_start_sig) begin
      dr_wr_data = \$168 [31:0];
    end else if (shr_start_sig) begin
      dr_wr_data = shr_result;
    end else if (bfext_start_sig) begin
      dr_wr_data = bfext_result;
    end else if (bfins_start_sig) begin
      dr_wr_data = \$191 [31:0];
    end else if (mcmp_start_sig) begin
      dr_wr_data = 32'd0;
    end else if (tperm_complete) begin
    end else begin
      dr_wr_data = 32'd0;
    end
    if (\dr_wr_en$123 ) begin
      dr_wr_data = { 30'h00000000, \$407  };
    end
    if (dr1_wr_en) begin
      dr_wr_data = { 16'h0000, \$408  };
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \dr_wr_en$107  = 1'h0;
    (* full_case = 32'd1 *)
    if (dr_wr_en) begin
      \dr_wr_en$107  = 1'h1;
    end else if (iadd_start_sig) begin
      \dr_wr_en$107  = 1'h1;
    end else if (isub_start_sig) begin
      \dr_wr_en$107  = 1'h1;
    end else if (shl_start_sig) begin
      \dr_wr_en$107  = 1'h1;
    end else if (shr_start_sig) begin
      \dr_wr_en$107  = 1'h1;
    end else if (bfext_start_sig) begin
      \dr_wr_en$107  = 1'h1;
    end else if (bfins_start_sig) begin
      \dr_wr_en$107  = 1'h1;
    end else if (mcmp_start_sig) begin
      \dr_wr_en$107  = 1'h0;
    end else if (tperm_complete) begin
    end else begin
      \dr_wr_en$107  = 1'h0;
    end
    if (\dr_wr_en$123 ) begin
      \dr_wr_en$107  = 1'h1;
    end
    if (dr1_wr_en) begin
      \dr_wr_en$107  = 1'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    tperm_flags_sig = 4'h0;
    if (dr_wr_en) begin
    end else if (iadd_start_sig) begin
    end else if (isub_start_sig) begin
    end else if (shl_start_sig) begin
    end else if (shr_start_sig) begin
    end else if (bfext_start_sig) begin
    end else if (bfins_start_sig) begin
    end else if (mcmp_start_sig) begin
    end else if (tperm_complete) begin
      tperm_flags_sig[1] = tperm_z_result;
      tperm_flags_sig[0] = \$68 ;
      tperm_flags_sig[2] = 1'h0;
      tperm_flags_sig[3] = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    boot_cap_wr_en = 1'h0;
    casez (boot_state)
      3'h2:
          boot_cap_wr_en = 1'h1;
      3'h3:
          /* empty */;
      3'h4:
          boot_cap_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    boot_cap_wr_addr = 4'h0;
    casez (boot_state)
      3'h2:
          boot_cap_wr_addr = 4'hf;
      3'h3:
          /* empty */;
      3'h4:
          boot_cap_wr_addr = 4'h6;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    boot_cap_wr_data = 96'h000000000000000000000000;
    casez (boot_state)
      3'h2:
          boot_cap_wr_data = 96'h000000120000000002000000;
      3'h3:
          /* empty */;
      3'h4:
          boot_cap_wr_data = 96'h0000003f000004004a000002;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    thrd_gt[30:0] = 31'h00000000;
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
        begin
          thrd_gt[15:0] = 16'h0001;
          thrd_gt[24:16] = 9'h000;
          thrd_gt[26:25] = 2'h1;
          thrd_gt[27] = 1'h0;
          thrd_gt[30:28] = 3'h0;
        end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    boot_cap8_wr_en = 1'h0;
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
          boot_cap8_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    boot_cap8_wr_gt = 32'd0;
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
          boot_cap8_wr_gt = thrd_gt;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    cr14_gt[30:0] = 31'h00000000;
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
        begin
          cr14_gt[15:0] = 16'h0003;
          cr14_gt[24:16] = 9'h000;
          cr14_gt[26:25] = 2'h1;
          cr14_gt[27] = 1'h0;
          cr14_gt[30:28] = 3'h4;
        end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    boot_cap14_wr_en = 1'h0;
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
          boot_cap14_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    boot_cap14_wr_gt = 32'd0;
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
          boot_cap14_wr_gt = cr14_gt;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap8_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$113 ) begin
        rt_cap8_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap8_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$113 ) begin
        rt_cap8_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap9_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$114 ) begin
        rt_cap9_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap9_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$114 ) begin
        rt_cap9_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap10_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$115 ) begin
        rt_cap10_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap10_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$115 ) begin
        rt_cap10_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap11_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$116 ) begin
        rt_cap11_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap11_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$116 ) begin
        rt_cap11_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap12_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$117 ) begin
        rt_cap12_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap12_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$117 ) begin
        rt_cap12_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap13_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$118 ) begin
        rt_cap13_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap13_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$118 ) begin
        rt_cap13_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap14_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$119 ) begin
        rt_cap14_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap14_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$119 ) begin
        rt_cap14_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap15_wr_en = 1'h0;
    if (switch_change_active) begin
      if (\$120 ) begin
        rt_cap15_wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    rt_cap15_wr_gt = 32'd0;
    if (switch_change_active) begin
      if (\$120 ) begin
        rt_cap15_wr_gt = cr_rd_data[31:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_dmem_rd_en = 1'h0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          mint_dmem_rd_en = 1'h1;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          (* full_case = 32'd1 *)
          if (\$256 ) begin
          end else begin
            mint_dmem_rd_en = 1'h1;
          end
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          (* full_case = 32'd1 *)
          if (\$262 ) begin
          end else begin
            mint_dmem_rd_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_dmem_addr = 32'd0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          mint_dmem_addr = mint_base_reg_ni;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          (* full_case = 32'd1 *)
          if (\$256 ) begin
          end else begin
            mint_dmem_addr = \$258 [31:0];
          end
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          (* full_case = 32'd1 *)
          if (\$262 ) begin
          end else begin
            mint_dmem_addr = \$265 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    lsz_c_ni = 15'h0000;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          lsz_c_ni = \$253 [14:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    scan_end_c_ni = 15'h0000;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          scan_end_c_ni = \$255 [14:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_ns_wr_en = 1'h0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          mint_ns_wr_en = 1'h1;
      4'h7:
          mint_ns_wr_en = 1'h1;
      4'h8:
          mint_ns_wr_en = 1'h1;
      4'h9:
          mint_ns_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_ns_addr = 32'd0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          mint_ns_addr = \$247 [31:0];
      4'h7:
          mint_ns_addr = \$259 [31:0];
      4'h8:
          mint_ns_addr = \$260 [31:0];
      4'h9:
          mint_ns_addr = \$261 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_ns_wr_data = 32'd0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          mint_ns_wr_data = mint_base_reg_ni;
      4'h7:
          mint_ns_wr_data = { 10'h000, \$250  };
      4'h8:
          mint_ns_wr_data = mint_integrity_ni;
      4'h9:
          mint_ns_wr_data = 32'd0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    cc_off_ni = 15'h0000;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          (* full_case = 32'd1 *)
          if (\$262 ) begin
          end else begin
            cc_off_ni = \$263 [14:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_clist_wr_en = 1'h0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          /* empty */;
      4'hd:
          mint_clist_wr_en = 1'h1;
      4'hb:
          mint_clist_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_clist_addr_d = 32'd0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          /* empty */;
      4'hd:
          mint_clist_addr_d = \$267 [31:0];
      4'hb:
          mint_clist_addr_d = mint_clist_addr_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_clist_wr_data_d = 32'd0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          /* empty */;
      4'hd:
          mint_clist_wr_data_d = mint_copy_data_reg_ni;
      4'hb:
          mint_clist_wr_data_d = { 1'h0, \$248  };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_done_comb_ni = 1'h0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          /* empty */;
      4'hd:
          /* empty */;
      4'hb:
          /* empty */;
      4'he:
          mint_done_comb_ni = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_result_gt = 32'd0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          /* empty */;
      4'hd:
          /* empty */;
      4'hb:
          /* empty */;
      4'he:
          mint_result_gt = { 1'h0, \$248  };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mint_fault_comb_ni = 1'h0;
    casez (mint_noniot_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hc:
          /* empty */;
      4'hd:
          /* empty */;
      4'hb:
          /* empty */;
      4'he:
          /* empty */;
      4'h4:
          mint_fault_comb_ni = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mwin_busy = 1'h0;
    casez (mwin_state)
      2'h0:
          mwin_busy = 1'h0;
      2'h1:
          mwin_busy = 1'h1;
      2'h2:
          mwin_busy = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mwin_cr_wr_en = 1'h0;
    casez (mwin_state)
      2'h0:
          mwin_cr_wr_en = 1'h0;
      2'h1:
          (* full_case = 32'd1 *)
          if (\$274 ) begin
            mwin_cr_wr_en = 1'h1;
          end else begin
            mwin_cr_wr_en = 1'h0;
          end
      2'h2:
          mwin_cr_wr_en = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mwin_cr_wr_data = 96'h000000000000000000000000;
    casez (mwin_state)
      2'h0:
          mwin_cr_wr_data = 96'h000000000000000000000000;
      2'h1:
          if (\$274 ) begin
            mwin_cr_wr_data[31:0] = mwin_dr11_lat;
            mwin_cr_wr_data[63:32] = mwin_dr12_lat;
            mwin_cr_wr_data[95:64] = mwin_dr13_lat;
          end
      2'h2:
          mwin_cr_wr_data = 96'h000000000000000000000000;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    m_set_en = 1'h0;
    casez (mwin_state)
      2'h0:
          m_set_en = \$272 ;
      2'h1:
          (* full_case = 32'd1 *)
          if (\$274 ) begin
            m_set_en = 1'h0;
          end else begin
            m_set_en = 1'h0;
          end
      2'h2:
          m_set_en = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    m_clear_en = 1'h0;
    casez (mwin_state)
      2'h0:
          m_clear_en = 1'h0;
      2'h1:
          (* full_case = 32'd1 *)
          if (\$274 ) begin
            m_clear_en = 1'h1;
          end else begin
            m_clear_en = 1'h1;
          end
      2'h2:
          m_clear_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    mwin_fault_valid = 1'h0;
    casez (mwin_state)
      2'h0:
          mwin_fault_valid = 1'h0;
      2'h1:
          (* full_case = 32'd1 *)
          if (\$274 ) begin
            mwin_fault_valid = 1'h0;
          end else begin
            mwin_fault_valid = 1'h1;
          end
      2'h2:
          mwin_fault_valid = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    if (fetch_bounds_fault) begin
      \fault$639  = 5'h08;
    end else if (fault_valid) begin
      \fault$639  = { 1'h0, \fault$641  };
    end else if (\fault_valid$624 ) begin
      \fault$639  = { 1'h0, fault_type };
    end else if (lambda_fault) begin
      \fault$639  = { 1'h0, \fault_type$643  };
    end else if (nested_lambda_fault) begin
      \fault$639  = 5'h0b;
    end else if (tperm_fault) begin
      \fault$639  = { 1'h0, \fault_type$644  };
    end else if (call_fault) begin
      \fault$639  = \fault_type$645 ;
    end else if (\fault_valid$628 ) begin
      \fault$639  = \fault_type$646 ;
    end else if (save_fault) begin
      \fault$639  = { 1'h0, \fault_type$647  };
    end else if (load_fault) begin
      \fault$639  = \fault_type$648 ;
    end else if (change_fault) begin
      \fault$639  = \fault_type$649 ;
    end else if (switch_fault) begin
      \fault$639  = { 1'h0, \fault_type$650  };
    end else if (fault) begin
      \fault$639  = { 1'h0, \fault_type$651  };
    end else if (\fault$634 ) begin
      \fault$639  = { 1'h0, \fault_type$652  };
    end else if (\fault$635 ) begin
      \fault$639  = \fault_type$653 ;
    end else if (\fault$636 ) begin
      \fault$639  = \fault_type$654 ;
    end else if (cload_fault) begin
      \fault$639  = cload_fault_type;
    end else if (\$283 ) begin
      \fault$639  = outform_fault_type_in;
    end else if (\fault$638 ) begin
      \fault$639  = \fault_type$656 ;
    end else if (mwin_fault_valid) begin
      \fault$639  = 5'h0b;
    end else begin
      \fault$639  = 5'h00;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    if (fetch_bounds_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (fault_valid) begin
      \fault_valid$640  = 1'h1;
    end else if (\fault_valid$624 ) begin
      \fault_valid$640  = 1'h1;
    end else if (lambda_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (nested_lambda_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (tperm_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (call_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (\fault_valid$628 ) begin
      \fault_valid$640  = 1'h1;
    end else if (save_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (load_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (change_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (switch_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (fault) begin
      \fault_valid$640  = 1'h1;
    end else if (\fault$634 ) begin
      \fault_valid$640  = 1'h1;
    end else if (\fault$635 ) begin
      \fault_valid$640  = 1'h1;
    end else if (\fault$636 ) begin
      \fault_valid$640  = 1'h1;
    end else if (cload_fault) begin
      \fault_valid$640  = 1'h1;
    end else if (\$283 ) begin
      \fault_valid$640  = 1'h1;
    end else if (\fault$638 ) begin
      \fault_valid$640  = 1'h1;
    end else if (mwin_fault_valid) begin
      \fault_valid$640  = 1'h1;
    end else begin
      \fault_valid$640  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    if (fetch_bounds_fault) begin
      fault_stage_w = 4'h0;
    end else if (fault_valid) begin
      fault_stage_w = 4'h1;
    end else if (\fault_valid$624 ) begin
      fault_stage_w = 4'h2;
    end else if (lambda_fault) begin
      fault_stage_w = 4'h3;
    end else if (nested_lambda_fault) begin
      fault_stage_w = 4'h3;
    end else if (tperm_fault) begin
      fault_stage_w = 4'h4;
    end else if (call_fault) begin
      fault_stage_w = 4'h5;
    end else if (\fault_valid$628 ) begin
      fault_stage_w = 4'h6;
    end else begin
      fault_stage_w = 4'h7;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    sub_start = 1'h0;
    if (call_busy) begin
      sub_start = mload_start;
    end else if (busy) begin
      sub_start = 1'h0;
    end else if (load_busy) begin
      sub_start = \mload_start$689 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    sub_cr_src = 4'h0;
    if (call_busy) begin
      sub_cr_src = mload_cr_src;
    end else if (busy) begin
      sub_cr_src = 4'h0;
    end else if (load_busy) begin
      sub_cr_src = instruction[18:15];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    sub_cr_dst = 4'h0;
    if (call_busy) begin
      sub_cr_dst = mload_cr_dst;
    end else if (busy) begin
      sub_cr_dst = 4'h0;
    end else if (load_busy) begin
      sub_cr_dst = instruction[22:19];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    sub_index = 16'h0000;
    if (call_busy) begin
      sub_index = mload_index;
    end else if (busy) begin
      sub_index = 16'h0000;
    end else if (load_busy) begin
      sub_index = { 1'h0, instruction[14:0] };
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    sub_direct = 1'h0;
    if (call_busy) begin
      sub_direct = 1'h0;
    end else if (busy) begin
      sub_direct = 1'h0;
    end else if (load_busy) begin
      sub_direct = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    sub_direct_gt = 32'd0;
    if (call_busy) begin
      sub_direct_gt = 32'd0;
    end else if (busy) begin
      sub_direct_gt = 32'd0;
    end else if (load_busy) begin
      sub_direct_gt = 32'd0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    sub_m_elevated = 1'h0;
    if (call_busy) begin
      sub_m_elevated = 1'h1;
    end else if (busy) begin
      sub_m_elevated = 1'h0;
    end else if (load_busy) begin
      sub_m_elevated = \mload_m_elevated$695 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    dmem_addr = 32'd0;
    if (\$284 ) begin
      dmem_addr = mem_addr;
    end else if (\mem_rd_en$715 ) begin
      dmem_addr = mem_rd_addr;
    end else if (\mem_wr_en$716 ) begin
      dmem_addr = mem_wr_addr;
    end else if (\mem_wr_en$717 ) begin
      dmem_addr = \mem_wr_addr$731 ;
    end else if (\mem_rd_en$718 ) begin
      dmem_addr = \mem_rd_addr$733 ;
    end else if (\dmem_rd_en$719 ) begin
      dmem_addr = \dmem_addr$734 ;
    end else if (\dmem_wr_en$720 ) begin
      (* full_case = 32'd1 *)
      if (\$285 ) begin
      end else begin
        dmem_addr = \dmem_addr$735 ;
      end
    end else if (\mem_rd_en$721 ) begin
      dmem_addr = \mem_addr$740 ;
    end else if (\mem_wr_en$722 ) begin
      dmem_addr = \mem_wr_addr$741 ;
    end else if (mint_dmem_rd_en) begin
      dmem_addr = mint_dmem_addr;
    end else if (\mem_rd_en$723 ) begin
      dmem_addr = \mem_rd_addr$743 ;
    end else if (\mem_wr_en$724 ) begin
      dmem_addr = \mem_wr_addr$744 ;
    end else if (\mem_rd_en$725 ) begin
      dmem_addr = \mem_rd_addr$746 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    dmem_rd_en = 1'h0;
    if (\$284 ) begin
      dmem_rd_en = mem_rd_en;
    end else if (\mem_rd_en$715 ) begin
      dmem_rd_en = 1'h1;
    end else if (\mem_wr_en$716 ) begin
    end else if (\mem_wr_en$717 ) begin
    end else if (\mem_rd_en$718 ) begin
      dmem_rd_en = 1'h1;
    end else if (\dmem_rd_en$719 ) begin
      dmem_rd_en = 1'h1;
    end else if (\dmem_wr_en$720 ) begin
    end else if (\mem_rd_en$721 ) begin
      dmem_rd_en = 1'h1;
    end else if (\mem_wr_en$722 ) begin
    end else if (mint_dmem_rd_en) begin
      dmem_rd_en = 1'h1;
    end else if (\mem_rd_en$723 ) begin
      dmem_rd_en = 1'h1;
    end else if (\mem_wr_en$724 ) begin
    end else if (\mem_rd_en$725 ) begin
      dmem_rd_en = 1'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    dmem_wr_data = 32'd0;
    if (\$284 ) begin
      dmem_wr_data = mem_wr_data;
    end else if (\mem_rd_en$715 ) begin
    end else if (\mem_wr_en$716 ) begin
      dmem_wr_data = \mem_wr_data$730 ;
    end else if (\mem_wr_en$717 ) begin
      dmem_wr_data = \mem_wr_data$732 ;
    end else if (\mem_rd_en$718 ) begin
    end else if (\dmem_rd_en$719 ) begin
    end else if (\dmem_wr_en$720 ) begin
      (* full_case = 32'd1 *)
      if (\$285 ) begin
      end else begin
        dmem_wr_data = \dmem_wr_data$738 ;
      end
    end else if (\mem_rd_en$721 ) begin
    end else if (\mem_wr_en$722 ) begin
      dmem_wr_data = \mem_wr_data$742 ;
    end else if (mint_dmem_rd_en) begin
    end else if (\mem_rd_en$723 ) begin
    end else if (\mem_wr_en$724 ) begin
      dmem_wr_data = \mem_wr_data$745 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    dmem_wr_en = 1'h0;
    if (\$284 ) begin
      dmem_wr_en = mem_wr_en;
    end else if (\mem_rd_en$715 ) begin
    end else if (\mem_wr_en$716 ) begin
      dmem_wr_en = 1'h1;
    end else if (\mem_wr_en$717 ) begin
      dmem_wr_en = 1'h1;
    end else if (\mem_rd_en$718 ) begin
    end else if (\dmem_rd_en$719 ) begin
    end else if (\dmem_wr_en$720 ) begin
      (* full_case = 32'd1 *)
      if (\$285 ) begin
      end else begin
        dmem_wr_en = 1'h1;
      end
    end else if (\mem_rd_en$721 ) begin
    end else if (\mem_wr_en$722 ) begin
      dmem_wr_en = 1'h1;
    end else if (mint_dmem_rd_en) begin
    end else if (\mem_rd_en$723 ) begin
    end else if (\mem_wr_en$724 ) begin
      dmem_wr_en = 1'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    wr_en = 1'h0;
    if (\$284 ) begin
    end else if (\mem_rd_en$715 ) begin
    end else if (\mem_wr_en$716 ) begin
    end else if (\mem_wr_en$717 ) begin
    end else if (\mem_rd_en$718 ) begin
    end else if (\dmem_rd_en$719 ) begin
    end else if (\dmem_wr_en$720 ) begin
      if (\$285 ) begin
        wr_en = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    wr_addr = 6'h00;
    if (\$284 ) begin
    end else if (\mem_rd_en$715 ) begin
    end else if (\mem_wr_en$716 ) begin
    end else if (\mem_wr_en$717 ) begin
    end else if (\mem_rd_en$718 ) begin
    end else if (\dmem_rd_en$719 ) begin
    end else if (\dmem_wr_en$720 ) begin
      if (\$285 ) begin
        wr_addr = \dmem_wr_data$738 [5:0];
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    wr_data = 1'h0;
    if (\$284 ) begin
    end else if (\mem_rd_en$715 ) begin
    end else if (\mem_wr_en$716 ) begin
    end else if (\mem_wr_en$717 ) begin
    end else if (\mem_rd_en$718 ) begin
    end else if (\dmem_rd_en$719 ) begin
    end else if (\dmem_wr_en$720 ) begin
      if (\$285 ) begin
        wr_data = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    if (mint_ns_wr_en) begin
      ns_addr = mint_ns_addr;
    end else if (gc_busy) begin
      ns_addr = \ns_addr$754 ;
    end else begin
      ns_addr = 32'd0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    if (mint_ns_wr_en) begin
      ns_rd_en = 1'h0;
    end else if (gc_busy) begin
      ns_rd_en = \ns_rd_en$755 ;
    end else begin
      ns_rd_en = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    if (mint_ns_wr_en) begin
      ns_wr_data = { 64'h0000000000000000, mint_ns_wr_data };
    end else if (gc_busy) begin
      ns_wr_data = \ns_wr_data$756 ;
    end else begin
      ns_wr_data = 96'h000000000000000000000000;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    (* full_case = 32'd1 *)
    if (mint_ns_wr_en) begin
      ns_wr_en = 1'h1;
    end else if (gc_busy) begin
      ns_wr_en = \ns_wr_en$757 ;
    end else begin
      ns_wr_en = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$376  = boot_state;
    casez (boot_state)
      3'h0:
          if (boot_start) begin
            \$376  = 3'h1;
          end
      3'h1:
          \$376  = 3'h2;
      3'h2:
          \$376  = 3'h3;
      3'h3:
          \$376  = 3'h4;
      3'h4:
          \$376  = 3'h5;
      3'h5:
          \$376  = 3'h6;
      3'h6:
          \$376  = 3'h6;
    endcase
    if (\$305 ) begin
      \$376  = 3'h1;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$377  = imem_addr;
    if (\$305 ) begin
      \$377  = 32'd0;
    end else if (clear_all) begin
      \$377  = 32'd0;
    end else if (free_run_start) begin
      \$377  = free_run_nia;
    end else if (nia_set) begin
      \$377  = nia_value;
    end else if (\nia_set$763 ) begin
      \$377  = \nia_value$770 ;
    end else if (\nia_set$764 ) begin
      \$377  = \nia_value$771 ;
    end else if (call_normal_complete) begin
      \$377  = \nia_value$772 ;
    end else if (\nia_set$766 ) begin
      \$377  = \nia_value$773 ;
    end else if (\nia_set$767 ) begin
      \$377  = \nia_value$774 ;
    end else if (\$307 ) begin
      \$377  = \$315 [31:0];
    end else if (\$314 ) begin
      \$377  = \$316 [31:0];
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$378  = code_lo_reg;
    if (\$317 ) begin
      \$378  = 32'd0;
    end else if (\$318 ) begin
    end else if (\$320 ) begin
      \$378  = 32'd0;
    end else if (\$322 ) begin
      \$378  = \cr_wr_data$155 [63:32];
    end else if (\$325 ) begin
      \$378  = 32'd0;
    end else if (call_normal_complete) begin
      \$378  = code_lo_out;
    end
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
          \$378  = 32'd0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$379  = code_hi_reg;
    if (\$317 ) begin
      \$379  = 32'd0;
    end else if (\$318 ) begin
    end else if (\$320 ) begin
      \$379  = 32'd0;
    end else if (\$322 ) begin
      \$379  = \$328 [31:0];
    end else if (\$325 ) begin
      \$379  = 32'd0;
    end else if (call_normal_complete) begin
      \$379  = code_hi_out;
    end
    casez (boot_state)
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
          \$379  = 32'd1020;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$380  = fence_pending_reg;
    if (\$317 ) begin
      \$380  = 1'h0;
    end else if (\$318 ) begin
      \$380  = 1'h1;
    end else if (\$320 ) begin
    end else if (\$322 ) begin
      \$380  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$381  = cross_domain_ret;
    if (ret_start_sig) begin
      \$381  = \$329 ;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$382  = cload_pending;
    if (\$334 ) begin
      \$382  = 1'h1;
    end else if (cload_pending) begin
      \$382  = 1'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$43 ) begin end
    \$383  = lambda_active_reg;
    if (clear_all) begin
      \$383  = 1'h0;
    end else if (lambda_clear) begin
      \$383  = 1'h0;
    end else if (\$336 ) begin
      \$383  = 1'h0;
    end else if (\$338 ) begin
      \$383  = 1'h1;
    end
  end
  assign boot_state_reg = boot_state;
  assign imem_data = instruction;
  assign \flags$9  = flags;
  assign church_op = instruction[31:27];
  assign cr_dst = instruction[22:19];
  assign cr_src = instruction[18:15];
  assign perm_gt_sig = cr_rd_data[31:0];
  assign gt_in = cr_rd_data[31:0];
  assign \required_perms$69  = required_perms;
  assign gc_start = 1'h0;
  assign \gc_start$73  = 1'h0;
  assign gc_mark_en = 1'h1;
  assign gc_sweep_en = 1'h1;
  assign ns_start_index = 16'h0001;
  assign ns_end_index = 16'h1000;
  assign ns_rd_data = { 64'h0000000000000000, \port$4577$0  };
  assign \ns_rd_data$79  = { 64'h0000000000000000, \port$4577$0  };
  assign \gc_busy$80  = gc_busy;
  assign garbage_count = gc_garbage_count;
  assign cr_rd_data_gt = cr_rd_data[31:0];
  assign clist_rd_en = 1'h0;
  assign \clear_all$93  = clear_all;
  assign shl_result = \$168 [31:0];
  assign bfins_result = \$191 [31:0];
  assign \dr_wr_addr$124  = 4'h0;
  assign \dr_wr_data$125  = { 30'h00000000, \$407  };
  assign dr1_wr_data = { 16'h0000, \$408  };
  assign \cr_wr_en$134  = 1'h0;
  assign dbg_cr_wr_en = 1'h0;
  assign dbg_cr_wr_addr = 4'h0;
  assign \cr_wr_addr$145  = 4'h0;
  assign dbg_cr_wr_data = 96'h000000000000000000000000;
  assign \cr_wr_data$158  = 96'h000000000000000000000000;
  assign mwin_m_set_en = m_set_en;
  assign mwin_m_clear_en = m_clear_en;
  assign \cr15_m_flag$174  = cr15_m_flag;
  assign m_dr11 = dbg_m_dr11;
  assign m_dr12 = dbg_m_dr12;
  assign m_dr13 = dbg_m_dr13;
  assign m_dr14 = dbg_m_dr14;
  assign m_dr15 = dbg_m_dr15;
  assign \m_flag_restore_en$186  = m_flag_restore_en;
  assign \m_flag_restore_val$188  = m_flag_restore_val;
  assign w0_rot = { cr15_namespace[56:32], cr15_namespace[63:57] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign nia_reg = imem_addr;
  assign nia = imem_addr;
  assign \flags$208  = flags;
  assign switch_src_gt = cr_rd_data[31:0];
  assign switch_target = instruction[3:0];
  assign boot_cap0_wr_en = 1'h0;
  assign rt_cap0_wr_en = 1'h0;
  assign rt_cap0_wr_gt = 32'd0;
  assign boot_cap0_wr_gt = 32'd0;
  assign boot_cap1_wr_en = 1'h0;
  assign rt_cap1_wr_en = 1'h0;
  assign rt_cap1_wr_gt = 32'd0;
  assign boot_cap1_wr_gt = 32'd0;
  assign boot_cap2_wr_en = 1'h0;
  assign rt_cap2_wr_en = 1'h0;
  assign rt_cap2_wr_gt = 32'd0;
  assign boot_cap2_wr_gt = 32'd0;
  assign boot_cap3_wr_en = 1'h0;
  assign rt_cap3_wr_en = 1'h0;
  assign rt_cap3_wr_gt = 32'd0;
  assign boot_cap3_wr_gt = 32'd0;
  assign boot_cap4_wr_en = 1'h0;
  assign rt_cap4_wr_en = 1'h0;
  assign rt_cap4_wr_gt = 32'd0;
  assign boot_cap4_wr_gt = 32'd0;
  assign boot_cap5_wr_en = 1'h0;
  assign rt_cap5_wr_en = 1'h0;
  assign rt_cap5_wr_gt = 32'd0;
  assign boot_cap5_wr_gt = 32'd0;
  assign boot_cap6_wr_en = 1'h0;
  assign rt_cap6_wr_en = 1'h0;
  assign rt_cap6_wr_gt = 32'd0;
  assign boot_cap6_wr_gt = 32'd0;
  assign boot_cap7_wr_en = 1'h0;
  assign rt_cap7_wr_en = 1'h0;
  assign rt_cap7_wr_gt = 32'd0;
  assign boot_cap7_wr_gt = 32'd0;
  assign boot_cap9_wr_en = 1'h0;
  assign boot_cap9_wr_gt = 32'd0;
  assign boot_cap10_wr_en = 1'h0;
  assign boot_cap10_wr_gt = 32'd0;
  assign boot_cap11_wr_en = 1'h0;
  assign boot_cap11_wr_gt = 32'd0;
  assign boot_cap12_wr_en = 1'h0;
  assign boot_cap12_wr_gt = 32'd0;
  assign boot_cap13_wr_en = 1'h0;
  assign boot_cap13_wr_gt = 32'd0;
  assign boot_cap15_wr_en = 1'h0;
  assign boot_cap15_wr_gt = 32'd0;
  assign src_cr = instruction[18:15];
  assign src_cr_data = cr_rd_data;
  assign call_start = call_start_sig;
  assign \cr_src$317  = instruction[18:15];
  assign index = 16'h0000;
  assign call_imm = instruction[14:0];
  assign \call_imm$320  = instruction[14:0];
  assign mask = 16'h0000;
  assign call_mask = 15'h0000;
  assign \cr_rd_data$323  = cr_rd_data;
  assign \cr15_namespace$324  = cr15_namespace;
  assign \cr14_code$326  = cr14_code;
  assign dmem_rd_data = mem_rd_data;
  assign dmem_rd_valid = mem_rd_valid;
  assign \cr5_heap$332  = cr5_heap;
  assign caller_pc = imem_addr[16:2];
  assign \cr12_thread$335  = cr12_thread;
  assign thread_base = cr12_thread[63:32];
  assign thread_hdr_out = thread_hdr;
  assign \cr_b_clear_mask$340  = cr_b_clear_mask;
  assign \cr_null_mask$342  = cr_null_mask;
  assign return_start = ret_start_sig;
  assign \cr_src$345  = instruction[17:15];
  assign \cr_rd_data$346  = cr_rd_data;
  assign lambda_active = lambda_active_reg;
  assign lambda_pc_reg = lambda_pc;
  assign \cr5_heap$350  = cr5_heap;
  assign \cr12_thread$351  = cr12_thread;
  assign \mem_rd_data$352  = mem_rd_data;
  assign \mem_rd_valid$353  = mem_rd_valid;
  assign cload_start = cload_pending;
  assign cload_e_gt = e_gt;
  assign \cr15_namespace$357  = cr15_namespace;
  assign \mem_rd_data$358  = mem_rd_data;
  assign \mem_rd_valid$359  = mem_rd_valid;
  assign lambda_start = lambda_start_sig;
  assign cr_target = instruction[22:19];
  assign \cr_rd_data$362  = cr_rd_data;
  assign saved_nia = \$136 [31:0];
  assign tperm_start = tperm_start_sig;
  assign \cr_target$366  = instruction[22:19];
  assign \cr_src$367  = instruction[18:15];
  assign preset = instruction[3:0];
  assign tperm_preset = instruction[3:0];
  assign \cr_rd_data$370  = cr_rd_data;
  assign stack_has_frame = 1'h0;
  assign save_start = save_start_sig;
  assign \cr_src$374  = instruction[18:15];
  assign \cr_dst$375  = instruction[22:19];
  assign \index$376  = { 1'h0, instruction[14:0] };
  assign cap_index = instruction[14:0];
  assign \cr_rd_data$378  = cr_rd_data;
  assign \cr15_namespace$379  = cr15_namespace;
  assign mem_wr_done = 1'h1;
  assign \mem_rd_data$381  = mem_rd_data;
  assign \mem_rd_valid$382  = mem_rd_valid;
  assign start = dread_start_sig;
  assign \cr_src$386  = instruction[18:15];
  assign dr_dst = instruction[22:19];
  assign imm = instruction[14:0];
  assign immediate = instruction[14:0];
  assign \cr_rd_data$390  = cr_rd_data;
  assign \dmem_rd_data$391  = mem_rd_data;
  assign dr_rd_data1 = dr_rd_data;
  assign \start$396  = dwrite_start_sig;
  assign \cr_src$397  = instruction[18:15];
  assign dr_src = instruction[22:19];
  assign \imm$399  = instruction[14:0];
  assign \cr_rd_data$400  = cr_rd_data;
  assign dr_rd_data2 = \dr_rd_data$401 ;
  assign \dr_rd_data2$403  = dr_rd_data;
  assign arith_imm_sx = { instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14:0] };
  assign shift_amt = instruction[4:0];
  assign asr_mode = instruction[5];
  assign shr_src_sx = { dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data[31], dr_rd_data };
  assign asr_result = \$169 [31:0];
  assign shr_c_shift = \$170 [4:0];
  assign shl_c_shift = \$171 [5:0];
  assign bf_offset = instruction[4:0];
  assign bf_width = instruction[9:5];
  assign bf_mask = \$181 [31:0];
  assign bfins_mask_shifted = \$186 [31:0];
  assign branch_sx32 = { instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14], instruction[14:0] };
  assign load_start = load_start_sig;
  assign \cr_src$436  = instruction[18:15];
  assign \cr_dst$437  = instruction[22:19];
  assign \index$438  = { 1'h0, instruction[14:0] };
  assign change_start = change_start_sig;
  assign \cr_src$441  = instruction[18:15];
  assign \cr_dst$442  = instruction[22:19];
  assign \index$444  = { 1'h0, instruction[14:0] };
  assign change_mask = 16'h0000;
  assign \cr_rd_data$446  = cr_rd_data;
  assign \cr12_thread$447  = cr12_thread;
  assign \cr15_namespace$448  = cr15_namespace;
  assign \mem_rd_data$449  = mem_rd_data;
  assign \mem_rd_valid$450  = mem_rd_valid;
  assign \mem_wr_done$451  = 1'h1;
  assign \dr_rd_data$452  = dr_rd_data;
  assign \nia$453  = imem_addr;
  assign \flags$454  = flags;
  assign cr15_m_flag_in = cr15_m_flag;
  assign switch_start = switch_start_sig;
  assign \cr_src$458  = instruction[17:15];
  assign target = instruction[2:0];
  assign \index$460  = { 1'h0, instruction[14:0] };
  assign \cr_rd_data$461  = cr_rd_data;
  assign \cr15_namespace$462  = cr15_namespace;
  assign \mem_rd_data$463  = mem_rd_data;
  assign \mem_rd_valid$464  = mem_rd_valid;
  assign \start$466  = eloadcall_start_sig;
  assign \cr_src$467  = instruction[18:15];
  assign \cr_dst$468  = instruction[22:19];
  assign \index$469  = { 8'h00, instruction[7:0] };
  assign eloadcall_clist_row = instruction[7:0];
  assign \mask$471  = 16'h0000;
  assign \call_imm$472  = { 8'h00, instruction[14:8] };
  assign eloadcall_method_index = instruction[14:8];
  assign \cr_rd_data$474  = cr_rd_data;
  assign \cr15_namespace$475  = cr15_namespace;
  assign \mem_rd_data$476  = mem_rd_data;
  assign \mem_rd_valid$477  = mem_rd_valid;
  assign \start$479  = xloadlambda_start_sig;
  assign \cr_src$480  = instruction[18:15];
  assign \cr_dst$481  = instruction[22:19];
  assign \index$482  = { 1'h0, instruction[14:0] };
  assign \cr_rd_data$483  = cr_rd_data;
  assign \cr15_namespace$484  = cr15_namespace;
  assign \mem_rd_data$485  = mem_rd_data;
  assign \mem_rd_valid$486  = mem_rd_valid;
  assign rd_data = pet_name_rd_data;
  assign \pet_name_rd_data$492  = pet_name_rd_data;
  assign timer_alarm = 1'h0;
  assign lazy_resolve_slot = pet_name_rd_addr;
  assign \lazy_resolve_slot$499  = \pet_name_rd_addr$489 ;
  assign \start$503  = irq_dispatch_start;
  assign irq_reason = irq_dispatch_reason;
  assign irq_slot = irq_dispatch_slot;
  assign \cr15_namespace$506  = cr15_namespace;
  assign \mem_rd_data$507  = mem_rd_data;
  assign \mem_rd_valid$508  = mem_rd_valid;
  assign \saved_nia$509  = \$226 [31:0];
  assign outform_start_in = 1'h0;
  assign outform_start = _outform_start;
  assign outform_gt_raw_in = 32'd0;
  assign outform_slot_id_in = 16'h0000;
  assign rx_valid = 1'h0;
  assign outform_rx_valid = 1'h0;
  assign rx_data = 8'h00;
  assign outform_rx_data = 8'h00;
  assign tx_valid = outform_tx_valid;
  assign tx_data = outform_tx_data;
  assign result_gt = outform_result_gt;
  assign \outform_busy$533  = outform_busy;
  assign outform_fsm_busy = \busy$35 ;
  assign tx_ack = 1'h0;
  assign outform_tx_ack = 1'h0;
  assign outform_fault_type = outform_fault_type_in;
  assign dbg_outform_done_inject = 1'h0;
  assign \outform_fault_type_in$547  = outform_fault_type_in;
  assign dbg_outform_result_gt = 32'd0;
  assign alloc_sz_w_noniot = \$233 [31:0];
  assign alloc_mask_w_noniot = \$234 [31:0];
  assign alloc_aligned_w_noniot = \$237 [31:0];
  assign alloc_new_wm_w_noniot = \$238 [32:0];
  assign alloc_base = \$245 [31:0];
  assign mint_ns_entry_base_ni = \$247 [31:0];
  assign mint_clist_slot_base_ni = { 7'h00, mint_slot_id_p3_ni, 8'h00 };
  assign mint_e_gt_d = { 1'h0, \$248  };
  assign mint_w2_ni = { 10'h000, \$250  };
  assign \w0_rot$570  = { mint_base_reg_ni[24:0], mint_base_reg_ni[31:25] };
  assign \w1_rot$572  = { \w1_masked$569 [18:0], \w1_masked$569 [31:19] };
  assign mint_done = mint_done_comb_ni;
  assign mint_fault = mint_fault_comb_ni;
  assign cr15_m_writeback_trigger = 1'h0;
  assign \w0_rot$602  = { mwin_dr12_lat[24:0], mwin_dr12_lat[31:25] };
  assign \w1_rot$604  = { \w1_masked$600 [18:0], \w1_masked$600 [31:19] };
  assign mwin_dr11_gt_seq = mwin_dr11_lat[24:16];
  assign mwin_dr13_gt_seq = mwin_dr13_lat[29:21];
  assign mwin_fnv_mul = \$271 [31:0];
  assign mwin_seal_masked = mwin_seal_computed[24:0];
  assign cr15_m_set = 1'h0;
  assign fault_gt = 32'd0;
  assign fault_instr_latch = fault_instr;
  assign fault_cr14 = 32'd0;
  assign fault_stage_latch = fault_stage;
  assign \cr_rd_data$664  = cr_rd_data;
  assign \cr15_namespace$665  = cr15_namespace;
  assign \mem_rd_data$666  = mem_rd_data;
  assign \mem_rd_valid$667  = mem_rd_valid;
  assign mload_direct = 1'h0;
  assign mload_direct_gt = 32'd0;
  assign mload_m_elevated = 1'h1;
  assign \mload_start$682  = 1'h0;
  assign \mload_cr_src$683  = 4'h0;
  assign \mload_cr_dst$684  = 4'h0;
  assign \mload_index$685  = 16'h0000;
  assign \mload_direct$686  = 1'h0;
  assign \mload_direct_gt$687  = 32'd0;
  assign \mload_m_elevated$688  = 1'h0;
  assign \mload_cr_src$690  = instruction[18:15];
  assign \mload_cr_dst$691  = instruction[22:19];
  assign \mload_index$692  = { 1'h0, instruction[14:0] };
  assign \mload_direct$693  = 1'h0;
  assign \mload_direct_gt$694  = 32'd0;
  assign sub_done = mload_done;
  assign sub_fault = mload_fault;
  assign mload_fault_type = \fault_type$648 ;
  assign sub_fault_type = \fault_type$648 ;
  assign \mload_done$702  = mload_done;
  assign \mload_fault$703  = mload_fault;
  assign \mload_fault_type$704  = \fault_type$648 ;
  assign mload_busy = sub_busy;
  assign \mload_done$706  = mload_done;
  assign \mload_fault$707  = mload_fault;
  assign \mload_fault_type$708  = \fault_type$648 ;
  assign gbit_reset_done = valid_key_access;
  assign access_index = 16'h0000;
  
  assign \nia_set$765  = call_normal_complete;
  assign outform_clist_addr_out = 32'd0;
  assign outform_clist_addr_in = 32'd0;
  assign \flags.N  = flags[0];
  assign \flags.Z  = flags[1];
  assign \flags.C  = flags[2];
  assign \flags.V  = flags[3];
  assign \flags$9.N  = flags[0];
  assign \flags$9.Z  = flags[1];
  assign \flags$9.C  = flags[2];
  assign \flags$9.V  = flags[3];
  assign \perm_gt_sig.slot_id  = cr_rd_data[15:0];
  assign \perm_gt_sig.gt_seq  = cr_rd_data[24:16];
  assign \perm_gt_sig.gt_type  = cr_rd_data[26:25];
  assign \perm_gt_sig.dom  = cr_rd_data[27];
  assign \perm_gt_sig.perm  = cr_rd_data[30:28];
  assign \perm_gt_sig.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \gt_in.slot_id  = cr_rd_data[15:0];
  assign \gt_in.gt_seq  = cr_rd_data[24:16];
  assign \gt_in.gt_type  = cr_rd_data[26:25];
  assign \gt_in.dom  = cr_rd_data[27];
  assign \gt_in.perm  = cr_rd_data[30:28];
  assign \gt_in.b_flag  = cr_rd_data[31];
  assign \cr_rd_data_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data_gt.b_flag  = cr_rd_data[31];
  assign \clist_wr_data.slot_id  = clist_wr_data[15:0];
  assign \clist_wr_data.gt_seq  = clist_wr_data[24:16];
  assign \clist_wr_data.gt_type  = clist_wr_data[26:25];
  assign \clist_wr_data.dom  = clist_wr_data[27];
  assign \clist_wr_data.perm  = clist_wr_data[30:28];
  assign \clist_wr_data.b_flag  = clist_wr_data[31];
  assign \flags_in.N  = flags_in[0];
  assign \flags_in.Z  = flags_in[1];
  assign \flags_in.C  = flags_in[2];
  assign \flags_in.V  = flags_in[3];
  assign \iadd_flags_sig.N  = iadd_flags_sig[0];
  assign \iadd_flags_sig.Z  = iadd_flags_sig[1];
  assign \iadd_flags_sig.C  = iadd_flags_sig[2];
  assign \iadd_flags_sig.V  = iadd_flags_sig[3];
  assign \isub_flags_sig.N  = isub_flags_sig[0];
  assign \isub_flags_sig.Z  = isub_flags_sig[1];
  assign \isub_flags_sig.C  = isub_flags_sig[2];
  assign \isub_flags_sig.V  = isub_flags_sig[3];
  assign \shl_flags_sig.N  = shl_flags_sig[0];
  assign \shl_flags_sig.Z  = shl_flags_sig[1];
  assign \shl_flags_sig.C  = shl_flags_sig[2];
  assign \shl_flags_sig.V  = shl_flags_sig[3];
  assign \shr_flags_sig.N  = shr_flags_sig[0];
  assign \shr_flags_sig.Z  = shr_flags_sig[1];
  assign \shr_flags_sig.C  = shr_flags_sig[2];
  assign \shr_flags_sig.V  = shr_flags_sig[3];
  assign \bfext_flags_sig.N  = bfext_flags_sig[0];
  assign \bfext_flags_sig.Z  = bfext_flags_sig[1];
  assign \bfext_flags_sig.C  = bfext_flags_sig[2];
  assign \bfext_flags_sig.V  = bfext_flags_sig[3];
  assign \bfins_flags_sig.N  = bfins_flags_sig[0];
  assign \bfins_flags_sig.Z  = bfins_flags_sig[1];
  assign \bfins_flags_sig.C  = bfins_flags_sig[2];
  assign \bfins_flags_sig.V  = bfins_flags_sig[3];
  assign \mcmp_flags_sig.N  = mcmp_flags_sig[0];
  assign \mcmp_flags_sig.Z  = mcmp_flags_sig[1];
  assign \mcmp_flags_sig.C  = mcmp_flags_sig[2];
  assign \mcmp_flags_sig.V  = mcmp_flags_sig[3];
  assign \tperm_flags_sig.N  = tperm_flags_sig[0];
  assign \tperm_flags_sig.Z  = tperm_flags_sig[1];
  assign \tperm_flags_sig.C  = tperm_flags_sig[2];
  assign \tperm_flags_sig.V  = tperm_flags_sig[3];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_wr_data$151.word0_gt  = \cr_wr_data$151 [31:0];
  assign \cr_wr_data$151.word0_gt.slot_id  = \cr_wr_data$151 [15:0];
  assign \cr_wr_data$151.word0_gt.gt_seq  = \cr_wr_data$151 [24:16];
  assign \cr_wr_data$151.word0_gt.gt_type  = \cr_wr_data$151 [26:25];
  assign \cr_wr_data$151.word0_gt.dom  = \cr_wr_data$151 [27];
  assign \cr_wr_data$151.word0_gt.perm  = \cr_wr_data$151 [30:28];
  assign \cr_wr_data$151.word0_gt.b_flag  = \cr_wr_data$151 [31];
  assign \cr_wr_data$151.word1_location  = \cr_wr_data$151 [63:32];
  assign \cr_wr_data$151.word2_w2  = \cr_wr_data$151 [95:64];
  assign \cr_wr_data$152.word0_gt  = \cr_wr_data$152 [31:0];
  assign \cr_wr_data$152.word0_gt.slot_id  = \cr_wr_data$152 [15:0];
  assign \cr_wr_data$152.word0_gt.gt_seq  = \cr_wr_data$152 [24:16];
  assign \cr_wr_data$152.word0_gt.gt_type  = \cr_wr_data$152 [26:25];
  assign \cr_wr_data$152.word0_gt.dom  = \cr_wr_data$152 [27];
  assign \cr_wr_data$152.word0_gt.perm  = \cr_wr_data$152 [30:28];
  assign \cr_wr_data$152.word0_gt.b_flag  = \cr_wr_data$152 [31];
  assign \cr_wr_data$152.word1_location  = \cr_wr_data$152 [63:32];
  assign \cr_wr_data$152.word2_w2  = \cr_wr_data$152 [95:64];
  assign \cr_wr_data$153.word0_gt  = \cr_wr_data$153 [31:0];
  assign \cr_wr_data$153.word0_gt.slot_id  = \cr_wr_data$153 [15:0];
  assign \cr_wr_data$153.word0_gt.gt_seq  = \cr_wr_data$153 [24:16];
  assign \cr_wr_data$153.word0_gt.gt_type  = \cr_wr_data$153 [26:25];
  assign \cr_wr_data$153.word0_gt.dom  = \cr_wr_data$153 [27];
  assign \cr_wr_data$153.word0_gt.perm  = \cr_wr_data$153 [30:28];
  assign \cr_wr_data$153.word0_gt.b_flag  = \cr_wr_data$153 [31];
  assign \cr_wr_data$153.word1_location  = \cr_wr_data$153 [63:32];
  assign \cr_wr_data$153.word2_w2  = \cr_wr_data$153 [95:64];
  assign \cr_wr_data$154.word0_gt  = \cr_wr_data$154 [31:0];
  assign \cr_wr_data$154.word0_gt.slot_id  = \cr_wr_data$154 [15:0];
  assign \cr_wr_data$154.word0_gt.gt_seq  = \cr_wr_data$154 [24:16];
  assign \cr_wr_data$154.word0_gt.gt_type  = \cr_wr_data$154 [26:25];
  assign \cr_wr_data$154.word0_gt.dom  = \cr_wr_data$154 [27];
  assign \cr_wr_data$154.word0_gt.perm  = \cr_wr_data$154 [30:28];
  assign \cr_wr_data$154.word0_gt.b_flag  = \cr_wr_data$154 [31];
  assign \cr_wr_data$154.word1_location  = \cr_wr_data$154 [63:32];
  assign \cr_wr_data$154.word2_w2  = \cr_wr_data$154 [95:64];
  assign \cr_wr_data$155.word0_gt  = \cr_wr_data$155 [31:0];
  assign \cr_wr_data$155.word0_gt.slot_id  = \cr_wr_data$155 [15:0];
  assign \cr_wr_data$155.word0_gt.gt_seq  = \cr_wr_data$155 [24:16];
  assign \cr_wr_data$155.word0_gt.gt_type  = \cr_wr_data$155 [26:25];
  assign \cr_wr_data$155.word0_gt.dom  = \cr_wr_data$155 [27];
  assign \cr_wr_data$155.word0_gt.perm  = \cr_wr_data$155 [30:28];
  assign \cr_wr_data$155.word0_gt.b_flag  = \cr_wr_data$155 [31];
  assign \cr_wr_data$155.word1_location  = \cr_wr_data$155 [63:32];
  assign \cr_wr_data$155.word2_w2  = \cr_wr_data$155 [95:64];
  assign \cr_wr_data$156.word0_gt  = \cr_wr_data$156 [31:0];
  assign \cr_wr_data$156.word0_gt.slot_id  = \cr_wr_data$156 [15:0];
  assign \cr_wr_data$156.word0_gt.gt_seq  = \cr_wr_data$156 [24:16];
  assign \cr_wr_data$156.word0_gt.gt_type  = \cr_wr_data$156 [26:25];
  assign \cr_wr_data$156.word0_gt.dom  = \cr_wr_data$156 [27];
  assign \cr_wr_data$156.word0_gt.perm  = \cr_wr_data$156 [30:28];
  assign \cr_wr_data$156.word0_gt.b_flag  = \cr_wr_data$156 [31];
  assign \cr_wr_data$156.word1_location  = \cr_wr_data$156 [63:32];
  assign \cr_wr_data$156.word2_w2  = \cr_wr_data$156 [95:64];
  assign \dbg_cr_wr_data.word0_gt  = 32'd0;
  assign \dbg_cr_wr_data.word0_gt.slot_id  = 16'h0000;
  assign \dbg_cr_wr_data.word0_gt.gt_seq  = 9'h000;
  assign \dbg_cr_wr_data.word0_gt.gt_type  = 2'h0;
  assign \dbg_cr_wr_data.word0_gt.dom  = 1'h0;
  assign \dbg_cr_wr_data.word0_gt.perm  = 3'h0;
  assign \dbg_cr_wr_data.word0_gt.b_flag  = 1'h0;
  assign \dbg_cr_wr_data.word1_location  = 32'd0;
  assign \dbg_cr_wr_data.word2_w2  = 32'd0;
  assign \cr_wr_data$158.word0_gt  = 32'd0;
  assign \cr_wr_data$158.word0_gt.slot_id  = 16'h0000;
  assign \cr_wr_data$158.word0_gt.gt_seq  = 9'h000;
  assign \cr_wr_data$158.word0_gt.gt_type  = 2'h0;
  assign \cr_wr_data$158.word0_gt.dom  = 1'h0;
  assign \cr_wr_data$158.word0_gt.perm  = 3'h0;
  assign \cr_wr_data$158.word0_gt.b_flag  = 1'h0;
  assign \cr_wr_data$158.word1_location  = 32'd0;
  assign \cr_wr_data$158.word2_w2  = 32'd0;
  assign \cr_wr_data$159.word0_gt  = \cr_wr_data$159 [31:0];
  assign \cr_wr_data$159.word0_gt.slot_id  = \cr_wr_data$159 [15:0];
  assign \cr_wr_data$159.word0_gt.gt_seq  = \cr_wr_data$159 [24:16];
  assign \cr_wr_data$159.word0_gt.gt_type  = \cr_wr_data$159 [26:25];
  assign \cr_wr_data$159.word0_gt.dom  = \cr_wr_data$159 [27];
  assign \cr_wr_data$159.word0_gt.perm  = \cr_wr_data$159 [30:28];
  assign \cr_wr_data$159.word0_gt.b_flag  = \cr_wr_data$159 [31];
  assign \cr_wr_data$159.word1_location  = \cr_wr_data$159 [63:32];
  assign \cr_wr_data$159.word2_w2  = \cr_wr_data$159 [95:64];
  assign \cr_wr_data$160.word0_gt  = \cr_wr_data$160 [31:0];
  assign \cr_wr_data$160.word0_gt.slot_id  = \cr_wr_data$160 [15:0];
  assign \cr_wr_data$160.word0_gt.gt_seq  = \cr_wr_data$160 [24:16];
  assign \cr_wr_data$160.word0_gt.gt_type  = \cr_wr_data$160 [26:25];
  assign \cr_wr_data$160.word0_gt.dom  = \cr_wr_data$160 [27];
  assign \cr_wr_data$160.word0_gt.perm  = \cr_wr_data$160 [30:28];
  assign \cr_wr_data$160.word0_gt.b_flag  = \cr_wr_data$160 [31];
  assign \cr_wr_data$160.word1_location  = \cr_wr_data$160 [63:32];
  assign \cr_wr_data$160.word2_w2  = \cr_wr_data$160 [95:64];
  assign \cr_wr_data$161.word0_gt  = \cr_wr_data$161 [31:0];
  assign \cr_wr_data$161.word0_gt.slot_id  = \cr_wr_data$161 [15:0];
  assign \cr_wr_data$161.word0_gt.gt_seq  = \cr_wr_data$161 [24:16];
  assign \cr_wr_data$161.word0_gt.gt_type  = \cr_wr_data$161 [26:25];
  assign \cr_wr_data$161.word0_gt.dom  = \cr_wr_data$161 [27];
  assign \cr_wr_data$161.word0_gt.perm  = \cr_wr_data$161 [30:28];
  assign \cr_wr_data$161.word0_gt.b_flag  = \cr_wr_data$161 [31];
  assign \cr_wr_data$161.word1_location  = \cr_wr_data$161 [63:32];
  assign \cr_wr_data$161.word2_w2  = \cr_wr_data$161 [95:64];
  assign \boot_cap_wr_data.word0_gt  = boot_cap_wr_data[31:0];
  assign \boot_cap_wr_data.word0_gt.slot_id  = boot_cap_wr_data[15:0];
  assign \boot_cap_wr_data.word0_gt.gt_seq  = boot_cap_wr_data[24:16];
  assign \boot_cap_wr_data.word0_gt.gt_type  = boot_cap_wr_data[26:25];
  assign \boot_cap_wr_data.word0_gt.dom  = boot_cap_wr_data[27];
  assign \boot_cap_wr_data.word0_gt.perm  = boot_cap_wr_data[30:28];
  assign \boot_cap_wr_data.word0_gt.b_flag  = boot_cap_wr_data[31];
  assign \boot_cap_wr_data.word1_location  = boot_cap_wr_data[63:32];
  assign \boot_cap_wr_data.word2_w2  = boot_cap_wr_data[95:64];
  assign \mwin_cr_wr_data.word0_gt  = mwin_cr_wr_data[31:0];
  assign \mwin_cr_wr_data.word0_gt.slot_id  = mwin_cr_wr_data[15:0];
  assign \mwin_cr_wr_data.word0_gt.gt_seq  = mwin_cr_wr_data[24:16];
  assign \mwin_cr_wr_data.word0_gt.gt_type  = mwin_cr_wr_data[26:25];
  assign \mwin_cr_wr_data.word0_gt.dom  = mwin_cr_wr_data[27];
  assign \mwin_cr_wr_data.word0_gt.perm  = mwin_cr_wr_data[30:28];
  assign \mwin_cr_wr_data.word0_gt.b_flag  = mwin_cr_wr_data[31];
  assign \mwin_cr_wr_data.word1_location  = mwin_cr_wr_data[63:32];
  assign \mwin_cr_wr_data.word2_w2  = mwin_cr_wr_data[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \flags$208.N  = flags[0];
  assign \flags$208.Z  = flags[1];
  assign \flags$208.C  = flags[2];
  assign \flags$208.V  = flags[3];
  assign \thrd_gt.slot_id  = thrd_gt[15:0];
  assign \thrd_gt.gt_seq  = thrd_gt[24:16];
  assign \thrd_gt.gt_type  = thrd_gt[26:25];
  assign \thrd_gt.dom  = thrd_gt[27];
  assign \thrd_gt.perm  = thrd_gt[30:28];
  assign \thrd_gt.b_flag  = thrd_gt[31];
  assign \boot_cap8_wr_gt.slot_id  = boot_cap8_wr_gt[15:0];
  assign \boot_cap8_wr_gt.gt_seq  = boot_cap8_wr_gt[24:16];
  assign \boot_cap8_wr_gt.gt_type  = boot_cap8_wr_gt[26:25];
  assign \boot_cap8_wr_gt.dom  = boot_cap8_wr_gt[27];
  assign \boot_cap8_wr_gt.perm  = boot_cap8_wr_gt[30:28];
  assign \boot_cap8_wr_gt.b_flag  = boot_cap8_wr_gt[31];
  assign \cr14_gt.slot_id  = cr14_gt[15:0];
  assign \cr14_gt.gt_seq  = cr14_gt[24:16];
  assign \cr14_gt.gt_type  = cr14_gt[26:25];
  assign \cr14_gt.dom  = cr14_gt[27];
  assign \cr14_gt.perm  = cr14_gt[30:28];
  assign \cr14_gt.b_flag  = cr14_gt[31];
  assign \boot_cap14_wr_gt.slot_id  = boot_cap14_wr_gt[15:0];
  assign \boot_cap14_wr_gt.gt_seq  = boot_cap14_wr_gt[24:16];
  assign \boot_cap14_wr_gt.gt_type  = boot_cap14_wr_gt[26:25];
  assign \boot_cap14_wr_gt.dom  = boot_cap14_wr_gt[27];
  assign \boot_cap14_wr_gt.perm  = boot_cap14_wr_gt[30:28];
  assign \boot_cap14_wr_gt.b_flag  = boot_cap14_wr_gt[31];
  assign \switch_src_gt.slot_id  = cr_rd_data[15:0];
  assign \switch_src_gt.gt_seq  = cr_rd_data[24:16];
  assign \switch_src_gt.gt_type  = cr_rd_data[26:25];
  assign \switch_src_gt.dom  = cr_rd_data[27];
  assign \switch_src_gt.perm  = cr_rd_data[30:28];
  assign \switch_src_gt.b_flag  = cr_rd_data[31];
  assign \rt_cap8_wr_gt.slot_id  = rt_cap8_wr_gt[15:0];
  assign \rt_cap8_wr_gt.gt_seq  = rt_cap8_wr_gt[24:16];
  assign \rt_cap8_wr_gt.gt_type  = rt_cap8_wr_gt[26:25];
  assign \rt_cap8_wr_gt.dom  = rt_cap8_wr_gt[27];
  assign \rt_cap8_wr_gt.perm  = rt_cap8_wr_gt[30:28];
  assign \rt_cap8_wr_gt.b_flag  = rt_cap8_wr_gt[31];
  assign \rt_cap9_wr_gt.slot_id  = rt_cap9_wr_gt[15:0];
  assign \rt_cap9_wr_gt.gt_seq  = rt_cap9_wr_gt[24:16];
  assign \rt_cap9_wr_gt.gt_type  = rt_cap9_wr_gt[26:25];
  assign \rt_cap9_wr_gt.dom  = rt_cap9_wr_gt[27];
  assign \rt_cap9_wr_gt.perm  = rt_cap9_wr_gt[30:28];
  assign \rt_cap9_wr_gt.b_flag  = rt_cap9_wr_gt[31];
  assign \rt_cap10_wr_gt.slot_id  = rt_cap10_wr_gt[15:0];
  assign \rt_cap10_wr_gt.gt_seq  = rt_cap10_wr_gt[24:16];
  assign \rt_cap10_wr_gt.gt_type  = rt_cap10_wr_gt[26:25];
  assign \rt_cap10_wr_gt.dom  = rt_cap10_wr_gt[27];
  assign \rt_cap10_wr_gt.perm  = rt_cap10_wr_gt[30:28];
  assign \rt_cap10_wr_gt.b_flag  = rt_cap10_wr_gt[31];
  assign \rt_cap11_wr_gt.slot_id  = rt_cap11_wr_gt[15:0];
  assign \rt_cap11_wr_gt.gt_seq  = rt_cap11_wr_gt[24:16];
  assign \rt_cap11_wr_gt.gt_type  = rt_cap11_wr_gt[26:25];
  assign \rt_cap11_wr_gt.dom  = rt_cap11_wr_gt[27];
  assign \rt_cap11_wr_gt.perm  = rt_cap11_wr_gt[30:28];
  assign \rt_cap11_wr_gt.b_flag  = rt_cap11_wr_gt[31];
  assign \rt_cap12_wr_gt.slot_id  = rt_cap12_wr_gt[15:0];
  assign \rt_cap12_wr_gt.gt_seq  = rt_cap12_wr_gt[24:16];
  assign \rt_cap12_wr_gt.gt_type  = rt_cap12_wr_gt[26:25];
  assign \rt_cap12_wr_gt.dom  = rt_cap12_wr_gt[27];
  assign \rt_cap12_wr_gt.perm  = rt_cap12_wr_gt[30:28];
  assign \rt_cap12_wr_gt.b_flag  = rt_cap12_wr_gt[31];
  assign \rt_cap13_wr_gt.slot_id  = rt_cap13_wr_gt[15:0];
  assign \rt_cap13_wr_gt.gt_seq  = rt_cap13_wr_gt[24:16];
  assign \rt_cap13_wr_gt.gt_type  = rt_cap13_wr_gt[26:25];
  assign \rt_cap13_wr_gt.dom  = rt_cap13_wr_gt[27];
  assign \rt_cap13_wr_gt.perm  = rt_cap13_wr_gt[30:28];
  assign \rt_cap13_wr_gt.b_flag  = rt_cap13_wr_gt[31];
  assign \rt_cap14_wr_gt.slot_id  = rt_cap14_wr_gt[15:0];
  assign \rt_cap14_wr_gt.gt_seq  = rt_cap14_wr_gt[24:16];
  assign \rt_cap14_wr_gt.gt_type  = rt_cap14_wr_gt[26:25];
  assign \rt_cap14_wr_gt.dom  = rt_cap14_wr_gt[27];
  assign \rt_cap14_wr_gt.perm  = rt_cap14_wr_gt[30:28];
  assign \rt_cap14_wr_gt.b_flag  = rt_cap14_wr_gt[31];
  assign \rt_cap15_wr_gt.slot_id  = rt_cap15_wr_gt[15:0];
  assign \rt_cap15_wr_gt.gt_seq  = rt_cap15_wr_gt[24:16];
  assign \rt_cap15_wr_gt.gt_type  = rt_cap15_wr_gt[26:25];
  assign \rt_cap15_wr_gt.dom  = rt_cap15_wr_gt[27];
  assign \rt_cap15_wr_gt.perm  = rt_cap15_wr_gt[30:28];
  assign \rt_cap15_wr_gt.b_flag  = rt_cap15_wr_gt[31];
  assign \cr0_gt_wr_data.slot_id  = cr0_gt_wr_data[15:0];
  assign \cr0_gt_wr_data.gt_seq  = cr0_gt_wr_data[24:16];
  assign \cr0_gt_wr_data.gt_type  = cr0_gt_wr_data[26:25];
  assign \cr0_gt_wr_data.dom  = cr0_gt_wr_data[27];
  assign \cr0_gt_wr_data.perm  = cr0_gt_wr_data[30:28];
  assign \cr0_gt_wr_data.b_flag  = cr0_gt_wr_data[31];
  assign \rt_cap0_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap0_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap0_wr_gt.gt_type  = 2'h0;
  assign \rt_cap0_wr_gt.dom  = 1'h0;
  assign \rt_cap0_wr_gt.perm  = 3'h0;
  assign \rt_cap0_wr_gt.b_flag  = 1'h0;
  assign \boot_cap0_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap0_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap0_wr_gt.gt_type  = 2'h0;
  assign \boot_cap0_wr_gt.dom  = 1'h0;
  assign \boot_cap0_wr_gt.perm  = 3'h0;
  assign \boot_cap0_wr_gt.b_flag  = 1'h0;
  assign \cr1_gt_wr_data.slot_id  = cr1_gt_wr_data[15:0];
  assign \cr1_gt_wr_data.gt_seq  = cr1_gt_wr_data[24:16];
  assign \cr1_gt_wr_data.gt_type  = cr1_gt_wr_data[26:25];
  assign \cr1_gt_wr_data.dom  = cr1_gt_wr_data[27];
  assign \cr1_gt_wr_data.perm  = cr1_gt_wr_data[30:28];
  assign \cr1_gt_wr_data.b_flag  = cr1_gt_wr_data[31];
  assign \rt_cap1_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap1_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap1_wr_gt.gt_type  = 2'h0;
  assign \rt_cap1_wr_gt.dom  = 1'h0;
  assign \rt_cap1_wr_gt.perm  = 3'h0;
  assign \rt_cap1_wr_gt.b_flag  = 1'h0;
  assign \boot_cap1_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap1_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap1_wr_gt.gt_type  = 2'h0;
  assign \boot_cap1_wr_gt.dom  = 1'h0;
  assign \boot_cap1_wr_gt.perm  = 3'h0;
  assign \boot_cap1_wr_gt.b_flag  = 1'h0;
  assign \cr2_gt_wr_data.slot_id  = cr2_gt_wr_data[15:0];
  assign \cr2_gt_wr_data.gt_seq  = cr2_gt_wr_data[24:16];
  assign \cr2_gt_wr_data.gt_type  = cr2_gt_wr_data[26:25];
  assign \cr2_gt_wr_data.dom  = cr2_gt_wr_data[27];
  assign \cr2_gt_wr_data.perm  = cr2_gt_wr_data[30:28];
  assign \cr2_gt_wr_data.b_flag  = cr2_gt_wr_data[31];
  assign \rt_cap2_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap2_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap2_wr_gt.gt_type  = 2'h0;
  assign \rt_cap2_wr_gt.dom  = 1'h0;
  assign \rt_cap2_wr_gt.perm  = 3'h0;
  assign \rt_cap2_wr_gt.b_flag  = 1'h0;
  assign \boot_cap2_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap2_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap2_wr_gt.gt_type  = 2'h0;
  assign \boot_cap2_wr_gt.dom  = 1'h0;
  assign \boot_cap2_wr_gt.perm  = 3'h0;
  assign \boot_cap2_wr_gt.b_flag  = 1'h0;
  assign \cr3_gt_wr_data.slot_id  = cr3_gt_wr_data[15:0];
  assign \cr3_gt_wr_data.gt_seq  = cr3_gt_wr_data[24:16];
  assign \cr3_gt_wr_data.gt_type  = cr3_gt_wr_data[26:25];
  assign \cr3_gt_wr_data.dom  = cr3_gt_wr_data[27];
  assign \cr3_gt_wr_data.perm  = cr3_gt_wr_data[30:28];
  assign \cr3_gt_wr_data.b_flag  = cr3_gt_wr_data[31];
  assign \rt_cap3_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap3_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap3_wr_gt.gt_type  = 2'h0;
  assign \rt_cap3_wr_gt.dom  = 1'h0;
  assign \rt_cap3_wr_gt.perm  = 3'h0;
  assign \rt_cap3_wr_gt.b_flag  = 1'h0;
  assign \boot_cap3_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap3_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap3_wr_gt.gt_type  = 2'h0;
  assign \boot_cap3_wr_gt.dom  = 1'h0;
  assign \boot_cap3_wr_gt.perm  = 3'h0;
  assign \boot_cap3_wr_gt.b_flag  = 1'h0;
  assign \cr4_gt_wr_data.slot_id  = cr4_gt_wr_data[15:0];
  assign \cr4_gt_wr_data.gt_seq  = cr4_gt_wr_data[24:16];
  assign \cr4_gt_wr_data.gt_type  = cr4_gt_wr_data[26:25];
  assign \cr4_gt_wr_data.dom  = cr4_gt_wr_data[27];
  assign \cr4_gt_wr_data.perm  = cr4_gt_wr_data[30:28];
  assign \cr4_gt_wr_data.b_flag  = cr4_gt_wr_data[31];
  assign \rt_cap4_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap4_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap4_wr_gt.gt_type  = 2'h0;
  assign \rt_cap4_wr_gt.dom  = 1'h0;
  assign \rt_cap4_wr_gt.perm  = 3'h0;
  assign \rt_cap4_wr_gt.b_flag  = 1'h0;
  assign \boot_cap4_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap4_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap4_wr_gt.gt_type  = 2'h0;
  assign \boot_cap4_wr_gt.dom  = 1'h0;
  assign \boot_cap4_wr_gt.perm  = 3'h0;
  assign \boot_cap4_wr_gt.b_flag  = 1'h0;
  assign \cr5_gt_wr_data.slot_id  = cr5_gt_wr_data[15:0];
  assign \cr5_gt_wr_data.gt_seq  = cr5_gt_wr_data[24:16];
  assign \cr5_gt_wr_data.gt_type  = cr5_gt_wr_data[26:25];
  assign \cr5_gt_wr_data.dom  = cr5_gt_wr_data[27];
  assign \cr5_gt_wr_data.perm  = cr5_gt_wr_data[30:28];
  assign \cr5_gt_wr_data.b_flag  = cr5_gt_wr_data[31];
  assign \rt_cap5_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap5_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap5_wr_gt.gt_type  = 2'h0;
  assign \rt_cap5_wr_gt.dom  = 1'h0;
  assign \rt_cap5_wr_gt.perm  = 3'h0;
  assign \rt_cap5_wr_gt.b_flag  = 1'h0;
  assign \boot_cap5_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap5_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap5_wr_gt.gt_type  = 2'h0;
  assign \boot_cap5_wr_gt.dom  = 1'h0;
  assign \boot_cap5_wr_gt.perm  = 3'h0;
  assign \boot_cap5_wr_gt.b_flag  = 1'h0;
  assign \cr6_gt_wr_data.slot_id  = cr6_gt_wr_data[15:0];
  assign \cr6_gt_wr_data.gt_seq  = cr6_gt_wr_data[24:16];
  assign \cr6_gt_wr_data.gt_type  = cr6_gt_wr_data[26:25];
  assign \cr6_gt_wr_data.dom  = cr6_gt_wr_data[27];
  assign \cr6_gt_wr_data.perm  = cr6_gt_wr_data[30:28];
  assign \cr6_gt_wr_data.b_flag  = cr6_gt_wr_data[31];
  assign \rt_cap6_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap6_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap6_wr_gt.gt_type  = 2'h0;
  assign \rt_cap6_wr_gt.dom  = 1'h0;
  assign \rt_cap6_wr_gt.perm  = 3'h0;
  assign \rt_cap6_wr_gt.b_flag  = 1'h0;
  assign \boot_cap6_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap6_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap6_wr_gt.gt_type  = 2'h0;
  assign \boot_cap6_wr_gt.dom  = 1'h0;
  assign \boot_cap6_wr_gt.perm  = 3'h0;
  assign \boot_cap6_wr_gt.b_flag  = 1'h0;
  assign \cr7_gt_wr_data.slot_id  = cr7_gt_wr_data[15:0];
  assign \cr7_gt_wr_data.gt_seq  = cr7_gt_wr_data[24:16];
  assign \cr7_gt_wr_data.gt_type  = cr7_gt_wr_data[26:25];
  assign \cr7_gt_wr_data.dom  = cr7_gt_wr_data[27];
  assign \cr7_gt_wr_data.perm  = cr7_gt_wr_data[30:28];
  assign \cr7_gt_wr_data.b_flag  = cr7_gt_wr_data[31];
  assign \rt_cap7_wr_gt.slot_id  = 16'h0000;
  assign \rt_cap7_wr_gt.gt_seq  = 9'h000;
  assign \rt_cap7_wr_gt.gt_type  = 2'h0;
  assign \rt_cap7_wr_gt.dom  = 1'h0;
  assign \rt_cap7_wr_gt.perm  = 3'h0;
  assign \rt_cap7_wr_gt.b_flag  = 1'h0;
  assign \boot_cap7_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap7_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap7_wr_gt.gt_type  = 2'h0;
  assign \boot_cap7_wr_gt.dom  = 1'h0;
  assign \boot_cap7_wr_gt.perm  = 3'h0;
  assign \boot_cap7_wr_gt.b_flag  = 1'h0;
  assign \cr8_gt_wr_data.slot_id  = cr8_gt_wr_data[15:0];
  assign \cr8_gt_wr_data.gt_seq  = cr8_gt_wr_data[24:16];
  assign \cr8_gt_wr_data.gt_type  = cr8_gt_wr_data[26:25];
  assign \cr8_gt_wr_data.dom  = cr8_gt_wr_data[27];
  assign \cr8_gt_wr_data.perm  = cr8_gt_wr_data[30:28];
  assign \cr8_gt_wr_data.b_flag  = cr8_gt_wr_data[31];
  assign \cr9_gt_wr_data.slot_id  = cr9_gt_wr_data[15:0];
  assign \cr9_gt_wr_data.gt_seq  = cr9_gt_wr_data[24:16];
  assign \cr9_gt_wr_data.gt_type  = cr9_gt_wr_data[26:25];
  assign \cr9_gt_wr_data.dom  = cr9_gt_wr_data[27];
  assign \cr9_gt_wr_data.perm  = cr9_gt_wr_data[30:28];
  assign \cr9_gt_wr_data.b_flag  = cr9_gt_wr_data[31];
  assign \boot_cap9_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap9_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap9_wr_gt.gt_type  = 2'h0;
  assign \boot_cap9_wr_gt.dom  = 1'h0;
  assign \boot_cap9_wr_gt.perm  = 3'h0;
  assign \boot_cap9_wr_gt.b_flag  = 1'h0;
  assign \cr10_gt_wr_data.slot_id  = cr10_gt_wr_data[15:0];
  assign \cr10_gt_wr_data.gt_seq  = cr10_gt_wr_data[24:16];
  assign \cr10_gt_wr_data.gt_type  = cr10_gt_wr_data[26:25];
  assign \cr10_gt_wr_data.dom  = cr10_gt_wr_data[27];
  assign \cr10_gt_wr_data.perm  = cr10_gt_wr_data[30:28];
  assign \cr10_gt_wr_data.b_flag  = cr10_gt_wr_data[31];
  assign \boot_cap10_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap10_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap10_wr_gt.gt_type  = 2'h0;
  assign \boot_cap10_wr_gt.dom  = 1'h0;
  assign \boot_cap10_wr_gt.perm  = 3'h0;
  assign \boot_cap10_wr_gt.b_flag  = 1'h0;
  assign \cr11_gt_wr_data.slot_id  = cr11_gt_wr_data[15:0];
  assign \cr11_gt_wr_data.gt_seq  = cr11_gt_wr_data[24:16];
  assign \cr11_gt_wr_data.gt_type  = cr11_gt_wr_data[26:25];
  assign \cr11_gt_wr_data.dom  = cr11_gt_wr_data[27];
  assign \cr11_gt_wr_data.perm  = cr11_gt_wr_data[30:28];
  assign \cr11_gt_wr_data.b_flag  = cr11_gt_wr_data[31];
  assign \boot_cap11_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap11_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap11_wr_gt.gt_type  = 2'h0;
  assign \boot_cap11_wr_gt.dom  = 1'h0;
  assign \boot_cap11_wr_gt.perm  = 3'h0;
  assign \boot_cap11_wr_gt.b_flag  = 1'h0;
  assign \cr12_gt_wr_data.slot_id  = cr12_gt_wr_data[15:0];
  assign \cr12_gt_wr_data.gt_seq  = cr12_gt_wr_data[24:16];
  assign \cr12_gt_wr_data.gt_type  = cr12_gt_wr_data[26:25];
  assign \cr12_gt_wr_data.dom  = cr12_gt_wr_data[27];
  assign \cr12_gt_wr_data.perm  = cr12_gt_wr_data[30:28];
  assign \cr12_gt_wr_data.b_flag  = cr12_gt_wr_data[31];
  assign \boot_cap12_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap12_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap12_wr_gt.gt_type  = 2'h0;
  assign \boot_cap12_wr_gt.dom  = 1'h0;
  assign \boot_cap12_wr_gt.perm  = 3'h0;
  assign \boot_cap12_wr_gt.b_flag  = 1'h0;
  assign \cr13_gt_wr_data.slot_id  = cr13_gt_wr_data[15:0];
  assign \cr13_gt_wr_data.gt_seq  = cr13_gt_wr_data[24:16];
  assign \cr13_gt_wr_data.gt_type  = cr13_gt_wr_data[26:25];
  assign \cr13_gt_wr_data.dom  = cr13_gt_wr_data[27];
  assign \cr13_gt_wr_data.perm  = cr13_gt_wr_data[30:28];
  assign \cr13_gt_wr_data.b_flag  = cr13_gt_wr_data[31];
  assign \boot_cap13_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap13_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap13_wr_gt.gt_type  = 2'h0;
  assign \boot_cap13_wr_gt.dom  = 1'h0;
  assign \boot_cap13_wr_gt.perm  = 3'h0;
  assign \boot_cap13_wr_gt.b_flag  = 1'h0;
  assign \cr14_gt_wr_data.slot_id  = cr14_gt_wr_data[15:0];
  assign \cr14_gt_wr_data.gt_seq  = cr14_gt_wr_data[24:16];
  assign \cr14_gt_wr_data.gt_type  = cr14_gt_wr_data[26:25];
  assign \cr14_gt_wr_data.dom  = cr14_gt_wr_data[27];
  assign \cr14_gt_wr_data.perm  = cr14_gt_wr_data[30:28];
  assign \cr14_gt_wr_data.b_flag  = cr14_gt_wr_data[31];
  assign \cr15_gt_wr_data.slot_id  = cr15_gt_wr_data[15:0];
  assign \cr15_gt_wr_data.gt_seq  = cr15_gt_wr_data[24:16];
  assign \cr15_gt_wr_data.gt_type  = cr15_gt_wr_data[26:25];
  assign \cr15_gt_wr_data.dom  = cr15_gt_wr_data[27];
  assign \cr15_gt_wr_data.perm  = cr15_gt_wr_data[30:28];
  assign \cr15_gt_wr_data.b_flag  = cr15_gt_wr_data[31];
  assign \boot_cap15_wr_gt.slot_id  = 16'h0000;
  assign \boot_cap15_wr_gt.gt_seq  = 9'h000;
  assign \boot_cap15_wr_gt.gt_type  = 2'h0;
  assign \boot_cap15_wr_gt.dom  = 1'h0;
  assign \boot_cap15_wr_gt.perm  = 3'h0;
  assign \boot_cap15_wr_gt.b_flag  = 1'h0;
  assign \src_cr_data.word0_gt  = cr_rd_data[31:0];
  assign \src_cr_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \src_cr_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \src_cr_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \src_cr_data.word0_gt.dom  = cr_rd_data[27];
  assign \src_cr_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \src_cr_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \src_cr_data.word1_location  = cr_rd_data[63:32];
  assign \src_cr_data.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$323.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$323.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$323.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$323.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$323.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$323.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$323.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$323.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$323.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace$324.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$324.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$324.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$324.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$324.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$324.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$324.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$324.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$324.word2_w2  = cr15_namespace[95:64];
  assign \cr14_code.word0_gt  = cr14_code[31:0];
  assign \cr14_code.word0_gt.slot_id  = cr14_code[15:0];
  assign \cr14_code.word0_gt.gt_seq  = cr14_code[24:16];
  assign \cr14_code.word0_gt.gt_type  = cr14_code[26:25];
  assign \cr14_code.word0_gt.dom  = cr14_code[27];
  assign \cr14_code.word0_gt.perm  = cr14_code[30:28];
  assign \cr14_code.word0_gt.b_flag  = cr14_code[31];
  assign \cr14_code.word1_location  = cr14_code[63:32];
  assign \cr14_code.word2_w2  = cr14_code[95:64];
  assign \cr14_code$326.word0_gt  = cr14_code[31:0];
  assign \cr14_code$326.word0_gt.slot_id  = cr14_code[15:0];
  assign \cr14_code$326.word0_gt.gt_seq  = cr14_code[24:16];
  assign \cr14_code$326.word0_gt.gt_type  = cr14_code[26:25];
  assign \cr14_code$326.word0_gt.dom  = cr14_code[27];
  assign \cr14_code$326.word0_gt.perm  = cr14_code[30:28];
  assign \cr14_code$326.word0_gt.b_flag  = cr14_code[31];
  assign \cr14_code$326.word1_location  = cr14_code[63:32];
  assign \cr14_code$326.word2_w2  = cr14_code[95:64];
  assign \cr5_heap.word0_gt  = cr5_heap[31:0];
  assign \cr5_heap.word0_gt.slot_id  = cr5_heap[15:0];
  assign \cr5_heap.word0_gt.gt_seq  = cr5_heap[24:16];
  assign \cr5_heap.word0_gt.gt_type  = cr5_heap[26:25];
  assign \cr5_heap.word0_gt.dom  = cr5_heap[27];
  assign \cr5_heap.word0_gt.perm  = cr5_heap[30:28];
  assign \cr5_heap.word0_gt.b_flag  = cr5_heap[31];
  assign \cr5_heap.word1_location  = cr5_heap[63:32];
  assign \cr5_heap.word2_w2  = cr5_heap[95:64];
  assign \cr5_heap$332.word0_gt  = cr5_heap[31:0];
  assign \cr5_heap$332.word0_gt.slot_id  = cr5_heap[15:0];
  assign \cr5_heap$332.word0_gt.gt_seq  = cr5_heap[24:16];
  assign \cr5_heap$332.word0_gt.gt_type  = cr5_heap[26:25];
  assign \cr5_heap$332.word0_gt.dom  = cr5_heap[27];
  assign \cr5_heap$332.word0_gt.perm  = cr5_heap[30:28];
  assign \cr5_heap$332.word0_gt.b_flag  = cr5_heap[31];
  assign \cr5_heap$332.word1_location  = cr5_heap[63:32];
  assign \cr5_heap$332.word2_w2  = cr5_heap[95:64];
  assign \cr12_thread.word0_gt  = cr12_thread[31:0];
  assign \cr12_thread.word0_gt.slot_id  = cr12_thread[15:0];
  assign \cr12_thread.word0_gt.gt_seq  = cr12_thread[24:16];
  assign \cr12_thread.word0_gt.gt_type  = cr12_thread[26:25];
  assign \cr12_thread.word0_gt.dom  = cr12_thread[27];
  assign \cr12_thread.word0_gt.perm  = cr12_thread[30:28];
  assign \cr12_thread.word0_gt.b_flag  = cr12_thread[31];
  assign \cr12_thread.word1_location  = cr12_thread[63:32];
  assign \cr12_thread.word2_w2  = cr12_thread[95:64];
  assign \cr12_thread$335.word0_gt  = cr12_thread[31:0];
  assign \cr12_thread$335.word0_gt.slot_id  = cr12_thread[15:0];
  assign \cr12_thread$335.word0_gt.gt_seq  = cr12_thread[24:16];
  assign \cr12_thread$335.word0_gt.gt_type  = cr12_thread[26:25];
  assign \cr12_thread$335.word0_gt.dom  = cr12_thread[27];
  assign \cr12_thread$335.word0_gt.perm  = cr12_thread[30:28];
  assign \cr12_thread$335.word0_gt.b_flag  = cr12_thread[31];
  assign \cr12_thread$335.word1_location  = cr12_thread[63:32];
  assign \cr12_thread$335.word2_w2  = cr12_thread[95:64];
  assign \cr_rd_data$346.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$346.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$346.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$346.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$346.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$346.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$346.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$346.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$346.word2_w2  = cr_rd_data[95:64];
  assign \cr5_heap$350.word0_gt  = cr5_heap[31:0];
  assign \cr5_heap$350.word0_gt.slot_id  = cr5_heap[15:0];
  assign \cr5_heap$350.word0_gt.gt_seq  = cr5_heap[24:16];
  assign \cr5_heap$350.word0_gt.gt_type  = cr5_heap[26:25];
  assign \cr5_heap$350.word0_gt.dom  = cr5_heap[27];
  assign \cr5_heap$350.word0_gt.perm  = cr5_heap[30:28];
  assign \cr5_heap$350.word0_gt.b_flag  = cr5_heap[31];
  assign \cr5_heap$350.word1_location  = cr5_heap[63:32];
  assign \cr5_heap$350.word2_w2  = cr5_heap[95:64];
  assign \cr12_thread$351.word0_gt  = cr12_thread[31:0];
  assign \cr12_thread$351.word0_gt.slot_id  = cr12_thread[15:0];
  assign \cr12_thread$351.word0_gt.gt_seq  = cr12_thread[24:16];
  assign \cr12_thread$351.word0_gt.gt_type  = cr12_thread[26:25];
  assign \cr12_thread$351.word0_gt.dom  = cr12_thread[27];
  assign \cr12_thread$351.word0_gt.perm  = cr12_thread[30:28];
  assign \cr12_thread$351.word0_gt.b_flag  = cr12_thread[31];
  assign \cr12_thread$351.word1_location  = cr12_thread[63:32];
  assign \cr12_thread$351.word2_w2  = cr12_thread[95:64];
  assign \cr15_namespace$357.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$357.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$357.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$357.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$357.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$357.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$357.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$357.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$357.word2_w2  = cr15_namespace[95:64];
  assign \cr_rd_data$362.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$362.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$362.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$362.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$362.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$362.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$362.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$362.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$362.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$370.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$370.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$370.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$370.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$370.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$370.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$370.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$370.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$370.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$378.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$378.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$378.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$378.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$378.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$378.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$378.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$378.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$378.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace$379.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$379.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$379.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$379.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$379.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$379.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$379.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$379.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$379.word2_w2  = cr15_namespace[95:64];
  assign \cr_rd_data$390.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$390.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$390.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$390.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$390.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$390.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$390.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$390.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$390.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$400.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$400.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$400.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$400.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$400.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$400.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$400.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$400.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$400.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$446.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$446.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$446.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$446.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$446.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$446.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$446.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$446.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$446.word2_w2  = cr_rd_data[95:64];
  assign \cr12_thread$447.word0_gt  = cr12_thread[31:0];
  assign \cr12_thread$447.word0_gt.slot_id  = cr12_thread[15:0];
  assign \cr12_thread$447.word0_gt.gt_seq  = cr12_thread[24:16];
  assign \cr12_thread$447.word0_gt.gt_type  = cr12_thread[26:25];
  assign \cr12_thread$447.word0_gt.dom  = cr12_thread[27];
  assign \cr12_thread$447.word0_gt.perm  = cr12_thread[30:28];
  assign \cr12_thread$447.word0_gt.b_flag  = cr12_thread[31];
  assign \cr12_thread$447.word1_location  = cr12_thread[63:32];
  assign \cr12_thread$447.word2_w2  = cr12_thread[95:64];
  assign \cr15_namespace$448.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$448.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$448.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$448.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$448.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$448.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$448.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$448.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$448.word2_w2  = cr15_namespace[95:64];
  assign \flags$454.N  = flags[0];
  assign \flags$454.Z  = flags[1];
  assign \flags$454.C  = flags[2];
  assign \flags$454.V  = flags[3];
  assign \cr_rd_data$461.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$461.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$461.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$461.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$461.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$461.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$461.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$461.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$461.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace$462.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$462.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$462.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$462.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$462.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$462.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$462.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$462.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$462.word2_w2  = cr15_namespace[95:64];
  assign \cr_rd_data$474.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$474.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$474.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$474.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$474.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$474.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$474.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$474.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$474.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace$475.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$475.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$475.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$475.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$475.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$475.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$475.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$475.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$475.word2_w2  = cr15_namespace[95:64];
  assign \cr_rd_data$483.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$483.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$483.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$483.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$483.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$483.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$483.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$483.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$483.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace$484.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$484.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$484.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$484.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$484.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$484.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$484.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$484.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$484.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$506.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$506.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$506.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$506.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$506.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$506.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$506.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$506.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$506.word2_w2  = cr15_namespace[95:64];
  assign \cr_rd_data$664.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$664.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$664.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$664.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$664.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$664.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$664.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$664.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$664.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace$665.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$665.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$665.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$665.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$665.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$665.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$665.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$665.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$665.word2_w2  = cr15_namespace[95:64];
  assign mcmp_flags_sig[3] = 1'h0;
  assign mcmp_flags_sig[2] = mcmp_result[32];
  assign mcmp_flags_sig[1] = \$195 ;
  assign mcmp_flags_sig[0] = mcmp_result[31];
  assign bfins_flags_sig[3] = 1'h0;
  assign bfins_flags_sig[2] = 1'h0;
  assign bfins_flags_sig[1] = \$192 ;
  assign bfins_flags_sig[0] = \$191 [31];
  assign bfext_flags_sig[3] = 1'h0;
  assign bfext_flags_sig[2] = 1'h0;
  assign bfext_flags_sig[1] = \$183 ;
  assign bfext_flags_sig[0] = bfext_result[31];
  assign shr_flags_sig[3] = 1'h0;
  assign shr_flags_sig[2] = shr_c_bit;
  assign shr_flags_sig[1] = \$177 ;
  assign shr_flags_sig[0] = shr_result[31];
  assign shl_flags_sig[3] = 1'h0;
  assign shl_flags_sig[2] = shl_c_bit;
  assign shl_flags_sig[1] = \$176 ;
  assign shl_flags_sig[0] = \$168 [31];
  assign isub_flags_sig[3] = 1'h0;
  assign isub_flags_sig[2] = isub_result[32];
  assign isub_flags_sig[1] = \$163 ;
  assign isub_flags_sig[0] = isub_result[31];
  assign iadd_flags_sig[3] = 1'h0;
  assign iadd_flags_sig[2] = iadd_result[32];
  assign iadd_flags_sig[1] = \$162 ;
  assign iadd_flags_sig[0] = iadd_result[31];
  always @*
    cr14_gt[31] = 1'h0;
  always @*
    thrd_gt[31] = 1'h0;
  assign \$75  = \$74 ;
  assign \$76  = \$75 ;
  assign \$87  = \$86 ;
  assign \$88  = \$87 ;
  assign \$97  = \$96 ;
  assign \$103  = \$102 ;
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = cr15_namespace[93:64];
  assign { cr15_m_set_integrity[29], cr15_m_set_integrity[24], cr15_m_set_integrity[22], cr15_m_set_integrity[20], cr15_m_set_integrity[17], cr15_m_set_integrity[14], cr15_m_set_integrity[8], cr15_m_set_integrity[4] } = { \$104 [29], \$104 [24], \$104 [22], \$104 [20], \$104 [17], \$104 [14], \$104 [8], \$104 [4] };
  assign { cr15_m_set_integrity[31:30], cr15_m_set_integrity[28:25], cr15_m_set_integrity[23], cr15_m_set_integrity[21], cr15_m_set_integrity[19:18], cr15_m_set_integrity[16:15], cr15_m_set_integrity[13:9], cr15_m_set_integrity[7:5], cr15_m_set_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$34 ;
  assign cr0_gt_wr_en = 1'h0;
  assign cr0_gt_wr_data = 32'd0;
  assign cr1_gt_wr_en = 1'h0;
  assign cr1_gt_wr_data = 32'd0;
  assign cr2_gt_wr_en = 1'h0;
  assign cr2_gt_wr_data = 32'd0;
  assign cr3_gt_wr_en = 1'h0;
  assign cr3_gt_wr_data = 32'd0;
  assign cr4_gt_wr_en = 1'h0;
  assign cr4_gt_wr_data = 32'd0;
  assign cr5_gt_wr_en = 1'h0;
  assign cr5_gt_wr_data = 32'd0;
  assign cr6_gt_wr_en = 1'h0;
  assign cr6_gt_wr_data = 32'd0;
  assign cr7_gt_wr_en = 1'h0;
  assign cr7_gt_wr_data = 32'd0;
  assign cr9_gt_wr_en = rt_cap9_wr_en;
  assign cr9_gt_wr_data = rt_cap9_wr_gt;
  assign cr10_gt_wr_en = rt_cap10_wr_en;
  assign cr10_gt_wr_data = rt_cap10_wr_gt;
  assign cr11_gt_wr_en = rt_cap11_wr_en;
  assign cr11_gt_wr_data = rt_cap11_wr_gt;
  assign cr12_gt_wr_en = rt_cap12_wr_en;
  assign cr12_gt_wr_data = rt_cap12_wr_gt;
  assign cr13_gt_wr_en = rt_cap13_wr_en;
  assign cr13_gt_wr_data = rt_cap13_wr_gt;
  assign cr15_gt_wr_en = rt_cap15_wr_en;
  assign cr15_gt_wr_data = rt_cap15_wr_gt;
  assign irq_dispatch_reason = \$219 ;
  assign irq_dispatch_slot = \$221 ;
  assign \$222  = lazy_load_irq;
  assign \$227  = outform_start_out;
  assign gt_raw = \$228 ;
  assign slot_id = \$229 ;
  assign \$232  = outform_done;
  assign result_gt_in = outform_result_gt;
  assign \$245  = { 1'h0, \$237 [31:0], 2'h0 };
  assign \$246  = { 3'h0, mint_slot_id_reg, 4'h0 };
  assign { \$248 [29:26], \$248 [24:17], \$248 [15:0] } = { 12'h000, mint_slot_id_reg };
  assign { \$248 [30], \$248 [25], \$248 [16] } = 3'h7;
  assign \$250 [20:0] = { 5'h00, \$249  };
  assign \$250 [21] = 1'h1;
  assign \w1_masked$569 [31:30] = 2'h0;
  assign \w1_masked$569 [29:0] = { 14'h0020, \$249  };
  assign { mint_integrity_ni[29], mint_integrity_ni[24], mint_integrity_ni[22], mint_integrity_ni[20], mint_integrity_ni[17], mint_integrity_ni[14], mint_integrity_ni[8], mint_integrity_ni[4] } = { \$251 [29], \$251 [24], \$251 [22], \$251 [20], \$251 [17], \$251 [14], \$251 [8], \$251 [4] };
  assign { mint_integrity_ni[31:30], mint_integrity_ni[28:25], mint_integrity_ni[23], mint_integrity_ni[21], mint_integrity_ni[19:18], mint_integrity_ni[16:15], mint_integrity_ni[13:9], mint_integrity_ni[7:5], mint_integrity_ni[3:0] } = \$auto$rtlil.cc:2739:Not$36 ;
  assign \$257  = { 1'h0, mint_scan_idx_reg_ni, 2'h0 };
  assign \$264  = { 1'h0, cc_off_ni, 2'h0 };
  assign \$266  = { 1'h0, mint_copy_idx_reg_ni, 2'h0 };
  assign \$269  = \$268 ;
  assign \w1_masked$600 [31:30] = 2'h0;
  assign \w1_masked$600 [29:0] = mwin_dr13_lat[29:0];
  assign { mwin_integrity_computed[29], mwin_integrity_computed[24], mwin_integrity_computed[22], mwin_integrity_computed[20], mwin_integrity_computed[17], mwin_integrity_computed[14], mwin_integrity_computed[8], mwin_integrity_computed[4] } = { \$270 [29], \$270 [24], \$270 [22], \$270 [20], \$270 [17], \$270 [14], \$270 [8], \$270 [4] };
  assign { mwin_integrity_computed[31:30], mwin_integrity_computed[28:25], mwin_integrity_computed[23], mwin_integrity_computed[21], mwin_integrity_computed[19:18], mwin_integrity_computed[16:15], mwin_integrity_computed[13:9], mwin_integrity_computed[7:5], mwin_integrity_computed[3:0] } = \$auto$rtlil.cc:2739:Not$38 ;
  assign { mwin_fnv_xor[30:25], mwin_fnv_xor[23:21], mwin_fnv_xor[17:16], mwin_fnv_xor[14:13], mwin_fnv_xor[9], mwin_fnv_xor[5:3], mwin_fnv_xor[1] } = { mwin_dr12_lat[30:25], mwin_dr12_lat[23:21], mwin_dr12_lat[17:16], mwin_dr12_lat[14:13], mwin_dr12_lat[9], mwin_dr12_lat[5:3], mwin_dr12_lat[1] };
  assign { mwin_fnv_xor[31], mwin_fnv_xor[24], mwin_fnv_xor[20:18], mwin_fnv_xor[15], mwin_fnv_xor[12:10], mwin_fnv_xor[8:6], mwin_fnv_xor[2], mwin_fnv_xor[0] } = \$auto$rtlil.cc:2739:Not$40 ;
  assign \$272  = mgt_set_trigger;
  assign \$327  = { 1'h0, \$326 , 2'h0 };
  assign \$357  = \$356 ;
  assign \$359  = \$358 ;
endmodule

(* src = "/home/runner/workspace/hardware/call.py:112" *)
(* generator = "Amaranth" *)
module \top.core.u_call (clk, mem_rd_valid, call_start, cr_rd_data, mload_src, mload_dst, mload_index, nia_computed, code_lo_out, code_hi_out, call_busy, lazy_load_irq, call_normal_complete, mgt_set_trigger, mload_fault, mload_done, caller_pc, cr5_heap, cr12_thread, cr14_code, cr15_namespace, cr_null_mask
, cr_b_clear_mask, cr_rd_addr, cr_wr_addr, cr_wr_data, cr_wr_en, mem_rd_addr, mem_rd_en, mem_wr_addr, mem_wr_data, mem_wr_en, call_fault, fault_type, mgt_gt_lat, mload_start, lazy_load_ns_slot, mgt_ns_location, mgt_ns_authority, mgt_ns_integrity, mgt_ns_seals, mload_fault_type, thread_hdr
, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$44  = 0;
  wire [4:0] \$1 ;
  wire [32:0] \$10 ;
  reg [31:0] \$100 ;
  reg [31:0] \$101 ;
  reg [31:0] \$102 ;
  reg [31:0] \$103 ;
  reg [31:0] \$104 ;
  wire [22:0] \$11 ;
  wire [32:0] \$12 ;
  wire [32:0] \$13 ;
  wire \$14 ;
  wire [32:0] \$15 ;
  wire [34:0] \$16 ;
  wire [35:0] \$17 ;
  wire [35:0] \$18 ;
  wire [13:0] \$19 ;
  wire [45:0] \$2 ;
  wire [15:0] \$20 ;
  wire [18:0] \$21 ;
  wire [33:0] \$22 ;
  wire [8:0] \$23 ;
  wire [32:0] \$24 ;
  wire [15:0] \$25 ;
  wire [32:0] \$26 ;
  wire [17:0] \$27 ;
  wire [32:0] \$28 ;
  wire \$29 ;
  wire [15:0] \$3 ;
  wire [11:0] \$30 ;
  wire [32:0] \$31 ;
  wire [35:0] \$32 ;
  wire [36:0] \$33 ;
  wire [34:0] \$34 ;
  wire [35:0] \$35 ;
  wire [32:0] \$36 ;
  wire [32:0] \$37 ;
  wire [32:0] \$38 ;
  wire [32:0] \$39 ;
  wire [16:0] \$4 ;
  wire \$40 ;
  wire \$41 ;
  wire \$42 ;
  wire \$43 ;
  wire \$44 ;
  wire \$45 ;
  wire \$46 ;
  wire \$47 ;
  wire \$48 ;
  wire \$49 ;
  wire [15:0] \$5 ;
  wire \$50 ;
  wire \$51 ;
  wire \$52 ;
  wire \$53 ;
  wire \$54 ;
  wire \$55 ;
  wire \$56 ;
  wire \$57 ;
  wire \$58 ;
  wire \$59 ;
  wire [15:0] \$6 ;
  wire \$60 ;
  wire \$61 ;
  wire \$62 ;
  wire \$63 ;
  wire \$64 ;
  wire \$65 ;
  wire \$66 ;
  wire \$67 ;
  wire \$68 ;
  wire \$69 ;
  wire [15:0] \$7 ;
  wire [4:0] \$70 ;
  wire [45:0] \$71 ;
  wire \$72 ;
  wire \$73 ;
  wire \$74 ;
  wire \$75 ;
  wire \$76 ;
  wire \$77 ;
  wire \$78 ;
  reg \$79 ;
  wire \$8 ;
  reg \$80 ;
  reg [4:0] \$81 ;
  reg \$82 ;
  reg \$83 ;
  reg \$84 ;
  reg [31:0] \$85 ;
  reg [15:0] \$86 ;
  reg [14:0] \$87 ;
  reg [4:0] \$88 ;
  reg [95:0] \$89 ;
  wire [22:0] \$9 ;
  reg [31:0] \$90 ;
  reg \$91 ;
  reg [31:0] \$92 ;
  reg [95:0] \$93 ;
  reg [31:0] \$94 ;
  reg [12:0] \$95 ;
  reg [7:0] \$96 ;
  reg [3:0] \$97 ;
  reg [14:0] \$98 ;
  reg [95:0] \$99 ;
  (* src = "/home/runner/workspace/hardware/call.py:18" *)
  output call_busy;
  wire call_busy;
  (* src = "/home/runner/workspace/hardware/call.py:19" *)
  wire call_complete;
  (* src = "/home/runner/workspace/hardware/call.py:122" *)
  output call_fault;
  reg call_fault = 1'h0;
  (* src = "/home/runner/workspace/hardware/call.py:16" *)
  wire [14:0] call_imm;
  (* src = "/home/runner/workspace/hardware/call.py:121" *)
  reg [14:0] call_imm_latched = 15'h0000;
  (* src = "/home/runner/workspace/hardware/call.py:42" *)
  output call_normal_complete;
  wire call_normal_complete;
  (* src = "/home/runner/workspace/hardware/call.py:13" *)
  input call_start;
  wire call_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [4:0] call_state = 5'h00;
  (* src = "/home/runner/workspace/hardware/call.py:164" *)
  reg [31:0] callee_egt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:254" *)
  wire [31:0] callee_ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/call.py:68" *)
  input [14:0] caller_pc;
  wire [14:0] caller_pc;
  (* src = "/home/runner/workspace/hardware/call.py:263" *)
  reg [7:0] cc_reg = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/call.py:93" *)
  output [31:0] code_hi_out;
  wire [31:0] code_hi_out;
  (* src = "/home/runner/workspace/hardware/call.py:92" *)
  output [31:0] code_lo_out;
  wire [31:0] code_lo_out;
  (* src = "/home/runner/workspace/hardware/call.py:197" *)
  wire cr12_null;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  input [95:0] cr12_thread;
  wire [95:0] cr12_thread;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [31:0] \cr12_thread.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire \cr12_thread.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire \cr12_thread.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [8:0] \cr12_thread.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [1:0] \cr12_thread.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [2:0] \cr12_thread.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [15:0] \cr12_thread.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [31:0] \cr12_thread.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:74" *)
  wire [31:0] \cr12_thread.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  input [95:0] cr14_code;
  wire [95:0] cr14_code;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [31:0] \cr14_code.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire \cr14_code.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire \cr14_code.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [8:0] \cr14_code.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [1:0] \cr14_code.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [2:0] \cr14_code.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [15:0] \cr14_code.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [31:0] \cr14_code.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:60" *)
  wire [31:0] \cr14_code.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  reg [95:0] cr14_latched = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire [31:0] \cr14_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire \cr14_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire \cr14_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire [8:0] \cr14_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire [1:0] \cr14_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire [2:0] \cr14_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire [15:0] \cr14_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire [31:0] \cr14_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  wire [31:0] \cr14_latched.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [95:0] cr14_with_limit;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [31:0] \cr14_with_limit.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire \cr14_with_limit.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire \cr14_with_limit.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [8:0] \cr14_with_limit.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [1:0] \cr14_with_limit.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [2:0] \cr14_with_limit.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [15:0] \cr14_with_limit.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [31:0] \cr14_with_limit.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:304" *)
  wire [31:0] \cr14_with_limit.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [95:0] cr14_with_m;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [31:0] \cr14_with_m.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire \cr14_with_m.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire \cr14_with_m.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [8:0] \cr14_with_m.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [1:0] \cr14_with_m.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [2:0] \cr14_with_m.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [15:0] \cr14_with_m.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [31:0] \cr14_with_m.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:269" *)
  wire [31:0] \cr14_with_m.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:57" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:189" *)
  wire cr5_has_r;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  input [95:0] cr5_heap;
  wire [95:0] cr5_heap;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [31:0] \cr5_heap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire \cr5_heap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire \cr5_heap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [8:0] \cr5_heap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [1:0] \cr5_heap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [2:0] \cr5_heap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [15:0] \cr5_heap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [31:0] \cr5_heap.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:64" *)
  wire [31:0] \cr5_heap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:188" *)
  wire cr5_null;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [95:0] cr6_adjusted;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [31:0] \cr6_adjusted.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire \cr6_adjusted.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire \cr6_adjusted.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [8:0] \cr6_adjusted.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [1:0] \cr6_adjusted.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [2:0] \cr6_adjusted.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [15:0] \cr6_adjusted.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [31:0] \cr6_adjusted.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:334" *)
  wire [31:0] \cr6_adjusted.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  reg [95:0] cr6_latched = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire [31:0] \cr6_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire \cr6_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire \cr6_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire [8:0] \cr6_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire [1:0] \cr6_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire [2:0] \cr6_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire [15:0] \cr6_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire [31:0] \cr6_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  wire [31:0] \cr6_latched.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:85" *)
  output [11:0] cr_b_clear_mask;
  reg [11:0] cr_b_clear_mask;
  (* src = "/home/runner/workspace/hardware/call.py:86" *)
  output [11:0] cr_null_mask;
  reg [11:0] cr_null_mask;
  (* src = "/home/runner/workspace/hardware/call.py:131" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:25" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:14" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/call.py:133" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:27" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:132" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:262" *)
  reg [12:0] cw_reg = 13'h0000;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/call.py:122" *)
  wire fault_latched;
  (* src = "/home/runner/workspace/hardware/call.py:123" *)
  output [4:0] fault_type;
  reg [4:0] fault_type = 5'h00;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/call.py:123" *)
  wire [4:0] fault_type_latched;
  (* src = "/home/runner/workspace/hardware/call.py:181" *)
  wire [31:0] frame_word;
  (* src = "/home/runner/workspace/hardware/call.py:15" *)
  wire [15:0] index;
  (* src = "/home/runner/workspace/hardware/call.py:108" *)
  output lazy_load_irq;
  wire lazy_load_irq;
  (* src = "/home/runner/workspace/hardware/call.py:109" *)
  output [15:0] lazy_load_ns_slot;
  wire [15:0] lazy_load_ns_slot;
  (* src = "/home/runner/workspace/hardware/call.py:131" *)
  wire [3:0] local_cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/call.py:133" *)
  wire [3:0] local_cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [95:0] local_cr_wr_data;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [31:0] \local_cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire \local_cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire \local_cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [8:0] \local_cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [1:0] \local_cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [2:0] \local_cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [15:0] \local_cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [31:0] \local_cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:134" *)
  wire [31:0] \local_cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:132" *)
  wire local_cr_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:136" *)
  wire [31:0] local_mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/call.py:137" *)
  wire [31:0] local_mem_wr_data;
  (* src = "/home/runner/workspace/hardware/call.py:138" *)
  wire local_mem_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:265" *)
  reg [14:0] lumpSize_reg = 15'h0000;
  (* src = "/home/runner/workspace/hardware/call.py:259" *)
  reg [31:0] lump_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:17" *)
  wire [15:0] mask;
  (* src = "/home/runner/workspace/hardware/call.py:120" *)
  reg [15:0] mask_latched = 16'h0000;
  (* src = "/home/runner/workspace/hardware/call.py:46" *)
  output [31:0] mem_rd_addr;
  reg [31:0] mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/call.py:48" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/call.py:47" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/call.py:49" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/call.py:136" *)
  output [31:0] mem_wr_addr;
  reg [31:0] mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/call.py:137" *)
  output [31:0] mem_wr_data;
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/call.py:138" *)
  output mem_wr_en;
  reg mem_wr_en;
  (* src = "/home/runner/workspace/hardware/call.py:128" *)
  reg [31:0] method_entry_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:99" *)
  output [31:0] mgt_gt_lat;
  reg [31:0] mgt_gt_lat = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/call.py:99" *)
  wire [31:0] mgt_gt_word;
  (* src = "/home/runner/workspace/hardware/call.py:172" *)
  output [31:0] mgt_ns_authority;
  reg [31:0] mgt_ns_authority = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:249" *)
  wire [31:0] mgt_ns_entry_base;
  (* src = "/home/runner/workspace/hardware/call.py:173" *)
  output [31:0] mgt_ns_integrity;
  reg [31:0] mgt_ns_integrity = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:171" *)
  output [31:0] mgt_ns_location;
  reg [31:0] mgt_ns_location = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:174" *)
  output [31:0] mgt_ns_seals;
  reg [31:0] mgt_ns_seals = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:98" *)
  output mgt_set_trigger;
  wire mgt_set_trigger;
  (* src = "/home/runner/workspace/hardware/call.py:32" *)
  wire [3:0] mload_cr_dst;
  (* src = "/home/runner/workspace/hardware/call.py:31" *)
  wire [3:0] mload_cr_src;
  (* src = "/home/runner/workspace/hardware/call.py:34" *)
  wire mload_direct;
  (* src = "/home/runner/workspace/hardware/call.py:35" *)
  wire [31:0] mload_direct_gt;
  (* src = "/home/runner/workspace/hardware/call.py:38" *)
  input mload_done;
  wire mload_done;
  (* src = "/home/runner/workspace/hardware/call.py:32" *)
  output [3:0] mload_dst;
  wire [3:0] mload_dst;
  (* src = "/home/runner/workspace/hardware/call.py:39" *)
  input mload_fault;
  wire mload_fault;
  (* src = "/home/runner/workspace/hardware/call.py:40" *)
  input [4:0] mload_fault_type;
  wire [4:0] mload_fault_type;
  (* src = "/home/runner/workspace/hardware/call.py:33" *)
  output [15:0] mload_index;
  wire [15:0] mload_index;
  (* src = "/home/runner/workspace/hardware/call.py:33" *)
  wire [15:0] \mload_index$24 ;
  (* src = "/home/runner/workspace/hardware/call.py:36" *)
  wire mload_m_elevated;
  (* src = "/home/runner/workspace/hardware/call.py:31" *)
  output [3:0] mload_src;
  wire [3:0] mload_src;
  (* src = "/home/runner/workspace/hardware/call.py:124" *)
  output mload_start;
  reg mload_start = 1'h0;
  (* src = "/home/runner/workspace/hardware/call.py:264" *)
  reg [3:0] n_minus_6_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/call.py:43" *)
  output [31:0] nia_computed;
  wire [31:0] nia_computed;
  (* src = "/home/runner/workspace/hardware/call.py:42" *)
  wire nia_set;
  (* src = "/home/runner/workspace/hardware/call.py:43" *)
  wire [31:0] nia_value;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/call.py:172" *)
  wire [31:0] ns_auth_lat;
  (* src = "/home/runner/workspace/hardware/call.py:288" *)
  wire [31:0] ns_base_from_cr14;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/call.py:173" *)
  wire [31:0] ns_int_lat;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/call.py:171" *)
  wire [31:0] ns_loc_lat;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/call.py:174" *)
  wire [31:0] ns_seal_lat;
  (* src = "/home/runner/workspace/hardware/call.py:118" *)
  reg phase = 1'h0;
  input [18:0] \port$5930$0 ;
  wire [18:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/call.py:140" *)
  reg [31:0] sp_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/call.py:153" *)
  wire [14:0] sp_max;
  (* src = "/home/runner/workspace/hardware/call.py:154" *)
  wire [14:0] sp_min;
  (* src = "/home/runner/workspace/hardware/call.py:155" *)
  wire [14:0] sp_min_base;
  (* src = "/home/runner/workspace/hardware/call.py:205" *)
  wire src_in_range;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  reg [95:0] src_reg_latched = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire [31:0] \src_reg_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire \src_reg_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire \src_reg_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire [8:0] \src_reg_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire [1:0] \src_reg_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire [2:0] \src_reg_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire [15:0] \src_reg_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire [31:0] \src_reg_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  wire [31:0] \src_reg_latched.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/call.py:125" *)
  reg sub_done_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/call.py:126" *)
  reg sub_fault_latched = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/call.py:124" *)
  wire sub_start_reg;
  (* src = "/home/runner/workspace/hardware/call.py:146" *)
  wire [14:0] thr_lump_sz;
  (* src = "/home/runner/workspace/hardware/call.py:71" *)
  wire [31:0] thread_base;
  (* src = "/home/runner/workspace/hardware/call.py:80" *)
  input [31:0] thread_hdr;
  wire [31:0] thread_hdr;
  (* src = "/home/runner/workspace/hardware/call.py:129" *)
  reg use_method_table = 1'h0;
  assign \$1  = thread_hdr[26:23] + (* src = "/home/runner/workspace/hardware/call.py:147" *) 3'h6;
  assign \$2  = 1'h1 << (* src = "/home/runner/workspace/hardware/call.py:147" *) \$1 ;
  assign \$3  = \$2 [14:0] - (* src = "/home/runner/workspace/hardware/call.py:157" *) 4'hc;
  assign \$4  = $signed(\$3 ) - (* src = "/home/runner/workspace/hardware/call.py:157" *) $signed(2'h1);
  assign \$5  = \$2 [14:0] - (* src = "/home/runner/workspace/hardware/call.py:158" *) 4'ha;
  assign \$6  = \$5 [14:0] - (* src = "/home/runner/workspace/hardware/call.py:159" *) thread_hdr[22:10];
  assign \$7  = caller_pc + (* src = "/home/runner/workspace/hardware/call.py:183" *) 1'h1;
  assign cr5_null = ! (* src = "/home/runner/workspace/hardware/call.py:191" *) cr5_heap[26:25];
  assign \$8  = ~ (* src = "/home/runner/workspace/hardware/call.py:192" *) cr5_heap[27];
  assign cr5_has_r = \$8  & (* src = "/home/runner/workspace/hardware/call.py:192" *) cr5_heap[28];
  assign cr12_null = ! (* src = "/home/runner/workspace/hardware/call.py:198" *) cr12_thread[26:25];
  assign src_in_range = \port$5930$0 [18:15] <= (* src = "/home/runner/workspace/hardware/call.py:206" *) 4'hb;
  assign mload_src = phase ? (* src = "/home/runner/workspace/hardware/call.py:216" *) 4'h6 : \port$5930$0 [18:15];
  assign mload_dst = phase ? (* src = "/home/runner/workspace/hardware/call.py:217" *) 4'he : 4'h6;
  assign \$10  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/call.py:251" *) \$9 ;
  assign \$12  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/call.py:256" *) \$11 ;
  assign \$13  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/call.py:281" *) 3'h4;
  assign \$14  = ! (* src = "/home/runner/workspace/hardware/call.py:297" *) call_imm_latched;
  assign \$15  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/call.py:298" *) 3'h4;
  assign \$17  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/call.py:299" *) \$16 ;
  assign \$18  = \$14  ? (* src = "/home/runner/workspace/hardware/call.py:297" *) { 3'h0, \$15  } : \$17 ;
  assign \$19  = cw_reg - (* src = "/home/runner/workspace/hardware/call.py:317" *) 1'h1;
  assign \$20  = lumpSize_reg - (* src = "/home/runner/workspace/hardware/call.py:349" *) cc_reg;
  assign \$22  = $signed({ 1'h0, cr14_latched[63:32] }) + (* src = "/home/runner/workspace/hardware/call.py:349" *) $signed(\$21 );
  assign \$23  = cc_reg - (* src = "/home/runner/workspace/hardware/call.py:351" *) 1'h1;
  assign \$24  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/call.py:366" *) 3'h4;
  assign \$26  = \$24 [31:0] + (* src = "/home/runner/workspace/hardware/call.py:367" *) \$25 ;
  assign \$28  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/call.py:498" *) \$27 ;
  assign \$29  = ! (* src = "/home/runner/workspace/hardware/call.py:522" *) cc_reg;
  assign \$30  = ~ (* src = "/home/runner/workspace/hardware/call.py:550" *) mask_latched[11:0];
  assign \$31  = sp_latched - (* src = "/home/runner/workspace/hardware/stack_frame.py:44" *) 1'h1;
  assign \$33  = $signed({ 1'h0, cr12_thread[63:32] }) + (* src = "/home/runner/workspace/hardware/stack_frame.py:44" *) $signed(\$32 );
  assign \$35  = cr12_thread[63:32] + (* src = "/home/runner/workspace/hardware/stack_frame.py:40" *) \$34 ;
  assign \$36  = sp_latched - (* src = "/home/runner/workspace/hardware/call.py:625" *) 2'h2;
  assign \$37  = \$10 [31:0] + (* src = "/home/runner/workspace/hardware/call.py:656" *) 3'h4;
  assign \$38  = \$10 [31:0] + (* src = "/home/runner/workspace/hardware/call.py:666" *) 4'h8;
  assign \$39  = \$10 [31:0] + (* src = "/home/runner/workspace/hardware/call.py:676" *) 4'hc;
  assign call_busy = ~ (* src = "/home/runner/workspace/hardware/call.py:697" *) \$40 ;
  assign call_complete = call_normal_complete | (* src = "/home/runner/workspace/hardware/call.py:698" *) mgt_set_trigger;
  assign \$40  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) call_state;
  assign \$41  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$42  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$43  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$44  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$45  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$46  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$47  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$48  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$49  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$50  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$51  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign lazy_load_irq = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$52  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$53  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'he;
  assign \$54  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hf;
  assign \$55  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h10;
  assign \$56  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h11;
  assign \$57  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h12;
  assign \$58  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h13;
  assign \$59  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h14;
  assign \$60  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h15;
  assign \$61  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h16;
  assign \$62  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h17;
  assign call_normal_complete = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h18;
  assign \$63  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h19;
  assign \$64  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1a;
  assign \$65  = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1b;
  assign mgt_set_trigger = call_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1c;
  assign \$66  = ~ (* src = "/home/runner/workspace/hardware/call.py:388" *) src_in_range;
  assign \$67  = src_reg_latched[26:25] == (* src = "/home/runner/workspace/hardware/call.py:400" *) 2'h3;
  assign \$68  = src_reg_latched[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) src_reg_latched[30];
  assign \$69  = ~ (* src = "/home/runner/workspace/hardware/call.py:406" *) \$68 ;
  assign \$70  = mem_rd_data[26:23] + (* src = "/home/runner/workspace/hardware/call.py:481" *) 3'h6;
  assign \$71  = 1'h1 << (* src = "/home/runner/workspace/hardware/call.py:481" *) \$70 ;
  assign \$72  = ! (* src = "/home/runner/workspace/hardware/call.py:485" *) mem_rd_data[22:10];
  assign \$73  = call_imm_latched > (* src = "/home/runner/workspace/hardware/call.py:487" *) 1'h0;
  assign \$74  = ! (* src = "/home/runner/workspace/hardware/call.py:503" *) mem_rd_data;
  assign \$75  = ! (* src = "/home/runner/workspace/hardware/call.py:522" *) cc_reg;
  assign \$76  = ~ (* src = "/home/runner/workspace/hardware/call.py:558" *) cr5_has_r;
  assign \$77  = sp_latched > (* src = "/home/runner/workspace/hardware/call.py:584" *) \$4 [14:0];
  assign \$78  = sp_latched < (* src = "/home/runner/workspace/hardware/call.py:590" *) \$6 [14:0];
  (* src = "/home/runner/workspace/hardware/call.py:118" *)
  always @(posedge clk)
    phase <= \$79 ;
  (* src = "/home/runner/workspace/hardware/call.py:122" *)
  always @(posedge clk)
    call_fault <= \$80 ;
  (* src = "/home/runner/workspace/hardware/call.py:123" *)
  always @(posedge clk)
    fault_type <= \$81 ;
  (* src = "/home/runner/workspace/hardware/call.py:125" *)
  always @(posedge clk)
    sub_done_latched <= \$82 ;
  (* src = "/home/runner/workspace/hardware/call.py:126" *)
  always @(posedge clk)
    sub_fault_latched <= \$83 ;
  (* src = "/home/runner/workspace/hardware/call.py:129" *)
  always @(posedge clk)
    use_method_table <= \$84 ;
  (* src = "/home/runner/workspace/hardware/call.py:128" *)
  always @(posedge clk)
    method_entry_reg <= \$85 ;
  (* src = "/home/runner/workspace/hardware/call.py:120" *)
  always @(posedge clk)
    mask_latched <= \$86 ;
  (* src = "/home/runner/workspace/hardware/call.py:121" *)
  always @(posedge clk)
    call_imm_latched <= \$87 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    call_state <= \$88 ;
  (* src = "/home/runner/workspace/hardware/call.py:119" *)
  always @(posedge clk)
    src_reg_latched <= \$89 ;
  (* src = "/home/runner/workspace/hardware/call.py:169" *)
  always @(posedge clk)
    mgt_gt_lat <= \$90 ;
  (* src = "/home/runner/workspace/hardware/call.py:124" *)
  always @(posedge clk)
    mload_start <= \$91 ;
  (* src = "/home/runner/workspace/hardware/call.py:164" *)
  always @(posedge clk)
    callee_egt_latched <= \$92 ;
  (* src = "/home/runner/workspace/hardware/call.py:201" *)
  always @(posedge clk)
    cr14_latched <= \$93 ;
  (* src = "/home/runner/workspace/hardware/call.py:259" *)
  always @(posedge clk)
    lump_reg <= \$94 ;
  (* src = "/home/runner/workspace/hardware/call.py:262" *)
  always @(posedge clk)
    cw_reg <= \$95 ;
  (* src = "/home/runner/workspace/hardware/call.py:263" *)
  always @(posedge clk)
    cc_reg <= \$96 ;
  (* src = "/home/runner/workspace/hardware/call.py:264" *)
  always @(posedge clk)
    n_minus_6_reg <= \$97 ;
  (* src = "/home/runner/workspace/hardware/call.py:265" *)
  always @(posedge clk)
    lumpSize_reg <= \$98 ;
  (* src = "/home/runner/workspace/hardware/call.py:324" *)
  always @(posedge clk)
    cr6_latched <= \$99 ;
  (* src = "/home/runner/workspace/hardware/call.py:140" *)
  always @(posedge clk)
    sp_latched <= \$100 ;
  (* src = "/home/runner/workspace/hardware/call.py:171" *)
  always @(posedge clk)
    mgt_ns_location <= \$101 ;
  (* src = "/home/runner/workspace/hardware/call.py:172" *)
  always @(posedge clk)
    mgt_ns_authority <= \$102 ;
  (* src = "/home/runner/workspace/hardware/call.py:173" *)
  always @(posedge clk)
    mgt_ns_integrity <= \$103 ;
  (* src = "/home/runner/workspace/hardware/call.py:174" *)
  always @(posedge clk)
    mgt_ns_seals <= \$104 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    cr_null_mask = 12'h000;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          cr_null_mask = mask_latched[11:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    cr_b_clear_mask = 12'h000;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          cr_b_clear_mask = \$30 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    cr_rd_addr = 4'h0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          cr_rd_addr = \port$5930$0 [18:15];
      5'h03:
          cr_rd_addr = \port$5930$0 [18:15];
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          cr_rd_addr = 4'h6;
      5'h08:
          /* empty */;
      5'h09:
          cr_rd_addr = 4'he;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          (* full_case = 32'd1 *)
          if (\$29 ) begin
          end else begin
            cr_rd_addr = 4'h6;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    cr_wr_addr = 4'h0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          cr_wr_addr = 4'he;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          cr_wr_addr = 4'he;
      5'h0f:
          if (\$29 ) begin
            cr_wr_addr = 4'h6;
          end
      5'h11:
          cr_wr_addr = 4'h6;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          cr_wr_data = cr14_with_m;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          cr_wr_data = cr14_with_limit;
      5'h0f:
          if (\$29 ) begin
            cr_wr_data = 96'h000000000000000000000000;
          end
      5'h11:
          cr_wr_data = cr6_adjusted;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    cr_wr_en = 1'h0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          cr_wr_en = 1'h1;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          cr_wr_en = 1'h1;
      5'h0f:
          if (\$29 ) begin
            cr_wr_en = 1'h1;
          end
      5'h11:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    mem_rd_addr = 32'd0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          mem_rd_addr = cr14_latched[63:32];
      5'h0d:
          mem_rd_addr = \$28 [31:0];
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          mem_rd_addr = cr5_heap[63:32];
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h02:
          /* empty */;
      5'h05:
          mem_rd_addr = \$10 [31:0];
      5'h19:
          mem_rd_addr = \$37 [31:0];
      5'h1a:
          mem_rd_addr = \$38 [31:0];
      5'h1b:
          mem_rd_addr = \$39 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    mem_rd_en = 1'h0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          mem_rd_en = 1'h1;
      5'h0d:
          mem_rd_en = 1'h1;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          mem_rd_en = 1'h1;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h02:
          /* empty */;
      5'h05:
          mem_rd_en = 1'h1;
      5'h19:
          mem_rd_en = 1'h1;
      5'h1a:
          mem_rd_en = 1'h1;
      5'h1b:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    mem_wr_addr = 32'd0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          mem_wr_addr = \$33 [31:0];
      5'h16:
          mem_wr_addr = \$35 [31:0];
      5'h17:
          mem_wr_addr = cr5_heap[63:32];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    mem_wr_data = 32'd0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          mem_wr_data = callee_egt_latched;
      5'h16:
          mem_wr_data = { 1'h1, \$7 [14:0], sp_latched[15:0] };
      5'h17:
          mem_wr_data = \$36 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    mem_wr_en = 1'h0;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          mem_wr_en = 1'h1;
      5'h16:
          mem_wr_en = 1'h1;
      5'h17:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$79  = phase;
    casez (call_state)
      5'h00:
          \$79  = 1'h0;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          \$79  = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$80  = call_fault;
    casez (call_state)
      5'h00:
          \$80  = 1'h0;
      5'h01:
          if (\$66 ) begin
            \$80  = 1'h1;
          end
      5'h03:
          /* empty */;
      5'h04:
          if (\$67 ) begin
          end else if (\$69 ) begin
            \$80  = 1'h1;
          end
      5'h06:
          if (mload_fault) begin
            \$80  = 1'h1;
          end
      5'h07:
          /* empty */;
      5'h08:
          if (mload_fault) begin
            \$80  = 1'h1;
          end
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          if (mem_rd_valid) begin
            if (\$74 ) begin
              \$80  = 1'h1;
            end
          end
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          if (cr5_null) begin
            \$80  = 1'h1;
          end else if (\$76 ) begin
            \$80  = 1'h1;
          end else if (cr12_null) begin
            \$80  = 1'h1;
          end
      5'h13:
          /* empty */;
      5'h14:
          if (\$77 ) begin
            \$80  = 1'h1;
          end else if (\$78 ) begin
            \$80  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$81  = fault_type;
    casez (call_state)
      5'h00:
          \$81  = 5'h00;
      5'h01:
          if (\$66 ) begin
            \$81  = 5'h06;
          end
      5'h03:
          /* empty */;
      5'h04:
          if (\$67 ) begin
          end else if (\$69 ) begin
            \$81  = 5'h06;
          end
      5'h06:
          if (mload_fault) begin
            \$81  = mload_fault_type;
          end
      5'h07:
          /* empty */;
      5'h08:
          if (mload_fault) begin
            \$81  = mload_fault_type;
          end
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          if (mem_rd_valid) begin
            if (\$74 ) begin
              \$81  = 5'h06;
            end
          end
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          if (cr5_null) begin
            \$81  = 5'h07;
          end else if (\$76 ) begin
            \$81  = 5'h01;
          end else if (cr12_null) begin
            \$81  = 5'h07;
          end
      5'h13:
          /* empty */;
      5'h14:
          if (\$77 ) begin
            \$81  = 5'h12;
          end else if (\$78 ) begin
            \$81  = 5'h10;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$82  = sub_done_latched;
    casez (call_state)
      5'h00:
          \$82  = 1'h0;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          if (mload_done) begin
            \$82  = 1'h1;
          end
      5'h07:
          \$82  = 1'h0;
      5'h08:
          if (mload_done) begin
            \$82  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$83  = sub_fault_latched;
    casez (call_state)
      5'h00:
          \$83  = 1'h0;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          if (mload_fault) begin
            \$83  = 1'h1;
          end
      5'h07:
          \$83  = 1'h0;
      5'h08:
          if (mload_fault) begin
            \$83  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$84  = use_method_table;
    casez (call_state)
      5'h00:
          \$84  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$85  = method_entry_reg;
    casez (call_state)
      5'h00:
          \$85  = 32'd0;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          if (mem_rd_valid) begin
            \$85  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$86  = mask_latched;
    casez (call_state)
      5'h00:
          if (call_start) begin
            \$86  = 16'h0000;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$87  = call_imm_latched;
    casez (call_state)
      5'h00:
          if (call_start) begin
            \$87  = \port$5930$0 [14:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$88  = call_state;
    casez (call_state)
      5'h00:
          if (call_start) begin
            \$88  = 5'h01;
          end
      5'h01:
          (* full_case = 32'd1 *)
          if (\$66 ) begin
            \$88  = 5'h02;
          end else begin
            \$88  = 5'h03;
          end
      5'h03:
          \$88  = 5'h04;
      5'h04:
          (* full_case = 32'd1 *)
          if (\$67 ) begin
            \$88  = 5'h05;
          end else if (\$69 ) begin
            \$88  = 5'h02;
          end else begin
            \$88  = 5'h06;
          end
      5'h06:
          if (sub_fault_latched) begin
            \$88  = 5'h02;
          end else if (sub_done_latched) begin
            \$88  = 5'h07;
          end
      5'h07:
          \$88  = 5'h08;
      5'h08:
          if (sub_fault_latched) begin
            \$88  = 5'h02;
          end else if (sub_done_latched) begin
            \$88  = 5'h09;
          end
      5'h09:
          \$88  = 5'h0a;
      5'h0a:
          \$88  = 5'h0b;
      5'h0b:
          if (mem_rd_valid) begin
            (* full_case = 32'd1 *)
            if (\$72 ) begin
              \$88  = 5'h0c;
            end else if (\$73 ) begin
              \$88  = 5'h0d;
            end else begin
              \$88  = 5'h0e;
            end
          end
      5'h0d:
          if (mem_rd_valid) begin
            (* full_case = 32'd1 *)
            if (\$74 ) begin
              \$88  = 5'h02;
            end else begin
              \$88  = 5'h0e;
            end
          end
      5'h0e:
          \$88  = 5'h0f;
      5'h0f:
          (* full_case = 32'd1 *)
          if (\$75 ) begin
            \$88  = 5'h10;
          end else begin
            \$88  = 5'h11;
          end
      5'h11:
          \$88  = 5'h10;
      5'h10:
          \$88  = 5'h12;
      5'h12:
          (* full_case = 32'd1 *)
          if (cr5_null) begin
            \$88  = 5'h02;
          end else if (\$76 ) begin
            \$88  = 5'h02;
          end else if (cr12_null) begin
            \$88  = 5'h02;
          end else begin
            \$88  = 5'h13;
          end
      5'h13:
          if (mem_rd_valid) begin
            \$88  = 5'h14;
          end
      5'h14:
          (* full_case = 32'd1 *)
          if (\$77 ) begin
            \$88  = 5'h02;
          end else if (\$78 ) begin
            \$88  = 5'h02;
          end else begin
            \$88  = 5'h15;
          end
      5'h15:
          \$88  = 5'h16;
      5'h16:
          \$88  = 5'h17;
      5'h17:
          \$88  = 5'h18;
      5'h18:
          \$88  = 5'h00;
      5'h02:
          \$88  = 5'h00;
      5'h05:
          if (mem_rd_valid) begin
            \$88  = 5'h19;
          end
      5'h19:
          if (mem_rd_valid) begin
            \$88  = 5'h1a;
          end
      5'h1a:
          if (mem_rd_valid) begin
            \$88  = 5'h1b;
          end
      5'h1b:
          if (mem_rd_valid) begin
            \$88  = 5'h1c;
          end
      5'h1c:
          \$88  = 5'h00;
      5'h0c:
          \$88  = 5'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$89  = src_reg_latched;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          \$89  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$90  = mgt_gt_lat;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          if (\$67 ) begin
            \$90  = src_reg_latched[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$91  = mload_start;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          (* full_case = 32'd1 *)
          if (\$67 ) begin
          end else if (\$69 ) begin
          end else begin
            \$91  = 1'h1;
          end
      5'h06:
          \$91  = 1'h0;
      5'h07:
          \$91  = 1'h1;
      5'h08:
          \$91  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$92  = callee_egt_latched;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          \$92  = cr_rd_data[31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$93  = cr14_latched;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          \$93  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$94  = lump_reg;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (mem_rd_valid) begin
            \$94  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$95  = cw_reg;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (mem_rd_valid) begin
            \$95  = mem_rd_data[22:10];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$96  = cc_reg;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (mem_rd_valid) begin
            \$96  = mem_rd_data[7:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$97  = n_minus_6_reg;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (mem_rd_valid) begin
            \$97  = mem_rd_data[26:23];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$98  = lumpSize_reg;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (mem_rd_valid) begin
            \$98  = \$71 [14:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$99  = cr6_latched;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          (* full_case = 32'd1 *)
          if (\$75 ) begin
          end else begin
            \$99  = cr_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$100  = sp_latched;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          if (mem_rd_valid) begin
            \$100  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$101  = mgt_ns_location;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h02:
          /* empty */;
      5'h05:
          if (mem_rd_valid) begin
            \$101  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$102  = mgt_ns_authority;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h02:
          /* empty */;
      5'h05:
          /* empty */;
      5'h19:
          if (mem_rd_valid) begin
            \$102  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$103  = mgt_ns_integrity;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h02:
          /* empty */;
      5'h05:
          /* empty */;
      5'h19:
          /* empty */;
      5'h1a:
          if (mem_rd_valid) begin
            \$103  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$44 ) begin end
    \$104  = mgt_ns_seals;
    casez (call_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h11:
          /* empty */;
      5'h10:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h02:
          /* empty */;
      5'h05:
          /* empty */;
      5'h19:
          /* empty */;
      5'h1a:
          /* empty */;
      5'h1b:
          if (mem_rd_valid) begin
            \$104  = mem_rd_data;
          end
    endcase
  end
  assign thr_lump_sz = \$2 [14:0];
  assign sp_max = \$4 [14:0];
  assign sp_min_base = \$5 [14:0];
  assign sp_min = \$6 [14:0];
  assign frame_word = { 1'h1, \$7 [14:0], sp_latched[15:0] };
  assign cr_src = \port$5930$0 [18:15];
  assign index = 16'h0000;
  assign sub_start_reg = mload_start;
  assign mload_cr_src = mload_src;
  assign mload_cr_dst = mload_dst;
  assign \mload_index$24  = mload_index;
  assign mload_direct = 1'h0;
  assign mload_m_elevated = 1'h1;
  assign mload_direct_gt = 32'd0;
  assign local_cr_wr_addr = cr_wr_addr;
  assign local_cr_wr_data = cr_wr_data;
  assign local_cr_wr_en = cr_wr_en;
  assign local_cr_rd_addr = cr_rd_addr;
  assign local_mem_wr_addr = mem_wr_addr;
  assign local_mem_wr_data = mem_wr_data;
  assign local_mem_wr_en = mem_wr_en;
  assign mgt_ns_entry_base = \$10 [31:0];
  assign callee_ns_entry_addr = \$12 [31:0];
  assign ns_base_from_cr14 = cr14_latched[63:32];
  assign thread_base = cr12_thread[63:32];
  assign fault_latched = call_fault;
  assign fault_type_latched = fault_type;
  assign nia_set = call_normal_complete;
  assign nia_value = \$18 [31:0];
  assign mgt_gt_word = mgt_gt_lat;
  assign ns_loc_lat = mgt_ns_location;
  assign ns_auth_lat = mgt_ns_authority;
  assign ns_int_lat = mgt_ns_integrity;
  assign ns_seal_lat = mgt_ns_seals;
  
  assign mask = 16'h0000;
  assign call_imm = \port$5930$0 [14:0];
  assign nia_computed = \$18 [31:0];
  assign code_lo_out = \$24 [31:0];
  assign code_hi_out = \$26 [31:0];
  assign lazy_load_ns_slot = callee_egt_latched[15:0];
  assign \cr5_heap.word0_gt  = cr5_heap[31:0];
  assign \cr5_heap.word0_gt.slot_id  = cr5_heap[15:0];
  assign \cr5_heap.word0_gt.gt_seq  = cr5_heap[24:16];
  assign \cr5_heap.word0_gt.gt_type  = cr5_heap[26:25];
  assign \cr5_heap.word0_gt.dom  = cr5_heap[27];
  assign \cr5_heap.word0_gt.perm  = cr5_heap[30:28];
  assign \cr5_heap.word0_gt.b_flag  = cr5_heap[31];
  assign \cr5_heap.word1_location  = cr5_heap[63:32];
  assign \cr5_heap.word2_w2  = cr5_heap[95:64];
  assign \cr12_thread.word0_gt  = cr12_thread[31:0];
  assign \cr12_thread.word0_gt.slot_id  = cr12_thread[15:0];
  assign \cr12_thread.word0_gt.gt_seq  = cr12_thread[24:16];
  assign \cr12_thread.word0_gt.gt_type  = cr12_thread[26:25];
  assign \cr12_thread.word0_gt.dom  = cr12_thread[27];
  assign \cr12_thread.word0_gt.perm  = cr12_thread[30:28];
  assign \cr12_thread.word0_gt.b_flag  = cr12_thread[31];
  assign \cr12_thread.word1_location  = cr12_thread[63:32];
  assign \cr12_thread.word2_w2  = cr12_thread[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \local_cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \local_cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \local_cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \local_cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \local_cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \local_cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \local_cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \local_cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \local_cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr14_code.word0_gt  = cr14_code[31:0];
  assign \cr14_code.word0_gt.slot_id  = cr14_code[15:0];
  assign \cr14_code.word0_gt.gt_seq  = cr14_code[24:16];
  assign \cr14_code.word0_gt.gt_type  = cr14_code[26:25];
  assign \cr14_code.word0_gt.dom  = cr14_code[27];
  assign \cr14_code.word0_gt.perm  = cr14_code[30:28];
  assign \cr14_code.word0_gt.b_flag  = cr14_code[31];
  assign \cr14_code.word1_location  = cr14_code[63:32];
  assign \cr14_code.word2_w2  = cr14_code[95:64];
  assign \cr14_with_m.word0_gt  = cr14_with_m[31:0];
  assign \cr14_with_m.word0_gt.slot_id  = cr14_with_m[15:0];
  assign \cr14_with_m.word0_gt.gt_seq  = cr14_with_m[24:16];
  assign \cr14_with_m.word0_gt.gt_type  = cr14_with_m[26:25];
  assign \cr14_with_m.word0_gt.dom  = cr14_with_m[27];
  assign \cr14_with_m.word0_gt.perm  = cr14_with_m[30:28];
  assign \cr14_with_m.word0_gt.b_flag  = cr14_with_m[31];
  assign \cr14_with_m.word1_location  = cr14_with_m[63:32];
  assign \cr14_with_m.word2_w2  = cr14_with_m[95:64];
  assign \cr14_latched.word0_gt  = cr14_latched[31:0];
  assign \cr14_latched.word0_gt.slot_id  = cr14_latched[15:0];
  assign \cr14_latched.word0_gt.gt_seq  = cr14_latched[24:16];
  assign \cr14_latched.word0_gt.gt_type  = cr14_latched[26:25];
  assign \cr14_latched.word0_gt.dom  = cr14_latched[27];
  assign \cr14_latched.word0_gt.perm  = cr14_latched[30:28];
  assign \cr14_latched.word0_gt.b_flag  = cr14_latched[31];
  assign \cr14_latched.word1_location  = cr14_latched[63:32];
  assign \cr14_latched.word2_w2  = cr14_latched[95:64];
  assign \cr14_with_limit.word0_gt  = cr14_with_limit[31:0];
  assign \cr14_with_limit.word0_gt.slot_id  = cr14_with_limit[15:0];
  assign \cr14_with_limit.word0_gt.gt_seq  = cr14_with_limit[24:16];
  assign \cr14_with_limit.word0_gt.gt_type  = cr14_with_limit[26:25];
  assign \cr14_with_limit.word0_gt.dom  = cr14_with_limit[27];
  assign \cr14_with_limit.word0_gt.perm  = cr14_with_limit[30:28];
  assign \cr14_with_limit.word0_gt.b_flag  = cr14_with_limit[31];
  assign \cr14_with_limit.word1_location  = cr14_with_limit[63:32];
  assign \cr14_with_limit.word2_w2  = cr14_with_limit[95:64];
  assign \cr6_adjusted.word0_gt  = cr6_adjusted[31:0];
  assign \cr6_adjusted.word0_gt.slot_id  = cr6_adjusted[15:0];
  assign \cr6_adjusted.word0_gt.gt_seq  = cr6_adjusted[24:16];
  assign \cr6_adjusted.word0_gt.gt_type  = cr6_adjusted[26:25];
  assign \cr6_adjusted.word0_gt.dom  = cr6_adjusted[27];
  assign \cr6_adjusted.word0_gt.perm  = cr6_adjusted[30:28];
  assign \cr6_adjusted.word0_gt.b_flag  = cr6_adjusted[31];
  assign \cr6_adjusted.word1_location  = cr6_adjusted[63:32];
  assign \cr6_adjusted.word2_w2  = cr6_adjusted[95:64];
  assign \cr6_latched.word0_gt  = cr6_latched[31:0];
  assign \cr6_latched.word0_gt.slot_id  = cr6_latched[15:0];
  assign \cr6_latched.word0_gt.gt_seq  = cr6_latched[24:16];
  assign \cr6_latched.word0_gt.gt_type  = cr6_latched[26:25];
  assign \cr6_latched.word0_gt.dom  = cr6_latched[27];
  assign \cr6_latched.word0_gt.perm  = cr6_latched[30:28];
  assign \cr6_latched.word0_gt.b_flag  = cr6_latched[31];
  assign \cr6_latched.word1_location  = cr6_latched[63:32];
  assign \cr6_latched.word2_w2  = cr6_latched[95:64];
  assign \src_reg_latched.word0_gt  = src_reg_latched[31:0];
  assign \src_reg_latched.word0_gt.slot_id  = src_reg_latched[15:0];
  assign \src_reg_latched.word0_gt.gt_seq  = src_reg_latched[24:16];
  assign \src_reg_latched.word0_gt.gt_type  = src_reg_latched[26:25];
  assign \src_reg_latched.word0_gt.dom  = src_reg_latched[27];
  assign \src_reg_latched.word0_gt.perm  = src_reg_latched[30:28];
  assign \src_reg_latched.word0_gt.b_flag  = src_reg_latched[31];
  assign \src_reg_latched.word1_location  = src_reg_latched[63:32];
  assign \src_reg_latched.word2_w2  = src_reg_latched[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign cr6_adjusted[95] = 1'h0;
  assign cr6_adjusted[94] = 1'h0;
  assign cr6_adjusted[93:85] = cr6_latched[93:85];
  assign cr6_adjusted[84:64] = { \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23 [8], \$23  };
  assign cr6_adjusted[63:32] = \$22 [31:0];
  assign cr6_adjusted[31] = cr6_latched[31];
  assign cr6_adjusted[30:28] = 3'h4;
  assign cr6_adjusted[27] = 1'h1;
  assign cr6_adjusted[26:25] = cr6_latched[26:25];
  assign cr6_adjusted[24:16] = cr6_latched[24:16];
  assign cr6_adjusted[15:0] = cr6_latched[15:0];
  assign cr14_with_limit[95] = 1'h0;
  assign cr14_with_limit[94] = 1'h0;
  assign cr14_with_limit[93:85] = cr14_latched[93:85];
  assign cr14_with_limit[84:64] = { \$19 [13], \$19 [13], \$19 [13], \$19 [13], \$19 [13], \$19 [13], \$19 [13], \$19  };
  assign cr14_with_limit[63:32] = cr14_with_m[63:32];
  assign cr14_with_limit[31] = cr14_with_m[31];
  assign cr14_with_limit[30:28] = cr14_with_m[30:28];
  assign cr14_with_limit[27] = cr14_with_m[27];
  assign cr14_with_limit[26:25] = cr14_with_m[26:25];
  assign cr14_with_limit[24:16] = cr14_with_m[24:16];
  assign cr14_with_limit[15:0] = cr14_with_m[15:0];
  assign cr14_with_m[95:64] = cr14_latched[95:64];
  assign cr14_with_m[63:32] = \$13 [31:0];
  assign cr14_with_m[31] = cr14_latched[31];
  assign cr14_with_m[30:28] = { 2'h2, cr14_latched[28] };
  assign cr14_with_m[27] = 1'h0;
  assign cr14_with_m[26:25] = cr14_latched[26:25];
  assign cr14_with_m[24:16] = cr14_latched[24:16];
  assign cr14_with_m[15:0] = cr14_latched[15:0];
  assign mload_index = 16'h0000;
  assign \$9  = { 3'h0, mgt_gt_lat[15:0], 4'h0 };
  assign \$11  = { 3'h0, cr14_code[15:0], 4'h0 };
  assign \$16  = { 1'h0, method_entry_reg, 2'h0 };
  assign \$21  = { \$20 [15], \$20 , 2'h0 };
  assign \$25  = { 1'h0, cw_reg, 2'h0 };
  assign \$27  = { 1'h0, call_imm_latched, 2'h0 };
  assign \$32  = { \$31 [32], \$31 , 2'h0 };
  assign \$34  = { 1'h0, sp_latched, 2'h0 };
endmodule

(* src = "/home/runner/workspace/hardware/change.py:65" *)
(* generator = "Amaranth" *)
module \top.core.u_change (clk, mem_rd_valid, change_start, m_elevated, cr_rd_data, dr_rd_data, cr_wr_addr, cr_wr_data, cr_wr_en, change_busy, nia, cr12_thread, cr15_namespace, flags, cr15_m_flag_in, m_flag_restore_en, m_flag_restore_val, cr_rd_addr, change_fault, fault_type, thread_hdr_reg, \port$5930$0 
, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$45  = 0;
  wire [16:0] \$1 ;
  wire [8:0] \$10 ;
  wire [31:0] \$11 ;
  wire \$12 ;
  wire [5:0] \$13 ;
  wire [8:0] \$14 ;
  wire [32:0] \$15 ;
  wire [32:0] \$16 ;
  wire [32:0] \$17 ;
  wire [32:0] \$18 ;
  wire \$19 ;
  wire \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  wire \$25 ;
  wire \$26 ;
  wire \$27 ;
  wire \$28 ;
  wire \$29 ;
  wire \$3 ;
  wire \$30 ;
  wire \$31 ;
  wire \$32 ;
  wire \$33 ;
  wire \$34 ;
  wire \$35 ;
  wire \$36 ;
  wire \$37 ;
  wire \$38 ;
  wire \$39 ;
  wire \$4 ;
  wire \$40 ;
  wire \$41 ;
  wire \$42 ;
  wire \$43 ;
  wire \$44 ;
  wire \$45 ;
  wire [5:0] \$46 ;
  wire \$47 ;
  wire [4:0] \$48 ;
  wire \$49 ;
  wire \$5 ;
  wire [4:0] \$50 ;
  wire \$51 ;
  reg \$52 ;
  reg [4:0] \$53 ;
  reg \$54 ;
  reg \$55 ;
  reg [15:0] \$56 ;
  reg [15:0] \$57 ;
  reg [3:0] \$58 ;
  reg [4:0] \$59 ;
  wire \$6 ;
  reg [4:0] \$60 ;
  reg [31:0] \$61 ;
  reg [95:0] \$62 ;
  reg \$63 ;
  reg [31:0] \$64 ;
  reg \$65 ;
  reg [31:0] \$66 ;
  wire \$7 ;
  wire [32:0] \$8 ;
  wire [32:0] \$9 ;
  (* src = "/home/runner/workspace/hardware/change.py:15" *)
  output change_busy;
  wire change_busy;
  (* src = "/home/runner/workspace/hardware/change.py:16" *)
  wire change_complete;
  (* src = "/home/runner/workspace/hardware/change.py:76" *)
  output change_fault;
  reg change_fault = 1'h0;
  (* src = "/home/runner/workspace/hardware/change.py:14" *)
  wire [15:0] change_mask;
  (* src = "/home/runner/workspace/hardware/change.py:11" *)
  input change_start;
  wire change_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [4:0] change_state = 5'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/change.py:115" *)
  wire cr12_null;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  input [95:0] cr12_thread;
  wire [95:0] cr12_thread;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [31:0] \cr12_thread.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire \cr12_thread.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire \cr12_thread.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [8:0] \cr12_thread.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [1:0] \cr12_thread.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [2:0] \cr12_thread.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [15:0] \cr12_thread.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [31:0] \cr12_thread.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:29" *)
  wire [31:0] \cr12_thread.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:60" *)
  input cr15_m_flag_in;
  wire cr15_m_flag_in;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [95:0] \cr15_namespace$28 ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [31:0] \cr15_namespace$28.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire \cr15_namespace$28.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire \cr15_namespace$28.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [8:0] \cr15_namespace$28.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [1:0] \cr15_namespace$28.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [2:0] \cr15_namespace$28.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [15:0] \cr15_namespace$28.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [31:0] \cr15_namespace$28.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:30" *)
  wire [31:0] \cr15_namespace$28.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [95:0] cr5_cap;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [31:0] \cr5_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire \cr5_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire \cr5_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [8:0] \cr5_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [1:0] \cr5_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [2:0] \cr5_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [15:0] \cr5_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [31:0] \cr5_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:161" *)
  wire [31:0] \cr5_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:160" *)
  reg cr5_install_active;
  (* src = "/home/runner/workspace/hardware/change.py:120" *)
  reg [31:0] cr7_base = 32'd0;
  (* src = "/home/runner/workspace/hardware/change.py:26" *)
  wire [3:0] cr_dst;
  (* src = "/home/runner/workspace/hardware/change.py:72" *)
  reg [3:0] cr_index = 4'h0;
  (* src = "/home/runner/workspace/hardware/change.py:106" *)
  wire cr_port_match;
  (* src = "/home/runner/workspace/hardware/change.py:20" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [95:0] \cr_rd_data$26 ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [31:0] \cr_rd_data$26.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire \cr_rd_data$26.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire \cr_rd_data$26.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [8:0] \cr_rd_data$26.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [1:0] \cr_rd_data$26.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [2:0] \cr_rd_data$26.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [15:0] \cr_rd_data$26.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [31:0] \cr_rd_data$26.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:21" *)
  wire [31:0] \cr_rd_data$26.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:12" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/change.py:22" *)
  output [3:0] cr_wr_addr;
  wire [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  wire [3:0] \cr_wr_addr$52 ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  output [95:0] cr_wr_data;
  wire [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [95:0] \cr_wr_data$54 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$54.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$54.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$54.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data$54.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data$54.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data$54.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data$54.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$54.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$54.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:23" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:24" *)
  output cr_wr_en;
  wire cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  wire \cr_wr_en$56 ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  reg [95:0] crn_reg_latched = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire [31:0] \crn_reg_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire \crn_reg_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire \crn_reg_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire [8:0] \crn_reg_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire [1:0] \crn_reg_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire [2:0] \crn_reg_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire [15:0] \crn_reg_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire [31:0] \crn_reg_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  wire [31:0] \crn_reg_latched.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/change.py:45" *)
  reg [3:0] dr_rd_addr;
  (* src = "/home/runner/workspace/hardware/change.py:46" *)
  input [31:0] dr_rd_data;
  wire [31:0] dr_rd_data;
  (* src = "/home/runner/workspace/hardware/change.py:93" *)
  wire [15:0] effective_mask;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/change.py:76" *)
  wire fault_latched;
  (* src = "/home/runner/workspace/hardware/change.py:77" *)
  output [4:0] fault_type;
  reg [4:0] fault_type = 5'h00;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/change.py:77" *)
  wire [4:0] fault_type_latched;
  (* src = "/home/runner/workspace/hardware/change.py:85" *)
  reg fetch_thr_hdr_active;
  (* src = "/home/runner/workspace/hardware/change.py:122" *)
  reg [31:0] fetched_gt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  input [3:0] flags;
  wire [3:0] flags;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags.C ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags.N ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags.V ;
  (* src = "/home/runner/workspace/hardware/change.py:48" *)
  wire \flags.Z ;
  (* src = "/home/runner/workspace/hardware/change.py:13" *)
  wire [15:0] index;
  (* src = "/home/runner/workspace/hardware/change.py:74" *)
  reg [15:0] index_latched = 16'h0000;
  (* src = "/home/runner/workspace/hardware/change.py:27" *)
  input m_elevated;
  wire m_elevated;
  (* src = "/home/runner/workspace/hardware/change.py:61" *)
  output m_flag_restore_en;
  reg m_flag_restore_en;
  (* src = "/home/runner/workspace/hardware/change.py:62" *)
  output m_flag_restore_val;
  reg m_flag_restore_val;
  (* src = "/home/runner/workspace/hardware/change.py:75" *)
  reg [15:0] mask_latched = 16'h0000;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/change.py:32" *)
  wire [31:0] mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/change.py:34" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/change.py:34" *)
  wire [31:0] \mem_rd_data$30 ;
  (* src = "/home/runner/workspace/hardware/change.py:33" *)
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  wire \mem_rd_en$47 ;
  (* src = "/home/runner/workspace/hardware/change.py:35" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/change.py:35" *)
  wire \mem_rd_valid$32 ;
  (* src = "/home/runner/workspace/hardware/change.py:36" *)
  reg [31:0] mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/change.py:151" *)
  wire [31:0] mem_wr_addr_reg;
  (* src = "/home/runner/workspace/hardware/change.py:37" *)
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/change.py:152" *)
  wire [31:0] mem_wr_data_reg;
  (* src = "/home/runner/workspace/hardware/change.py:39" *)
  wire mem_wr_done;
  (* src = "/home/runner/workspace/hardware/change.py:38" *)
  reg mem_wr_en;
  (* src = "/home/runner/workspace/hardware/change.py:153" *)
  wire mem_wr_en_reg;
  (* src = "/home/runner/workspace/hardware/change.py:156" *)
  reg mflag_rd_active;
  (* src = "/home/runner/workspace/hardware/change.py:157" *)
  reg [31:0] mflag_rd_addr;
  (* src = "/home/runner/workspace/hardware/change.py:158" *)
  reg mflag_val_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/change.py:90" *)
  reg mload_done_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/change.py:134" *)
  wire [3:0] mload_dst;
  (* src = "/home/runner/workspace/hardware/change.py:91" *)
  reg mload_fault_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/change.py:135" *)
  wire [15:0] mload_index;
  (* src = "/home/runner/workspace/hardware/change.py:133" *)
  wire [3:0] mload_src;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/change.py:89" *)
  wire mload_start_reg;
  (* src = "/home/runner/workspace/hardware/change.py:47" *)
  input [31:0] nia;
  wire [31:0] nia;
  (* src = "/home/runner/workspace/hardware/change.py:129" *)
  wire [31:0] packed_pc_word;
  (* src = "/home/runner/workspace/hardware/change.py:128" *)
  wire [31:0] pc_offset;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/change.py:87" *)
  reg [4:0] save_index = 5'h00;
  (* src = "/home/runner/workspace/hardware/change.py:96" *)
  wire skip_current_cr;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  reg [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  reg [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:47" *)
  wire [4:0] sub_fault_type;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  reg [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  reg sub_start = 1'h0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/change.py:54" *)
  wire [31:0] thread_hdr_out;
  (* src = "/home/runner/workspace/hardware/change.py:54" *)
  output [31:0] thread_hdr_reg;
  reg [31:0] thread_hdr_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/change.py:43" *)
  wire [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  wire [31:0] \thread_wr_data$62 ;
  (* src = "/home/runner/workspace/hardware/change.py:41" *)
  wire thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  wire \thread_wr_en$58 ;
  (* src = "/home/runner/workspace/hardware/change.py:42" *)
  wire [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  wire [3:0] \thread_wr_idx$60 ;
  assign \$25  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$26  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$27  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign change_complete = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$28  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$29  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign \$30  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$31  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$32  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'he;
  assign \$33  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hf;
  assign \$34  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h10;
  assign \$35  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h11;
  assign \$36  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h12;
  assign \$37  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h13;
  assign \$38  = \port$5930$0 [22:19] == (* src = "/home/runner/workspace/hardware/change.py:233" *) 4'hc;
  assign \$39  = \port$5930$0 [22:19] == (* src = "/home/runner/workspace/hardware/change.py:233" *) 4'hd;
  assign \$40  = \$38  | (* src = "/home/runner/workspace/hardware/change.py:233" *) \$39 ;
  assign \$41  = crn_reg_latched[27] & (* src = "/home/runner/workspace/hardware/change.py:101" *) crn_reg_latched[28];
  assign \$42  = ~ (* src = "/home/runner/workspace/hardware/change.py:237" *) \$41 ;
  assign \$43  = crn_reg_latched[27] & (* src = "/home/runner/workspace/hardware/change.py:102" *) crn_reg_latched[29];
  assign \$44  = ~ (* src = "/home/runner/workspace/hardware/change.py:253" *) \$43 ;
  assign \$45  = ~ (* src = "/home/runner/workspace/hardware/change.py:256" *) cr_port_match;
  assign \$46  = save_index + (* src = "/home/runner/workspace/hardware/change.py:290" *) 1'h1;
  assign \$47  = save_index >= (* src = "/home/runner/workspace/hardware/change.py:291" *) 4'hf;
  assign \$48  = cr_index + (* src = "/home/runner/workspace/hardware/change.py:341" *) 1'h1;
  assign \$49  = cr_index >= (* src = "/home/runner/workspace/hardware/change.py:342" *) 4'he;
  assign \$50  = cr_index + (* src = "/home/runner/workspace/hardware/change.py:358" *) 1'h1;
  assign \$51  = cr_index >= (* src = "/home/runner/workspace/hardware/change.py:359" *) 4'he;
  (* src = "/home/runner/workspace/hardware/change.py:76" *)
  always @(posedge clk)
    change_fault <= \$52 ;
  (* src = "/home/runner/workspace/hardware/change.py:77" *)
  always @(posedge clk)
    fault_type <= \$53 ;
  (* src = "/home/runner/workspace/hardware/change.py:90" *)
  always @(posedge clk)
    mload_done_latched <= \$54 ;
  (* src = "/home/runner/workspace/hardware/change.py:91" *)
  always @(posedge clk)
    mload_fault_latched <= \$55 ;
  (* src = "/home/runner/workspace/hardware/change.py:74" *)
  always @(posedge clk)
    index_latched <= \$56 ;
  (* src = "/home/runner/workspace/hardware/change.py:75" *)
  always @(posedge clk)
    mask_latched <= \$57 ;
  (* src = "/home/runner/workspace/hardware/change.py:72" *)
  always @(posedge clk)
    cr_index <= \$58 ;
  (* src = "/home/runner/workspace/hardware/change.py:87" *)
  always @(posedge clk)
    save_index <= \$59 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    change_state <= \$60 ;
  (* src = "/home/runner/workspace/hardware/change.py:120" *)
  always @(posedge clk)
    cr7_base <= \$61 ;
  (* src = "/home/runner/workspace/hardware/change.py:73" *)
  always @(posedge clk)
    crn_reg_latched <= \$62 ;
  (* src = "/home/runner/workspace/hardware/change.py:89" *)
  always @(posedge clk)
    sub_start <= \$63 ;
  (* src = "/home/runner/workspace/hardware/change.py:122" *)
  always @(posedge clk)
    fetched_gt_latched <= \$64 ;
  (* src = "/home/runner/workspace/hardware/change.py:158" *)
  always @(posedge clk)
    mflag_val_latched <= \$65 ;
  (* src = "/home/runner/workspace/hardware/change.py:84" *)
  always @(posedge clk)
    thread_hdr_reg <= \$66 ;
  assign \$2  = cr_index > (* src = "/home/runner/workspace/hardware/change.py:97" *) 4'he;
  assign \$3  = { mask_latched[14:9], 2'h0, mask_latched[6:0] } >> cr_index;
  assign \$4  = ~ (* src = "/home/runner/workspace/hardware/change.py:97" *) \$3 ;
  assign skip_current_cr = \$2  | (* src = "/home/runner/workspace/hardware/change.py:97" *) \$4 ;
  assign \$5  = \port$5930$0 [22:19] == (* src = "/home/runner/workspace/hardware/change.py:108" *) 4'hc;
  assign \$6  = crn_reg_latched[63:32] == (* src = "/home/runner/workspace/hardware/change.py:109" *) 32'd4294967052;
  assign \$7  = crn_reg_latched[63:32] == (* src = "/home/runner/workspace/hardware/change.py:110" *) 32'd4294967053;
  assign cr_port_match = \$5  ? (* src = "/home/runner/workspace/hardware/change.py:108" *) \$6  : \$7 ;
  assign cr12_null = ! (* src = "/home/runner/workspace/hardware/change.py:116" *) cr12_thread[26:25];
  assign \$8  = nia - (* src = "/home/runner/workspace/hardware/change.py:130" *) cr7_base;
  assign \$9  = cr12_thread[63:32] + (* src = "/home/runner/workspace/hardware/change.py:174" *) 7'h44;
  assign \$10  = thread_hdr_reg[7:0] - (* src = "/home/runner/workspace/hardware/change.py:175" *) 1'h1;
  assign \$11  = fetch_thr_hdr_active ? (* src = "/home/runner/workspace/hardware/change.py:185" *) cr12_thread[63:32] : mem_addr;
  assign mem_rd_addr = mflag_rd_active ? (* src = "/home/runner/workspace/hardware/change.py:184" *) mflag_rd_addr : \$11 ;
  assign \$12  = mflag_rd_active | (* src = "/home/runner/workspace/hardware/change.py:187" *) fetch_thr_hdr_active;
  assign mem_rd_en = \$12  | (* src = "/home/runner/workspace/hardware/change.py:187" *) \mem_rd_en$47 ;
  assign cr_wr_addr = cr5_install_active ? (* src = "/home/runner/workspace/hardware/change.py:192" *) 4'h5 : \cr_wr_addr$52 ;
  assign cr_wr_data = cr5_install_active ? (* src = "/home/runner/workspace/hardware/change.py:193" *) cr5_cap : \cr_wr_data$54 ;
  assign cr_wr_en = \cr_wr_en$56  | (* src = "/home/runner/workspace/hardware/change.py:194" *) cr5_install_active;
  assign \$13  = 1'h1 + (* src = "/home/runner/workspace/hardware/change.py:286" *) save_index;
  assign \$15  = cr12_thread[63:32] + (* src = "/home/runner/workspace/hardware/change.py:286" *) \$14 ;
  assign \$16  = cr12_thread[63:32] + (* src = "/home/runner/workspace/hardware/change.py:297" *) 7'h44;
  assign \$17  = cr12_thread[63:32] + (* src = "/home/runner/workspace/hardware/change.py:308" *) 7'h48;
  assign \$18  = cr12_thread[63:32] + (* src = "/home/runner/workspace/hardware/change.py:370" *) 7'h48;
  assign change_busy = ~ (* src = "/home/runner/workspace/hardware/change.py:418" *) \$19 ;
  assign \$19  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) change_state;
  assign \$20  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$21  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$22  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$23  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$24  = change_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  (* src = "/home/runner/workspace/hardware/change.py:70" *)
  \top.core.u_change.u_mload  u_mload (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(\cr_wr_addr$52 ),
    .cr_wr_data(\cr_wr_data$54 ),
    .cr_wr_en(\cr_wr_en$56 ),
    .mem_addr(mem_addr),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$47 ),
    .\mem_rd_valid$23 (mem_rd_valid),
    .sub_cr_dst(sub_cr_dst),
    .sub_cr_src(sub_cr_src),
    .sub_done(sub_done),
    .sub_fault(sub_fault),
    .sub_fault_type(sub_fault_type),
    .sub_index(sub_index),
    .sub_start(sub_start),
    .thread_wr_data(thread_wr_data),
    .thread_wr_en(thread_wr_en),
    .thread_wr_idx(thread_wr_idx)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    m_flag_restore_en = 1'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h10:
          m_flag_restore_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    m_flag_restore_val = 1'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h10:
          m_flag_restore_val = mflag_val_latched;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    cr_rd_addr = 4'h0;
    casez (change_state)
      5'h00:
          if (change_start) begin
            cr_rd_addr = 4'h7;
          end
      5'h01:
          cr_rd_addr = 4'h7;
      5'h02:
          cr_rd_addr = \port$5930$0 [18:15];
      5'h03:
          cr_rd_addr = \port$5930$0 [18:15];
      5'h04:
          cr_rd_addr = \port$5930$0 [18:15];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    sub_cr_src = 4'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          sub_cr_src = \port$5930$0 [18:15];
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          sub_cr_src = \port$5930$0 [18:15];
      5'h0d:
          sub_cr_src = 4'h8;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    sub_cr_dst = 4'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          sub_cr_dst = \port$5930$0 [22:19];
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          sub_cr_dst = 4'h8;
      5'h0d:
          sub_cr_dst = cr_index;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    sub_index = 16'h0000;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          sub_index = index_latched;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          sub_index = index_latched;
      5'h0d:
          sub_index = { 12'h000, cr_index };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    dr_rd_addr = 4'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          dr_rd_addr = save_index[3:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    mem_wr_en = 1'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          mem_wr_en = 1'h1;
      5'h0a:
          mem_wr_en = 1'h1;
      5'h0b:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    mem_wr_addr = 32'd0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          mem_wr_addr = \$15 [31:0];
      5'h0a:
          mem_wr_addr = \$16 [31:0];
      5'h0b:
          mem_wr_addr = \$17 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    mem_wr_data = 32'd0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          mem_wr_data = dr_rd_data;
      5'h0a:
          mem_wr_data = { flags, \$8 [27:0] };
      5'h0b:
          mem_wr_data = { 31'h00000000, cr15_m_flag_in };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    mflag_rd_active = 1'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          mflag_rd_active = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    mflag_rd_addr = 32'd0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          mflag_rd_addr = \$18 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    fetch_thr_hdr_active = 1'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h10:
          /* empty */;
      5'h11:
          /* empty */;
      5'h12:
          fetch_thr_hdr_active = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    cr5_install_active = 1'h0;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h10:
          /* empty */;
      5'h11:
          /* empty */;
      5'h12:
          /* empty */;
      5'h13:
          cr5_install_active = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$52  = change_fault;
    casez (change_state)
      5'h00:
          \$52  = 1'h0;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          if (\$40 ) begin
          end else if (\$42 ) begin
            \$52  = 1'h1;
          end else if (cr12_null) begin
            \$52  = 1'h1;
          end
      5'h05:
          if (m_elevated) begin
          end else if (\$44 ) begin
            \$52  = 1'h1;
          end else if (\$45 ) begin
            \$52  = 1'h1;
          end
      5'h08:
          if (sub_fault) begin
            \$52  = 1'h1;
          end
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          if (sub_fault) begin
            \$52  = 1'h1;
          end
      5'h0d:
          (* full_case = 32'd1 *)
          if (skip_current_cr) begin
          end else begin
            if (sub_fault) begin
              \$52  = 1'h1;
            end
          end
      5'h0f:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h10:
          /* empty */;
      5'h11:
          if (cr12_null) begin
            \$52  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$53  = fault_type;
    casez (change_state)
      5'h00:
          \$53  = 5'h00;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          if (\$40 ) begin
          end else if (\$42 ) begin
            \$53  = 5'h04;
          end else if (cr12_null) begin
            \$53  = 5'h07;
          end
      5'h05:
          if (m_elevated) begin
          end else if (\$44 ) begin
            \$53  = 5'h05;
          end else if (\$45 ) begin
            \$53  = 5'h05;
          end
      5'h08:
          if (sub_fault) begin
            \$53  = sub_fault_type;
          end
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          if (sub_fault) begin
            \$53  = sub_fault_type;
          end
      5'h0d:
          (* full_case = 32'd1 *)
          if (skip_current_cr) begin
          end else begin
            if (sub_fault) begin
              \$53  = sub_fault_type;
            end
          end
      5'h0f:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h10:
          /* empty */;
      5'h11:
          if (cr12_null) begin
            \$53  = 5'h07;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$54  = mload_done_latched;
    casez (change_state)
      5'h00:
          \$54  = 1'h0;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
        begin
          \$54  = 1'h0;
          if (sub_done) begin
            \$54  = 1'h1;
          end
        end
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
        begin
          \$54  = 1'h0;
          if (sub_done) begin
            \$54  = 1'h1;
          end
        end
      5'h0d:
          (* full_case = 32'd1 *)
          if (skip_current_cr) begin
          end else begin
            \$54  = 1'h0;
            if (sub_done) begin
              \$54  = 1'h1;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$55  = mload_fault_latched;
    casez (change_state)
      5'h00:
          \$55  = 1'h0;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
        begin
          \$55  = 1'h0;
          if (sub_fault) begin
            \$55  = 1'h1;
          end
        end
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
        begin
          \$55  = 1'h0;
          if (sub_fault) begin
            \$55  = 1'h1;
          end
        end
      5'h0d:
          (* full_case = 32'd1 *)
          if (skip_current_cr) begin
          end else begin
            \$55  = 1'h0;
            if (sub_fault) begin
              \$55  = 1'h1;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$56  = index_latched;
    casez (change_state)
      5'h00:
          if (change_start) begin
            \$56  = { 1'h0, \port$5930$0 [14:0] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$57  = mask_latched;
    casez (change_state)
      5'h00:
          if (change_start) begin
            \$57  = 16'h0000;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$58  = cr_index;
    casez (change_state)
      5'h00:
          if (change_start) begin
            \$58  = 4'h0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          if (mload_fault_latched) begin
          end else if (mload_done_latched) begin
            \$58  = 4'h0;
          end
      5'h0d:
          if (skip_current_cr) begin
            \$58  = \$48 [3:0];
          end
      5'h0f:
          \$58  = \$50 [3:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$59  = save_index;
    casez (change_state)
      5'h00:
          if (change_start) begin
            \$59  = 5'h00;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          \$59  = \$46 [4:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$60  = change_state;
    casez (change_state)
      5'h00:
          if (change_start) begin
            \$60  = 5'h01;
          end
      5'h01:
          \$60  = 5'h02;
      5'h02:
          \$60  = 5'h03;
      5'h03:
          \$60  = 5'h04;
      5'h04:
          (* full_case = 32'd1 *)
          if (\$40 ) begin
            \$60  = 5'h05;
          end else if (\$42 ) begin
            \$60  = 5'h06;
          end else if (cr12_null) begin
            \$60  = 5'h06;
          end else begin
            \$60  = 5'h07;
          end
      5'h05:
          (* full_case = 32'd1 *)
          if (m_elevated) begin
            \$60  = 5'h08;
          end else if (\$44 ) begin
            \$60  = 5'h06;
          end else if (\$45 ) begin
            \$60  = 5'h06;
          end else begin
            \$60  = 5'h08;
          end
      5'h08:
          if (mload_fault_latched) begin
            \$60  = 5'h06;
          end else if (mload_done_latched) begin
            \$60  = 5'h09;
          end
      5'h07:
          if (\$47 ) begin
            \$60  = 5'h0a;
          end
      5'h0a:
          \$60  = 5'h0b;
      5'h0b:
          \$60  = 5'h0c;
      5'h0c:
          if (mload_fault_latched) begin
            \$60  = 5'h06;
          end else if (mload_done_latched) begin
            \$60  = 5'h0d;
          end
      5'h0d:
          (* full_case = 32'd1 *)
          if (skip_current_cr) begin
            if (\$49 ) begin
              \$60  = 5'h0e;
            end
          end else begin
            if (mload_fault_latched) begin
              \$60  = 5'h06;
            end else if (mload_done_latched) begin
              \$60  = 5'h0f;
            end
          end
      5'h0f:
          (* full_case = 32'd1 *)
          if (\$51 ) begin
            \$60  = 5'h0e;
          end else begin
            \$60  = 5'h0d;
          end
      5'h0e:
          if (mem_rd_valid) begin
            \$60  = 5'h10;
          end
      5'h10:
          \$60  = 5'h11;
      5'h11:
          (* full_case = 32'd1 *)
          if (cr12_null) begin
            \$60  = 5'h06;
          end else begin
            \$60  = 5'h12;
          end
      5'h12:
          if (mem_rd_valid) begin
            \$60  = 5'h13;
          end
      5'h13:
          \$60  = 5'h09;
      5'h09:
          \$60  = 5'h00;
      5'h06:
          \$60  = 5'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$61  = cr7_base;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          \$61  = cr_rd_data[63:32];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$62  = crn_reg_latched;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          \$62  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$63  = sub_start;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          \$63  = 1'h1;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          \$63  = 1'h1;
      5'h0d:
          (* full_case = 32'd1 *)
          if (skip_current_cr) begin
          end else begin
            \$63  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$64  = fetched_gt_latched;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          if (sub_done) begin
            \$64  = cr_rd_data[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$65  = mflag_val_latched;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          if (mem_rd_valid) begin
            \$65  = mem_rd_data[0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$45 ) begin end
    \$66  = thread_hdr_reg;
    casez (change_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h04:
          /* empty */;
      5'h05:
          /* empty */;
      5'h08:
          /* empty */;
      5'h07:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h10:
          /* empty */;
      5'h11:
          /* empty */;
      5'h12:
          if (mem_rd_valid) begin
            \$66  = mem_rd_data;
          end
    endcase
  end
  assign effective_mask = \$1 [15:0];
  assign cr_dst = \port$5930$0 [22:19];
  assign pc_offset = \$8 [31:0];
  assign packed_pc_word = { flags, \$8 [27:0] };
  assign mload_start_reg = sub_start;
  assign mload_src = sub_cr_src;
  assign mload_dst = sub_cr_dst;
  assign mload_index = sub_index;
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign sub_m_elevated = 1'h1;
  assign \cr_rd_data$26  = cr_rd_data;
  assign \cr15_namespace$28  = cr15_namespace;
  assign \mem_rd_data$30  = mem_rd_data;
  assign \mem_rd_valid$32  = mem_rd_valid;
  assign mem_wr_addr_reg = mem_wr_addr;
  assign mem_wr_data_reg = mem_wr_data;
  assign mem_wr_en_reg = mem_wr_en;
  assign \thread_wr_en$58  = thread_wr_en;
  assign \thread_wr_idx$60  = thread_wr_idx;
  assign \thread_wr_data$62  = thread_wr_data;
  assign thread_hdr_out = thread_hdr_reg;
  assign cr_src = \port$5930$0 [18:15];
  assign fault_latched = change_fault;
  assign fault_type_latched = fault_type;
  
  assign index = { 1'h0, \port$5930$0 [14:0] };
  assign change_mask = 16'h0000;
  assign mem_wr_done = 1'h1;
  assign \crn_reg_latched.word0_gt  = crn_reg_latched[31:0];
  assign \crn_reg_latched.word0_gt.slot_id  = crn_reg_latched[15:0];
  assign \crn_reg_latched.word0_gt.gt_seq  = crn_reg_latched[24:16];
  assign \crn_reg_latched.word0_gt.gt_type  = crn_reg_latched[26:25];
  assign \crn_reg_latched.word0_gt.dom  = crn_reg_latched[27];
  assign \crn_reg_latched.word0_gt.perm  = crn_reg_latched[30:28];
  assign \crn_reg_latched.word0_gt.b_flag  = crn_reg_latched[31];
  assign \crn_reg_latched.word1_location  = crn_reg_latched[63:32];
  assign \crn_reg_latched.word2_w2  = crn_reg_latched[95:64];
  assign \cr12_thread.word0_gt  = cr12_thread[31:0];
  assign \cr12_thread.word0_gt.slot_id  = cr12_thread[15:0];
  assign \cr12_thread.word0_gt.gt_seq  = cr12_thread[24:16];
  assign \cr12_thread.word0_gt.gt_type  = cr12_thread[26:25];
  assign \cr12_thread.word0_gt.dom  = cr12_thread[27];
  assign \cr12_thread.word0_gt.perm  = cr12_thread[30:28];
  assign \cr12_thread.word0_gt.b_flag  = cr12_thread[31];
  assign \cr12_thread.word1_location  = cr12_thread[63:32];
  assign \cr12_thread.word2_w2  = cr12_thread[95:64];
  assign \flags.N  = flags[0];
  assign \flags.Z  = flags[1];
  assign \flags.C  = flags[2];
  assign \flags.V  = flags[3];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$26.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$26.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$26.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$26.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$26.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$26.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$26.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$26.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$26.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$28.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$28.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$28.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$28.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$28.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$28.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$28.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$28.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$28.word2_w2  = cr15_namespace[95:64];
  assign \cr5_cap.word0_gt  = cr5_cap[31:0];
  assign \cr5_cap.word0_gt.slot_id  = cr5_cap[15:0];
  assign \cr5_cap.word0_gt.gt_seq  = cr5_cap[24:16];
  assign \cr5_cap.word0_gt.gt_type  = cr5_cap[26:25];
  assign \cr5_cap.word0_gt.dom  = cr5_cap[27];
  assign \cr5_cap.word0_gt.perm  = cr5_cap[30:28];
  assign \cr5_cap.word0_gt.b_flag  = cr5_cap[31];
  assign \cr5_cap.word1_location  = cr5_cap[63:32];
  assign \cr5_cap.word2_w2  = cr5_cap[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_wr_data$54.word0_gt  = \cr_wr_data$54 [31:0];
  assign \cr_wr_data$54.word0_gt.slot_id  = \cr_wr_data$54 [15:0];
  assign \cr_wr_data$54.word0_gt.gt_seq  = \cr_wr_data$54 [24:16];
  assign \cr_wr_data$54.word0_gt.gt_type  = \cr_wr_data$54 [26:25];
  assign \cr_wr_data$54.word0_gt.dom  = \cr_wr_data$54 [27];
  assign \cr_wr_data$54.word0_gt.perm  = \cr_wr_data$54 [30:28];
  assign \cr_wr_data$54.word0_gt.b_flag  = \cr_wr_data$54 [31];
  assign \cr_wr_data$54.word1_location  = \cr_wr_data$54 [63:32];
  assign \cr_wr_data$54.word2_w2  = \cr_wr_data$54 [95:64];
  assign cr5_cap[95:64] = { \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10 [8], \$10  };
  assign cr5_cap[63:32] = \$9 [31:0];
  assign cr5_cap[31] = 1'h0;
  assign cr5_cap[30:28] = 3'h3;
  assign cr5_cap[27] = 1'h0;
  assign cr5_cap[26:25] = 2'h1;
  assign cr5_cap[24:16] = 9'h000;
  assign cr5_cap[15:0] = 16'h0000;
  assign { \$1 [15], \$1 [8:7] } = 3'h0;
  assign { \$1 [16], \$1 [14:9], \$1 [6:0] } = { 1'h0, mask_latched[14:9], mask_latched[6:0] };
  assign \$14  = { 1'h0, \$13 , 2'h0 };
endmodule

(* src = "/home/runner/workspace/hardware/mload.py:88" *)
(* generator = "Amaranth" *)
module \top.core.u_change.u_mload (clk, \mem_rd_valid$23 , cr_rd_data, mem_addr, mem_rd_en, sub_fault, sub_done, cr15_namespace, sub_cr_src, sub_cr_dst, sub_index, sub_start, thread_wr_en, thread_wr_idx, thread_wr_data, cr_wr_addr, cr_wr_data, cr_wr_en, sub_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$46  = 0;
  wire [18:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [32:0] \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  reg [3:0] \$25 ;
  reg [3:0] \$26 ;
  reg [15:0] \$27 ;
  reg \$28 ;
  reg [31:0] \$29 ;
  wire [32:0] \$3 ;
  reg \$30 ;
  reg [95:0] \$31 ;
  reg [4:0] \$32 ;
  reg [3:0] \$33 ;
  reg [95:0] \$34 ;
  reg [31:0] \$35 ;
  reg [31:0] \$36 ;
  reg [15:0] \$37 ;
  reg [31:0] \$38 ;
  wire [32:0] \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/mload.py:115" *)
  wire bounds_ok;
  (* src = "/home/runner/workspace/hardware/mload.py:119" *)
  wire [31:0] clist_gt_addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [95:0] \cr15_namespace$8 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace$8.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace$8.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace$8.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace$8.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  reg [3:0] cr_dst_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  reg [3:0] cr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  reg [31:0] direct_gt_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  reg direct_mode = 1'h0;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:253" *)
  reg [31:0] gbit_cleared_w1;
  (* src = "/home/runner/workspace/hardware/mload.py:66" *)
  reg gbit_reset_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  reg [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  reg [15:0] index_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/mload.py:135" *)
  reg [31:0] local_mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:136" *)
  reg local_mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:138" *)
  wire [31:0] local_mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:137" *)
  wire local_mem_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  reg m_elevated_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  output [31:0] mem_addr;
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  wire [31:0] \mem_addr$12 ;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  wire [31:0] \mem_rd_data$21 ;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  output mem_rd_en;
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  wire \mem_rd_en$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/mload.py:61" *)
  input \mem_rd_valid$23 ;
  wire \mem_rd_valid$23 ;
  (* src = "/home/runner/workspace/hardware/mload.py:63" *)
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:62" *)
  reg mem_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] mload_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:85" *)
  wire [31:0] ns_abstract_gt;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:71" *)
  wire [31:0] \ns_abstract_gt$56 ;
  (* src = "/home/runner/workspace/hardware/mload.py:65" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] \ns_entry_addr_out$25 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:64" *)
  wire [4:0] ns_gate_fault_type;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  reg ns_gate_start;
  (* src = "/home/runner/workspace/hardware/mload.py:125" *)
  wire ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  reg [31:0] ns_w1_saved = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:79" *)
  reg [31:0] outform_clist_addr = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  wire [31:0] outform_clist_addr_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:81" *)
  wire outform_done_in;
  (* src = "/home/runner/workspace/hardware/mload.py:82" *)
  wire outform_fault_in;
  (* src = "/home/runner/workspace/hardware/mload.py:83" *)
  wire [4:0] outform_fault_type_in;
  (* src = "/home/runner/workspace/hardware/mload.py:77" *)
  reg [31:0] outform_gt_raw = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  wire [31:0] outform_gt_raw_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:78" *)
  reg [15:0] outform_slot_id = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  wire [15:0] outform_slot_id_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:76" *)
  wire outform_start_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  reg [95:0] result_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [8:0] \result_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [1:0] \result_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [2:0] \result_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [15:0] \result_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  reg [95:0] src_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [8:0] \src_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [1:0] \src_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [2:0] \src_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [15:0] \src_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:112" *)
  wire src_is_null;
  (* src = "/home/runner/workspace/hardware/mload.py:44" *)
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  input [3:0] sub_cr_dst;
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  input [3:0] sub_cr_src;
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  output sub_done;
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  output sub_fault;
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  output [4:0] sub_fault_type;
  reg [4:0] sub_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  input [15:0] sub_index;
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  input sub_start;
  wire sub_start;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  output [31:0] thread_wr_data;
  reg [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  output thread_wr_en;
  reg thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  output [3:0] thread_wr_idx;
  reg [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  always @(posedge clk)
    m_elevated_reg <= \$30 ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  always @(posedge clk)
    result_cap <= \$31 ;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  always @(posedge clk)
    sub_fault_type <= \$32 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    mload_state <= \$33 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  always @(posedge clk)
    src_cap <= \$34 ;
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  always @(posedge clk)
    outform_clist_addr <= \$35 ;
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  always @(posedge clk)
    outform_gt_raw <= \$36 ;
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  always @(posedge clk)
    outform_slot_id <= \$37 ;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  always @(posedge clk)
    ns_w1_saved <= \$38 ;
  assign src_is_null = ! (* src = "/home/runner/workspace/hardware/mload.py:113" *) src_cap[26:25];
  assign bounds_ok = index_reg < (* src = "/home/runner/workspace/hardware/mload.py:117" *) src_cap[79:64];
  assign \$2  = src_cap[63:32] + (* src = "/home/runner/workspace/hardware/mload.py:120" *) \$1 ;
  assign ns_index_in_bounds = result_cap[15:0] < (* src = "/home/runner/workspace/hardware/mload.py:126" *) cr15_namespace[79:64];
  assign mem_addr = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:144" *) \mem_addr$12  : local_mem_addr;
  assign mem_rd_en = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:147" *) \mem_rd_en$15  : local_mem_rd_en;
  assign mem_rd_valid = ns_gate_busy & (* src = "/home/runner/workspace/hardware/mload.py:152" *) \mem_rd_valid$23 ;
  assign \$4  = ns_entry_addr_out + (* src = "/home/runner/workspace/hardware/mload.py:256" *) 3'h4;
  assign \$5  = cr_dst_reg <= (* src = "/home/runner/workspace/hardware/mload.py:264" *) 3'h7;
  assign sub_busy = ~ (* src = "/home/runner/workspace/hardware/mload.py:302" *) \$6 ;
  assign ns_abstract_gt = m_elevated_reg ? (* src = "/home/runner/workspace/hardware/mload.py:310" *) \ns_abstract_gt$56  : 32'd0;
  assign \$6  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) mload_state;
  assign \$7  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$8  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$9  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign sub_fault = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$10  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$11  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign outform_start_out = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$12  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$13  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$14  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$15  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign sub_done = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$16  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$17  = src_cap[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) src_cap[28];
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$17 ;
  assign \$21  = ~ (* src = "/home/runner/workspace/hardware/mload.py:192" *) bounds_ok;
  assign \$22  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:205" *) 2'h3;
  assign \$23  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:212" *) 2'h2;
  assign \$24  = ~ (* src = "/home/runner/workspace/hardware/mload.py:223" *) ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  always @(posedge clk)
    cr_src_reg <= \$25 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  always @(posedge clk)
    cr_dst_reg <= \$26 ;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  always @(posedge clk)
    index_reg <= \$27 ;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  always @(posedge clk)
    direct_mode <= \$28 ;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  always @(posedge clk)
    direct_gt_reg <= \$29 ;
  (* src = "/home/runner/workspace/hardware/mload.py:90" *)
  \top.core.u_change.u_mload.u_ns_gate  u_ns_gate (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .gt_word0(gt_word0),
    .mem_addr(\mem_addr$12 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$15 ),
    .mem_rd_valid(mem_rd_valid),
    .ns_abstract_gt(\ns_abstract_gt$56 ),
    .ns_entry_addr(ns_entry_addr_out),
    .ns_gate_busy(ns_gate_busy),
    .ns_gate_done(ns_gate_done),
    .ns_gate_fault(ns_gate_fault),
    .ns_gate_fault_type(ns_gate_fault_type),
    .ns_gate_start(ns_gate_start),
    .raw_base_reg(raw_base),
    .raw_w2_reg(raw_w2)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$31  = result_cap;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$31  = 96'h000000000000000000000000;
          end
      4'h1:
          if (direct_mode) begin
            \$31 [31:0] = direct_gt_reg;
          end
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            \$31 [31:0] = mem_rd_data;
          end
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$31 [63:32] = raw_base;
            \$31 [95:64] = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$32  = sub_fault_type;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$32  = 5'h00;
          end
      4'h1:
          /* empty */;
      4'h3:
          if (src_is_null) begin
            \$32  = 5'h07;
          end else if (\$20 ) begin
            \$32  = 5'h04;
          end
      4'h5:
          if (\$21 ) begin
            \$32  = 5'h08;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
              \$32  = 5'h0b;
            end
          end
      4'h2:
          if (\$24 ) begin
            \$32  = 5'h08;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
            \$32  = ns_gate_fault_type;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$33  = mload_state;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$33  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
            \$33  = 4'h2;
          end else begin
            \$33  = 4'h3;
          end
      4'h3:
          (* full_case = 32'd1 *)
          if (src_is_null) begin
            \$33  = 4'h4;
          end else if (\$20 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$21 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h6;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            (* full_case = 32'd1 *)
            if (\$22 ) begin
              \$33  = 4'h4;
            end else if (\$23 ) begin
              \$33  = 4'h7;
            end else begin
              \$33  = 4'h2;
            end
          end
      4'h2:
          (* full_case = 32'd1 *)
          if (\$24 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h8;
          end
      4'h8:
          \$33  = 4'h9;
      4'h9:
          if (ns_gate_fault) begin
            \$33  = 4'h4;
          end else if (ns_gate_done) begin
            \$33  = 4'ha;
          end
      4'ha:
          \$33  = 4'hb;
      4'hb:
          \$33  = 4'hc;
      4'hc:
          \$33  = 4'h0;
      4'h4:
          \$33  = 4'h0;
      4'h7:
          \$33  = 4'hd;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$34  = src_cap;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            \$34  = cr_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$35  = outform_clist_addr;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$35  = \$2 [31:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$36  = outform_gt_raw;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$36  = mem_rd_data;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$37  = outform_slot_id;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$37  = mem_rd_data[15:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$38  = ns_w1_saved;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$38  = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    cr_rd_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            cr_rd_addr = cr_src_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    local_mem_addr = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_addr = \$2 [31:0];
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          local_mem_addr = \$4 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    local_mem_rd_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    ns_gate_start = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          ns_gate_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    gt_word0 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          gt_word0 = result_cap[31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    gbit_cleared_w1 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_cleared_w1 = \$3 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    mem_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    mem_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_data = gbit_cleared_w1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    gbit_reset_done = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_reset_done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    thread_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    thread_wr_idx = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_idx = cr_dst_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    thread_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_data = result_cap[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    cr_wr_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_addr = cr_dst_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_data = result_cap;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    cr_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$25  = cr_src_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$25  = sub_cr_src;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$26  = cr_dst_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$26  = sub_cr_dst;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$27  = index_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$27  = sub_index;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$28  = direct_mode;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$28  = 1'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$29  = direct_gt_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$29  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$46 ) begin end
    \$30  = m_elevated_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$30  = 1'h1;
          end
    endcase
  end
  assign clist_gt_addr = \$2 [31:0];
  assign \cr15_namespace$8  = cr15_namespace;
  assign local_mem_wr_en = mem_wr_en;
  assign local_mem_wr_data = mem_wr_data;
  assign \mem_rd_data$21  = mem_rd_data;
  assign \ns_entry_addr_out$25  = ns_entry_addr_out;
  assign fault_type_reg = sub_fault_type;
  assign outform_gt_raw_reg = outform_gt_raw;
  assign outform_slot_id_reg = outform_slot_id;
  assign outform_clist_addr_reg = outform_clist_addr;
  
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign sub_m_elevated = 1'h1;
  assign outform_fault_in = 1'h0;
  assign outform_done_in = 1'h0;
  assign outform_fault_type_in = 5'h00;
  assign \src_cap.word0_gt  = src_cap[31:0];
  assign \src_cap.word0_gt.slot_id  = src_cap[15:0];
  assign \src_cap.word0_gt.gt_seq  = src_cap[24:16];
  assign \src_cap.word0_gt.gt_type  = src_cap[26:25];
  assign \src_cap.word0_gt.dom  = src_cap[27];
  assign \src_cap.word0_gt.perm  = src_cap[30:28];
  assign \src_cap.word0_gt.b_flag  = src_cap[31];
  assign \src_cap.word1_location  = src_cap[63:32];
  assign \src_cap.word2_w2  = src_cap[95:64];
  assign \result_cap.word0_gt  = result_cap[31:0];
  assign \result_cap.word0_gt.slot_id  = result_cap[15:0];
  assign \result_cap.word0_gt.gt_seq  = result_cap[24:16];
  assign \result_cap.word0_gt.gt_type  = result_cap[26:25];
  assign \result_cap.word0_gt.dom  = result_cap[27];
  assign \result_cap.word0_gt.perm  = result_cap[30:28];
  assign \result_cap.word0_gt.b_flag  = result_cap[31];
  assign \result_cap.word1_location  = result_cap[63:32];
  assign \result_cap.word2_w2  = result_cap[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$8.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$8.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$8.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$8.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$8.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$8.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$8.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$8.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$8.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \$1  = { 1'h0, index_reg, 2'h0 };
  assign \$3 [30] = 1'h0;
  assign { \$3 [32:31], \$3 [29:0] } = { 1'h0, ns_w1_saved[31], ns_w1_saved[29:0] };
  assign \$19  = 1'h0;
  assign \$20  = 1'h0;
endmodule

(* src = "/home/runner/workspace/hardware/ns_gate.py:80" *)
(* generator = "Amaranth" *)
module \top.core.u_change.u_mload.u_ns_gate (clk, mem_rd_valid, ns_entry_addr, ns_gate_busy, ns_gate_fault, ns_gate_done, cr15_namespace, ns_gate_start, gt_word0, mem_addr, mem_rd_en, raw_base_reg, raw_w2_reg, ns_abstract_gt, ns_gate_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$47  = 0;
  wire [22:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  reg [31:0] \$15 ;
  reg [31:0] \$16 ;
  reg [31:0] \$17 ;
  reg [31:0] \$18 ;
  reg [4:0] \$19 ;
  wire [32:0] \$2 ;
  reg [31:0] \$20 ;
  reg [2:0] \$21 ;
  wire [31:0] \$3 ;
  wire [32:0] \$4 ;
  wire [32:0] \$5 ;
  wire [32:0] \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$28 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:103" *)
  wire [31:0] computed_integrity;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  reg [31:0] gt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:99" *)
  wire gt_seq_match;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  input [31:0] gt_word0;
  wire [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  output [31:0] mem_addr;
  reg [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:76" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  output [31:0] ns_abstract_gt;
  reg [31:0] ns_abstract_gt = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  output [31:0] ns_entry_addr;
  wire [31:0] ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  output ns_gate_busy;
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  output ns_gate_done;
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  output ns_gate_fault;
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  output [4:0] ns_gate_fault_type;
  reg [4:0] ns_gate_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  input ns_gate_start;
  wire ns_gate_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] ns_gate_state = 3'h0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  output [31:0] raw_base_reg;
  reg [31:0] raw_base_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  reg [31:0] raw_integrity_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  output [31:0] raw_w2_reg;
  reg [31:0] raw_w2_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  wire [31:0] raw_w3_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:106" *)
  wire seal_ok;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  assign \$2  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/ns_gate.py:93" *) \$1 ;
  assign gt_seq_match = gt_latched[24:16] == (* src = "/home/runner/workspace/hardware/ns_gate.py:100" *) raw_w2_reg[29:21];
  assign \$3  = { raw_base_reg[24:0], raw_base_reg[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign seal_ok = computed_integrity == (* src = "/home/runner/workspace/hardware/ns_gate.py:107" *) raw_integrity_reg;
  assign \$4  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:135" *) 3'h4;
  assign \$5  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:148" *) 4'h8;
  assign \$6  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:170" *) 4'hc;
  assign ns_gate_busy = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:184" *) \$7 ;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) ns_gate_state;
  assign \$8  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign ns_gate_fault = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$12  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign ns_gate_done = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:156" *) gt_seq_match;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:159" *) seal_ok;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  always @(posedge clk)
    gt_latched <= \$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:86" *)
  always @(posedge clk)
    raw_base_reg <= \$16 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:87" *)
  always @(posedge clk)
    raw_w2_reg <= \$17 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  always @(posedge clk)
    ns_abstract_gt <= \$18 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  always @(posedge clk)
    ns_gate_fault_type <= \$19 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  always @(posedge clk)
    raw_integrity_reg <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    ns_gate_state <= \$21 ;
  assign \$auto$rtlil.cc:2739:Not$28  = ~ { \$3 [31:30], \$3 [28:25], \$3 [23], \$3 [21], \$3 [19:18], \$3 [16:15], \$3 [13:9], \$3 [7:5], \$3 [3:0] };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    mem_addr = 32'd0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_addr = \$2 [31:0];
      3'h2:
          mem_addr = \$4 [31:0];
      3'h3:
          mem_addr = \$5 [31:0];
      3'h4:
          /* empty */;
      3'h6:
          mem_addr = \$6 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    mem_rd_en = 1'h0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_en = 1'h1;
      3'h2:
          mem_rd_en = 1'h1;
      3'h3:
          mem_rd_en = 1'h1;
      3'h4:
          /* empty */;
      3'h6:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    \$15  = gt_latched;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$15  = gt_word0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    \$16  = raw_base_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$16  = 32'd0;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$16  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    \$17  = raw_w2_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$17  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          if (mem_rd_valid) begin
            \$17  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    \$18  = ns_abstract_gt;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$18  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          if (mem_rd_valid) begin
            \$18  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    \$19  = ns_gate_fault_type;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$19  = 5'h00;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (\$13 ) begin
            \$19  = 5'h09;
          end else if (\$14 ) begin
            \$19  = 5'h0a;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    \$20  = raw_integrity_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$20  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          if (mem_rd_valid) begin
            \$20  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$47 ) begin end
    \$21  = ns_gate_state;
    (* full_case = 32'd1 *)
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$21  = 3'h1;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$21  = 3'h2;
          end
      3'h2:
          if (mem_rd_valid) begin
            \$21  = 3'h3;
          end
      3'h3:
          if (mem_rd_valid) begin
            \$21  = 3'h4;
          end
      3'h4:
          (* full_case = 32'd1 *)
          if (\$13 ) begin
            \$21  = 3'h5;
          end else if (\$14 ) begin
            \$21  = 3'h5;
          end else begin
            \$21  = 3'h6;
          end
      3'h6:
          if (mem_rd_valid) begin
            \$21  = 3'h7;
          end
      3'h7:
          \$21  = 3'h0;
      3'h5:
          \$21  = 3'h0;
    endcase
  end
  assign w0_rot = { raw_base_reg[24:0], raw_base_reg[31:25] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign fault_type_reg = ns_gate_fault_type;
  assign raw_base = raw_base_reg;
  assign raw_w2 = raw_w2_reg;
  assign raw_w3_reg = ns_abstract_gt;
  assign ns_entry_addr_out = \$2 [31:0];
  
  assign ns_entry_addr = \$2 [31:0];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \$1  = { 3'h0, gt_latched[15:0], 4'h0 };
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = raw_w2_reg[29:0];
  assign { computed_integrity[29], computed_integrity[24], computed_integrity[22], computed_integrity[20], computed_integrity[17], computed_integrity[14], computed_integrity[8], computed_integrity[4] } = { \$3 [29], \$3 [24], \$3 [22], \$3 [20], \$3 [17], \$3 [14], \$3 [8], \$3 [4] };
  assign { computed_integrity[31:30], computed_integrity[28:25], computed_integrity[23], computed_integrity[21], computed_integrity[19:18], computed_integrity[16:15], computed_integrity[13:9], computed_integrity[7:5], computed_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$28 ;
endmodule

(* src = "/home/runner/workspace/hardware/cload.py:75" *)
(* generator = "Amaranth" *)
module \top.core.u_cload (clk, \mem_rd_valid$12 , mem_addr, mem_rd_en, cload_busy, cload_fault, cload_start, cr15_namespace, e_gt, cr_wr_addr, cr_wr_data, cr_wr_en, cload_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$48  = 0;
  wire [32:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [13:0] \$2 ;
  wire \$20 ;
  wire [4:0] \$21 ;
  wire [45:0] \$22 ;
  reg [31:0] \$23 ;
  reg [31:0] \$24 ;
  reg [31:0] \$25 ;
  reg [7:0] \$26 ;
  reg [12:0] \$27 ;
  reg [3:0] \$28 ;
  reg [14:0] \$29 ;
  wire [15:0] \$3 ;
  reg [4:0] \$30 ;
  reg [3:0] \$31 ;
  wire [18:0] \$4 ;
  wire [33:0] \$5 ;
  wire [8:0] \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/cload.py:88" *)
  reg [7:0] cc_reg = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/cload.py:56" *)
  output cload_busy;
  wire cload_busy;
  (* src = "/home/runner/workspace/hardware/cload.py:57" *)
  wire cload_done;
  (* src = "/home/runner/workspace/hardware/cload.py:58" *)
  output cload_fault;
  wire cload_fault;
  (* src = "/home/runner/workspace/hardware/cload.py:83" *)
  output [4:0] cload_fault_type;
  reg [4:0] cload_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/cload.py:55" *)
  input cload_start;
  wire cload_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] cload_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [95:0] cr14_out;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [31:0] \cr14_out.word0_gt ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire \cr14_out.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire \cr14_out.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [8:0] \cr14_out.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [1:0] \cr14_out.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [2:0] \cr14_out.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [15:0] \cr14_out.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [31:0] \cr14_out.word1_location ;
  (* src = "/home/runner/workspace/hardware/cload.py:110" *)
  wire [31:0] \cr14_out.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [95:0] \cr15_namespace$1 ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [31:0] \cr15_namespace$1.word0_gt ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire \cr15_namespace$1.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire \cr15_namespace$1.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [8:0] \cr15_namespace$1.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [1:0] \cr15_namespace$1.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [2:0] \cr15_namespace$1.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [15:0] \cr15_namespace$1.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [31:0] \cr15_namespace$1.word1_location ;
  (* src = "/home/runner/workspace/hardware/cload.py:63" *)
  wire [31:0] \cr15_namespace$1.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [95:0] cr6_out;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [31:0] \cr6_out.word0_gt ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire \cr6_out.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire \cr6_out.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [8:0] \cr6_out.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [1:0] \cr6_out.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [2:0] \cr6_out.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [15:0] \cr6_out.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [31:0] \cr6_out.word1_location ;
  (* src = "/home/runner/workspace/hardware/cload.py:130" *)
  wire [31:0] \cr6_out.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/cload.py:144" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/cload.py:66" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/cload.py:146" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/cload.py:89" *)
  reg [12:0] cw_reg = 13'h0000;
  (* src = "/home/runner/workspace/hardware/cload.py:61" *)
  input [31:0] e_gt;
  wire [31:0] e_gt;
  (* src = "/home/runner/workspace/hardware/cload.py:81" *)
  reg [31:0] e_gt_latched = 32'd0;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/cload.py:83" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  reg [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/cload.py:144" *)
  wire [3:0] local_cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [95:0] local_cr_wr_data;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [31:0] \local_cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire \local_cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire \local_cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [8:0] \local_cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [1:0] \local_cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [2:0] \local_cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [15:0] \local_cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [31:0] \local_cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/cload.py:145" *)
  wire [31:0] \local_cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/cload.py:146" *)
  wire local_cr_wr_en;
  (* src = "/home/runner/workspace/hardware/cload.py:93" *)
  reg [31:0] local_mem_addr;
  (* src = "/home/runner/workspace/hardware/cload.py:94" *)
  reg local_mem_rd_en;
  (* src = "/home/runner/workspace/hardware/cload.py:91" *)
  reg [14:0] lump_size_reg = 15'h0000;
  (* src = "/home/runner/workspace/hardware/cload.py:69" *)
  output [31:0] mem_addr;
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  wire [31:0] \mem_addr$5 ;
  (* src = "/home/runner/workspace/hardware/cload.py:71" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/cload.py:71" *)
  wire [31:0] \mem_rd_data$10 ;
  (* src = "/home/runner/workspace/hardware/cload.py:70" *)
  output mem_rd_en;
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  wire \mem_rd_en$8 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/cload.py:72" *)
  input \mem_rd_valid$12 ;
  wire \mem_rd_valid$12 ;
  (* src = "/home/runner/workspace/hardware/cload.py:90" *)
  reg [3:0] n_minus_6_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:64" *)
  wire [4:0] ns_gate_fault_type;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  reg ns_gate_start;
  (* src = "/home/runner/workspace/hardware/cload.py:85" *)
  reg [31:0] raw_base = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] \raw_base$42 ;
  (* src = "/home/runner/workspace/hardware/cload.py:86" *)
  reg [31:0] raw_w2 = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] \raw_w2$43 ;
  assign mem_addr = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/cload.py:100" *) \mem_addr$5  : local_mem_addr;
  assign mem_rd_en = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/cload.py:103" *) \mem_rd_en$8  : local_mem_rd_en;
  assign mem_rd_valid = ns_gate_busy & (* src = "/home/runner/workspace/hardware/cload.py:106" *) \mem_rd_valid$12 ;
  assign \$1  = raw_base + (* src = "/home/runner/workspace/hardware/cload.py:122" *) 3'h4;
  assign \$2  = cw_reg - (* src = "/home/runner/workspace/hardware/cload.py:123" *) 1'h1;
  assign \$3  = lump_size_reg - (* src = "/home/runner/workspace/hardware/cload.py:136" *) cc_reg;
  assign \$5  = $signed({ 1'h0, raw_base }) + (* src = "/home/runner/workspace/hardware/cload.py:136" *) $signed(\$4 );
  assign \$6  = cc_reg - (* src = "/home/runner/workspace/hardware/cload.py:138" *) 1'h1;
  assign \$7  = ! (* src = "/home/runner/workspace/hardware/cload.py:234" *) cc_reg;
  assign cload_busy = ~ (* src = "/home/runner/workspace/hardware/cload.py:255" *) \$8 ;
  assign \$8  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) cload_state;
  assign \$9  = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign cload_fault = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$12  = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$13  = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$14  = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign cload_done = cload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$15  = e_gt_latched[26:25] == (* src = "/home/runner/workspace/hardware/cload.py:180" *) 1'h1;
  assign \$16  = e_gt_latched[26:25] == (* src = "/home/runner/workspace/hardware/cload.py:181" *) 2'h3;
  assign \$17  = \$15  | (* src = "/home/runner/workspace/hardware/cload.py:180" *) \$16 ;
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/cload.py:183" *) \$17 ;
  assign \$19  = e_gt_latched[27] & (* src = "/home/runner/workspace/hardware/cload.py:186" *) e_gt_latched[30];
  assign \$20  = ~ (* src = "/home/runner/workspace/hardware/cload.py:186" *) \$19 ;
  assign \$21  = mem_rd_data[26:23] + (* src = "/home/runner/workspace/hardware/cload.py:221" *) 3'h6;
  assign \$22  = 1'h1 << (* src = "/home/runner/workspace/hardware/cload.py:221" *) \$21 ;
  (* src = "/home/runner/workspace/hardware/cload.py:81" *)
  always @(posedge clk)
    e_gt_latched <= \$23 ;
  (* src = "/home/runner/workspace/hardware/cload.py:85" *)
  always @(posedge clk)
    raw_base <= \$24 ;
  (* src = "/home/runner/workspace/hardware/cload.py:86" *)
  always @(posedge clk)
    raw_w2 <= \$25 ;
  (* src = "/home/runner/workspace/hardware/cload.py:88" *)
  always @(posedge clk)
    cc_reg <= \$26 ;
  (* src = "/home/runner/workspace/hardware/cload.py:89" *)
  always @(posedge clk)
    cw_reg <= \$27 ;
  (* src = "/home/runner/workspace/hardware/cload.py:90" *)
  always @(posedge clk)
    n_minus_6_reg <= \$28 ;
  (* src = "/home/runner/workspace/hardware/cload.py:91" *)
  always @(posedge clk)
    lump_size_reg <= \$29 ;
  (* src = "/home/runner/workspace/hardware/cload.py:83" *)
  always @(posedge clk)
    cload_fault_type <= \$30 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    cload_state <= \$31 ;
  (* src = "/home/runner/workspace/hardware/cload.py:77" *)
  \top.core.u_cload.u_ns_gate  u_ns_gate (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .gt_word0(gt_word0),
    .mem_addr(\mem_addr$5 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$8 ),
    .mem_rd_valid(mem_rd_valid),
    .ns_gate_busy(ns_gate_busy),
    .ns_gate_done(ns_gate_done),
    .ns_gate_fault(ns_gate_fault),
    .ns_gate_fault_type(ns_gate_fault_type),
    .ns_gate_start(ns_gate_start),
    .raw_base_reg(\raw_base$42 ),
    .raw_w2_reg(\raw_w2$43 )
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    ns_gate_start = 1'h0;
    casez (cload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          ns_gate_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    gt_word0 = 32'd0;
    casez (cload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          gt_word0 = e_gt_latched;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    local_mem_addr = 32'd0;
    casez (cload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          local_mem_addr = raw_base;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    local_mem_rd_en = 1'h0;
    casez (cload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          local_mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    cr_wr_addr = 4'h0;
    casez (cload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          cr_wr_addr = 4'he;
      4'h7:
          (* full_case = 32'd1 *)
          if (\$7 ) begin
            cr_wr_addr = 4'h6;
          end else begin
            cr_wr_addr = 4'h6;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (cload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          cr_wr_data = cr14_out;
      4'h7:
          (* full_case = 32'd1 *)
          if (\$7 ) begin
            cr_wr_data = 96'h000000000000000000000000;
          end else begin
            cr_wr_data = cr6_out;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    cr_wr_en = 1'h0;
    casez (cload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          cr_wr_en = 1'h1;
      4'h7:
          (* full_case = 32'd1 *)
          if (\$7 ) begin
            cr_wr_en = 1'h1;
          end else begin
            cr_wr_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$23  = e_gt_latched;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$23  = e_gt;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$24  = raw_base;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$24  = 32'd0;
          end
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$24  = \raw_base$42 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$25  = raw_w2;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$25  = 32'd0;
          end
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$25  = \raw_w2$43 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$26  = cc_reg;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$26  = 8'h00;
          end
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          if (\mem_rd_valid$12 ) begin
            \$26  = mem_rd_data[7:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$27  = cw_reg;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$27  = 13'h0000;
          end
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          if (\mem_rd_valid$12 ) begin
            \$27  = mem_rd_data[22:10];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$28  = n_minus_6_reg;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$28  = 4'h0;
          end
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          if (\mem_rd_valid$12 ) begin
            \$28  = mem_rd_data[26:23];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$29  = lump_size_reg;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$29  = 15'h0000;
          end
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          if (\mem_rd_valid$12 ) begin
            \$29  = \$22 [14:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$30  = cload_fault_type;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$30  = 5'h00;
          end
      4'h1:
          if (\$18 ) begin
            \$30  = 5'h06;
          end else if (\$20 ) begin
            \$30  = 5'h06;
          end
      4'h3:
          /* empty */;
      4'h4:
          if (ns_gate_fault) begin
            \$30  = ns_gate_fault_type;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$48 ) begin end
    \$31  = cload_state;
    casez (cload_state)
      4'h0:
          if (cload_start) begin
            \$31  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (\$18 ) begin
            \$31  = 4'h2;
          end else if (\$20 ) begin
            \$31  = 4'h2;
          end else begin
            \$31  = 4'h3;
          end
      4'h3:
          \$31  = 4'h4;
      4'h4:
          if (ns_gate_fault) begin
            \$31  = 4'h2;
          end else if (ns_gate_done) begin
            \$31  = 4'h5;
          end
      4'h5:
          if (\mem_rd_valid$12 ) begin
            \$31  = 4'h6;
          end
      4'h6:
          \$31  = 4'h7;
      4'h7:
          \$31  = 4'h8;
      4'h8:
          \$31  = 4'h0;
      4'h2:
          \$31  = 4'h0;
    endcase
  end
  assign \cr15_namespace$1  = cr15_namespace;
  assign \mem_rd_data$10  = mem_rd_data;
  assign local_cr_wr_addr = cr_wr_addr;
  assign local_cr_wr_data = cr_wr_data;
  assign local_cr_wr_en = cr_wr_en;
  assign fault_type_reg = cload_fault_type;
  
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$1.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$1.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$1.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$1.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$1.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$1.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$1.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$1.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$1.word2_w2  = cr15_namespace[95:64];
  assign \cr14_out.word0_gt  = cr14_out[31:0];
  assign \cr14_out.word0_gt.slot_id  = cr14_out[15:0];
  assign \cr14_out.word0_gt.gt_seq  = cr14_out[24:16];
  assign \cr14_out.word0_gt.gt_type  = cr14_out[26:25];
  assign \cr14_out.word0_gt.dom  = cr14_out[27];
  assign \cr14_out.word0_gt.perm  = cr14_out[30:28];
  assign \cr14_out.word0_gt.b_flag  = cr14_out[31];
  assign \cr14_out.word1_location  = cr14_out[63:32];
  assign \cr14_out.word2_w2  = cr14_out[95:64];
  assign \cr6_out.word0_gt  = cr6_out[31:0];
  assign \cr6_out.word0_gt.slot_id  = cr6_out[15:0];
  assign \cr6_out.word0_gt.gt_seq  = cr6_out[24:16];
  assign \cr6_out.word0_gt.gt_type  = cr6_out[26:25];
  assign \cr6_out.word0_gt.dom  = cr6_out[27];
  assign \cr6_out.word0_gt.perm  = cr6_out[30:28];
  assign \cr6_out.word0_gt.b_flag  = cr6_out[31];
  assign \cr6_out.word1_location  = cr6_out[63:32];
  assign \cr6_out.word2_w2  = cr6_out[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \local_cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \local_cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \local_cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \local_cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \local_cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \local_cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \local_cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \local_cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \local_cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign cr6_out[95] = 1'h0;
  assign cr6_out[94] = 1'h0;
  assign cr6_out[93:85] = e_gt_latched[24:16];
  assign cr6_out[84:64] = { \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6 [8], \$6  };
  assign cr6_out[63:32] = \$5 [31:0];
  assign cr6_out[31:0] = e_gt_latched;
  assign cr14_out[95] = 1'h0;
  assign cr14_out[94] = 1'h0;
  assign cr14_out[93:85] = e_gt_latched[24:16];
  assign cr14_out[84:64] = { \$2 [13], \$2 [13], \$2 [13], \$2 [13], \$2 [13], \$2 [13], \$2 [13], \$2  };
  assign cr14_out[63:32] = \$1 [31:0];
  assign cr14_out[31] = 1'h0;
  assign cr14_out[30:28] = 3'h5;
  assign cr14_out[27] = 1'h0;
  assign cr14_out[26:25] = e_gt_latched[26:25];
  assign cr14_out[24:16] = e_gt_latched[24:16];
  assign cr14_out[15:0] = e_gt_latched[15:0];
  assign \$4  = { \$3 [15], \$3 , 2'h0 };
endmodule

(* src = "/home/runner/workspace/hardware/ns_gate.py:80" *)
(* generator = "Amaranth" *)
module \top.core.u_cload.u_ns_gate (clk, mem_rd_valid, ns_gate_busy, ns_gate_fault, ns_gate_done, cr15_namespace, ns_gate_start, gt_word0, mem_addr, mem_rd_en, raw_base_reg, raw_w2_reg, ns_gate_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$49  = 0;
  wire [22:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  reg [31:0] \$15 ;
  reg [31:0] \$16 ;
  reg [31:0] \$17 ;
  reg [31:0] \$18 ;
  reg [4:0] \$19 ;
  wire [32:0] \$2 ;
  reg [31:0] \$20 ;
  reg [2:0] \$21 ;
  wire [31:0] \$3 ;
  wire [32:0] \$4 ;
  wire [32:0] \$5 ;
  wire [32:0] \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$20 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:103" *)
  wire [31:0] computed_integrity;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  reg [31:0] gt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:99" *)
  wire gt_seq_match;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  input [31:0] gt_word0;
  wire [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  output [31:0] mem_addr;
  reg [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:76" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:71" *)
  reg [31:0] ns_abstract_gt = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:91" *)
  wire [31:0] ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  output ns_gate_busy;
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  output ns_gate_done;
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  output ns_gate_fault;
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  output [4:0] ns_gate_fault_type;
  reg [4:0] ns_gate_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  input ns_gate_start;
  wire ns_gate_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] ns_gate_state = 3'h0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  output [31:0] raw_base_reg;
  reg [31:0] raw_base_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  reg [31:0] raw_integrity_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  output [31:0] raw_w2_reg;
  reg [31:0] raw_w2_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  wire [31:0] raw_w3_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:106" *)
  wire seal_ok;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  assign \$2  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/ns_gate.py:93" *) \$1 ;
  assign gt_seq_match = gt_latched[24:16] == (* src = "/home/runner/workspace/hardware/ns_gate.py:100" *) raw_w2_reg[29:21];
  assign \$3  = { raw_base_reg[24:0], raw_base_reg[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign seal_ok = computed_integrity == (* src = "/home/runner/workspace/hardware/ns_gate.py:107" *) raw_integrity_reg;
  assign \$4  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:135" *) 3'h4;
  assign \$5  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:148" *) 4'h8;
  assign \$6  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:170" *) 4'hc;
  assign ns_gate_busy = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:184" *) \$7 ;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) ns_gate_state;
  assign \$8  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign ns_gate_fault = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$12  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign ns_gate_done = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:156" *) gt_seq_match;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:159" *) seal_ok;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  always @(posedge clk)
    gt_latched <= \$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:86" *)
  always @(posedge clk)
    raw_base_reg <= \$16 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:87" *)
  always @(posedge clk)
    raw_w2_reg <= \$17 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  always @(posedge clk)
    ns_abstract_gt <= \$18 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  always @(posedge clk)
    ns_gate_fault_type <= \$19 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  always @(posedge clk)
    raw_integrity_reg <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    ns_gate_state <= \$21 ;
  assign \$auto$rtlil.cc:2739:Not$20  = ~ { \$3 [31:30], \$3 [28:25], \$3 [23], \$3 [21], \$3 [19:18], \$3 [16:15], \$3 [13:9], \$3 [7:5], \$3 [3:0] };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    mem_addr = 32'd0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_addr = \$2 [31:0];
      3'h2:
          mem_addr = \$4 [31:0];
      3'h3:
          mem_addr = \$5 [31:0];
      3'h4:
          /* empty */;
      3'h6:
          mem_addr = \$6 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    mem_rd_en = 1'h0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_en = 1'h1;
      3'h2:
          mem_rd_en = 1'h1;
      3'h3:
          mem_rd_en = 1'h1;
      3'h4:
          /* empty */;
      3'h6:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    \$15  = gt_latched;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$15  = gt_word0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    \$16  = raw_base_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$16  = 32'd0;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$16  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    \$17  = raw_w2_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$17  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          if (mem_rd_valid) begin
            \$17  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    \$18  = ns_abstract_gt;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$18  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          if (mem_rd_valid) begin
            \$18  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    \$19  = ns_gate_fault_type;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$19  = 5'h00;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (\$13 ) begin
            \$19  = 5'h09;
          end else if (\$14 ) begin
            \$19  = 5'h0a;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    \$20  = raw_integrity_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$20  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          if (mem_rd_valid) begin
            \$20  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$49 ) begin end
    \$21  = ns_gate_state;
    (* full_case = 32'd1 *)
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$21  = 3'h1;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$21  = 3'h2;
          end
      3'h2:
          if (mem_rd_valid) begin
            \$21  = 3'h3;
          end
      3'h3:
          if (mem_rd_valid) begin
            \$21  = 3'h4;
          end
      3'h4:
          (* full_case = 32'd1 *)
          if (\$13 ) begin
            \$21  = 3'h5;
          end else if (\$14 ) begin
            \$21  = 3'h5;
          end else begin
            \$21  = 3'h6;
          end
      3'h6:
          if (mem_rd_valid) begin
            \$21  = 3'h7;
          end
      3'h7:
          \$21  = 3'h0;
      3'h5:
          \$21  = 3'h0;
    endcase
  end
  assign ns_entry_addr = \$2 [31:0];
  assign w0_rot = { raw_base_reg[24:0], raw_base_reg[31:25] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign fault_type_reg = ns_gate_fault_type;
  assign raw_base = raw_base_reg;
  assign raw_w2 = raw_w2_reg;
  assign raw_w3_reg = ns_abstract_gt;
  assign ns_entry_addr_out = \$2 [31:0];
  
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \$1  = { 3'h0, gt_latched[15:0], 4'h0 };
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = raw_w2_reg[29:0];
  assign { computed_integrity[29], computed_integrity[24], computed_integrity[22], computed_integrity[20], computed_integrity[17], computed_integrity[14], computed_integrity[8], computed_integrity[4] } = { \$3 [29], \$3 [24], \$3 [22], \$3 [20], \$3 [17], \$3 [14], \$3 [8], \$3 [4] };
  assign { computed_integrity[31:30], computed_integrity[28:25], computed_integrity[23], computed_integrity[21], computed_integrity[19:18], computed_integrity[16:15], computed_integrity[13:9], computed_integrity[7:5], computed_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$20 ;
endmodule

(* src = "/home/runner/workspace/hardware/decoder.py:73" *)
(* generator = "Amaranth" *)
module \top.core.u_decoder (exec_enable, is_church_op, is_dread_op, is_dwrite_op, is_iadd_op, is_isub_op, is_branch_op, is_shl_op, is_shr_op, is_bfext_op, is_bfins_op, is_mcmp_op, flags, fault_valid, fault, instruction, instr_valid);
  reg \$auto$verilog_backend.cc:2355:dump_module$50  = 0;
  wire \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  wire \$25 ;
  wire \$26 ;
  wire \$27 ;
  wire \$28 ;
  wire \$29 ;
  wire \$3 ;
  wire \$30 ;
  wire \$31 ;
  wire \$32 ;
  wire \$33 ;
  wire \$34 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/decoder.py:58" *)
  wire [14:0] call_imm;
  (* src = "/home/runner/workspace/hardware/decoder.py:57" *)
  wire [14:0] call_mask;
  (* src = "/home/runner/workspace/hardware/decoder.py:64" *)
  wire [14:0] call_method_index;
  (* src = "/home/runner/workspace/hardware/decoder.py:56" *)
  wire [14:0] cap_index;
  (* src = "/home/runner/workspace/hardware/decoder.py:50" *)
  wire [4:0] church_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:104" *)
  reg cond_pass;
  (* src = "/home/runner/workspace/hardware/decoder.py:51" *)
  wire [3:0] cr_dst;
  (* src = "/home/runner/workspace/hardware/decoder.py:52" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/decoder.py:67" *)
  wire [7:0] eloadcall_clist_row;
  (* src = "/home/runner/workspace/hardware/decoder.py:66" *)
  wire [6:0] eloadcall_method_index;
  (* src = "/home/runner/workspace/hardware/decoder.py:59" *)
  wire [7:0] eloadcall_row;
  (* src = "/home/runner/workspace/hardware/decoder.py:37" *)
  output exec_enable;
  wire exec_enable;
  (* src = "/home/runner/workspace/hardware/decoder.py:69" *)
  output [3:0] fault;
  reg [3:0] fault;
  (* src = "/home/runner/workspace/hardware/decoder.py:70" *)
  output fault_valid;
  reg fault_valid;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  input [3:0] flags;
  wire [3:0] flags;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.C ;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.N ;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.V ;
  (* src = "/home/runner/workspace/hardware/decoder.py:35" *)
  wire \flags.Z ;
  (* src = "/home/runner/workspace/hardware/decoder.py:53" *)
  wire [14:0] immediate;
  (* src = "/home/runner/workspace/hardware/decoder.py:34" *)
  input instr_valid;
  wire instr_valid;
  (* src = "/home/runner/workspace/hardware/decoder.py:33" *)
  input [31:0] instruction;
  wire [31:0] instruction;
  (* src = "/home/runner/workspace/hardware/decoder.py:165" *)
  wire iot_excluded;
  (* src = "/home/runner/workspace/hardware/decoder.py:149" *)
  wire is_bfext;
  (* src = "/home/runner/workspace/hardware/decoder.py:46" *)
  output is_bfext_op;
  wire is_bfext_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:150" *)
  wire is_bfins;
  (* src = "/home/runner/workspace/hardware/decoder.py:47" *)
  output is_bfins_op;
  wire is_bfins_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:146" *)
  wire is_branch;
  (* src = "/home/runner/workspace/hardware/decoder.py:43" *)
  output is_branch_op;
  wire is_branch_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:38" *)
  output is_church_op;
  wire is_church_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:142" *)
  wire is_dread;
  (* src = "/home/runner/workspace/hardware/decoder.py:39" *)
  output is_dread_op;
  wire is_dread_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:143" *)
  wire is_dwrite;
  (* src = "/home/runner/workspace/hardware/decoder.py:40" *)
  output is_dwrite_op;
  wire is_dwrite_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:144" *)
  wire is_iadd;
  (* src = "/home/runner/workspace/hardware/decoder.py:41" *)
  output is_iadd_op;
  wire is_iadd_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:145" *)
  wire is_isub;
  (* src = "/home/runner/workspace/hardware/decoder.py:42" *)
  output is_isub_op;
  wire is_isub_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:151" *)
  wire is_mcmp;
  (* src = "/home/runner/workspace/hardware/decoder.py:48" *)
  output is_mcmp_op;
  wire is_mcmp_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:147" *)
  wire is_shl;
  (* src = "/home/runner/workspace/hardware/decoder.py:44" *)
  output is_shl_op;
  wire is_shl_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:148" *)
  wire is_shr;
  (* src = "/home/runner/workspace/hardware/decoder.py:45" *)
  output is_shr_op;
  wire is_shr_op;
  (* src = "/home/runner/workspace/hardware/decoder.py:61" *)
  wire [3:0] switch_target;
  (* src = "/home/runner/workspace/hardware/decoder.py:55" *)
  wire [3:0] tperm_preset;
  (* src = "/home/runner/workspace/hardware/decoder.py:177" *)
  wire valid_opcode;
  assign \$1  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:110" *) flags[1];
  assign \$2  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:114" *) flags[2];
  assign \$3  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:118" *) flags[0];
  assign \$4  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:122" *) flags[3];
  assign \$5  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:124" *) flags[1];
  assign \$6  = flags[2] & (* src = "/home/runner/workspace/hardware/decoder.py:124" *) \$5 ;
  assign \$7  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:126" *) flags[2];
  assign \$8  = \$7  | (* src = "/home/runner/workspace/hardware/decoder.py:126" *) flags[1];
  assign \$9  = flags[0] == (* src = "/home/runner/workspace/hardware/decoder.py:128" *) flags[3];
  assign \$10  = flags[0] != (* src = "/home/runner/workspace/hardware/decoder.py:130" *) flags[3];
  assign \$11  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:132" *) flags[1];
  assign \$12  = flags[0] == (* src = "/home/runner/workspace/hardware/decoder.py:132" *) flags[3];
  assign \$13  = \$11  & (* src = "/home/runner/workspace/hardware/decoder.py:132" *) \$12 ;
  assign \$14  = flags[0] != (* src = "/home/runner/workspace/hardware/decoder.py:134" *) flags[3];
  assign \$15  = flags[1] | (* src = "/home/runner/workspace/hardware/decoder.py:134" *) \$14 ;
  assign exec_enable = instr_valid & (* src = "/home/runner/workspace/hardware/decoder.py:140" *) cond_pass;
  assign is_dread = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:153" *) 5'h10;
  assign is_dwrite = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:154" *) 5'h11;
  assign is_iadd = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:155" *) 5'h15;
  assign is_isub = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:156" *) 5'h16;
  assign is_branch = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:157" *) 5'h17;
  assign is_shl = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:158" *) 5'h18;
  assign is_shr = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:159" *) 5'h19;
  assign is_bfext = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:160" *) 5'h12;
  assign is_bfins = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:161" *) 5'h13;
  assign is_mcmp = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:162" *) 5'h14;
  assign \$16  = instruction[31:27] <= (* src = "/home/runner/workspace/hardware/decoder.py:179" *) 4'h9;
  assign \$19  = \$18  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_dread;
  assign \$20  = \$19  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_dwrite;
  assign \$21  = \$20  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_iadd;
  assign \$22  = \$21  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_isub;
  assign \$23  = \$22  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_branch;
  assign \$24  = \$23  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_shl;
  assign \$25  = \$24  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_shr;
  assign \$26  = \$25  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_bfext;
  assign \$27  = \$26  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_bfins;
  assign valid_opcode = \$27  | (* src = "/home/runner/workspace/hardware/decoder.py:179" *) is_mcmp;
  assign \$28  = instruction[31:27] <= (* src = "/home/runner/workspace/hardware/decoder.py:184" *) 4'h9;
  assign is_church_op = \$30  & (* src = "/home/runner/workspace/hardware/decoder.py:184" *) instr_valid;
  assign is_dread_op = is_dread & (* src = "/home/runner/workspace/hardware/decoder.py:185" *) instr_valid;
  assign is_dwrite_op = is_dwrite & (* src = "/home/runner/workspace/hardware/decoder.py:186" *) instr_valid;
  assign is_iadd_op = is_iadd & (* src = "/home/runner/workspace/hardware/decoder.py:187" *) instr_valid;
  assign is_isub_op = is_isub & (* src = "/home/runner/workspace/hardware/decoder.py:188" *) instr_valid;
  assign is_branch_op = is_branch & (* src = "/home/runner/workspace/hardware/decoder.py:189" *) instr_valid;
  assign is_shl_op = is_shl & (* src = "/home/runner/workspace/hardware/decoder.py:190" *) instr_valid;
  assign is_shr_op = is_shr & (* src = "/home/runner/workspace/hardware/decoder.py:191" *) instr_valid;
  assign is_bfext_op = is_bfext & (* src = "/home/runner/workspace/hardware/decoder.py:192" *) instr_valid;
  assign is_bfins_op = is_bfins & (* src = "/home/runner/workspace/hardware/decoder.py:193" *) instr_valid;
  assign is_mcmp_op = is_mcmp & (* src = "/home/runner/workspace/hardware/decoder.py:194" *) instr_valid;
  assign \$31  = ~ (* src = "/home/runner/workspace/hardware/decoder.py:203" *) valid_opcode;
  assign \$32  = instruction[31:27] == (* src = "/home/runner/workspace/hardware/decoder.py:208" *) 3'h6;
  assign \$33  = instruction[3:0] == (* src = "/home/runner/workspace/hardware/decoder.py:209" *) 4'hf;
  assign \$34  = \$32  & (* src = "/home/runner/workspace/hardware/decoder.py:208" *) \$33 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$50 ) begin end
    (* full_case = 32'd1 *)
    casez (instruction[26:23])
      4'h0:
          cond_pass = flags[1];
      4'h1:
          cond_pass = \$1 ;
      4'h2:
          cond_pass = flags[2];
      4'h3:
          cond_pass = \$2 ;
      4'h4:
          cond_pass = flags[0];
      4'h5:
          cond_pass = \$3 ;
      4'h6:
          cond_pass = flags[3];
      4'h7:
          cond_pass = \$4 ;
      4'h8:
          cond_pass = \$6 ;
      4'h9:
          cond_pass = \$8 ;
      4'ha:
          cond_pass = \$9 ;
      4'hb:
          cond_pass = \$10 ;
      4'hc:
          cond_pass = \$13 ;
      4'hd:
          cond_pass = \$15 ;
      4'he:
          cond_pass = 1'h1;
      4'hf:
          cond_pass = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$50 ) begin end
    fault_valid = 1'h0;
    if (instr_valid) begin
      if (\$31 ) begin
        fault_valid = 1'h1;
      end else if (\$34 ) begin
        fault_valid = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$50 ) begin end
    fault = 4'h0;
    if (instr_valid) begin
      if (\$31 ) begin
        fault = 4'hb;
      end else if (\$34 ) begin
        fault = 4'hc;
      end
    end
  end
  assign church_op = instruction[31:27];
  assign cr_dst = instruction[22:19];
  assign cr_src = instruction[18:15];
  assign immediate = instruction[14:0];
  assign cap_index = instruction[14:0];
  assign tperm_preset = instruction[3:0];
  assign call_mask = 15'h0000;
  assign call_imm = instruction[14:0];
  assign eloadcall_row = instruction[7:0];
  assign eloadcall_method_index = instruction[14:8];
  assign switch_target = instruction[3:0];
  assign call_method_index = instruction[14:0];
  assign eloadcall_clist_row = instruction[7:0];
  assign iot_excluded = 1'h0;
  assign \flags.N  = flags[0];
  assign \flags.Z  = flags[1];
  assign \flags.C  = flags[2];
  assign \flags.V  = flags[3];
  assign \$17  = 1'h1;
  assign \$18  = \$16 ;
  assign \$29  = 1'h1;
  assign \$30  = \$28 ;
endmodule

(* src = "/home/runner/workspace/hardware/dread.py:64" *)
(* generator = "Amaranth" *)
module \top.core.u_dread (clk, start, cr_rd_data, dr_rd_data, cr_rd_addr, busy, fault, fault_type, dmem_addr, dmem_rd_en, dr_wr_addr, dr_wr_data, dr_wr_en, dr_rd_addr, \port$5930$0 , dmem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$51  = 0;
  wire \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire [31:0] \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire [32:0] \$18 ;
  reg [3:0] \$19 ;
  wire [32:0] \$2 ;
  reg [3:0] \$20 ;
  reg [14:0] \$21 ;
  reg [31:0] \$22 ;
  reg [2:0] \$23 ;
  reg [31:0] \$24 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/dread.py:69" *)
  reg [31:0] addr_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/dread.py:38" *)
  output busy;
  reg busy;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/dread.py:48" *)
  output [3:0] cr_rd_addr;
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/dread.py:49" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/dread.py:41" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/dread.py:66" *)
  reg [3:0] cr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/dread.py:59" *)
  output [31:0] dmem_addr;
  reg [31:0] dmem_addr;
  (* src = "/home/runner/workspace/hardware/dread.py:61" *)
  input [31:0] dmem_rd_data;
  wire [31:0] dmem_rd_data;
  (* src = "/home/runner/workspace/hardware/dread.py:60" *)
  output dmem_rd_en;
  reg dmem_rd_en;
  (* src = "/home/runner/workspace/hardware/dread.py:39" *)
  reg done;
  (* src = "/home/runner/workspace/hardware/dread.py:42" *)
  wire [3:0] dr_dst;
  (* src = "/home/runner/workspace/hardware/dread.py:67" *)
  reg [3:0] dr_dst_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/dread.py:52" *)
  output [3:0] dr_rd_addr;
  wire [3:0] dr_rd_addr;
  (* src = "/home/runner/workspace/hardware/dread.py:53" *)
  input [31:0] dr_rd_data;
  wire [31:0] dr_rd_data;
  (* src = "/home/runner/workspace/hardware/dread.py:55" *)
  output [3:0] dr_wr_addr;
  reg [3:0] dr_wr_addr;
  (* src = "/home/runner/workspace/hardware/dread.py:56" *)
  output [31:0] dr_wr_data;
  reg [31:0] dr_wr_data;
  (* src = "/home/runner/workspace/hardware/dread.py:57" *)
  output dr_wr_en;
  reg dr_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] dread_fsm_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/dread.py:70" *)
  reg [31:0] drx_val_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/dread.py:83" *)
  wire [32:0] eff_off;
  (* src = "/home/runner/workspace/hardware/dread.py:45" *)
  output fault;
  reg fault;
  (* src = "/home/runner/workspace/hardware/dread.py:46" *)
  output [4:0] fault_type;
  reg [4:0] fault_type;
  (* src = "/home/runner/workspace/hardware/dread.py:76" *)
  wire gt_null;
  (* src = "/home/runner/workspace/hardware/dread.py:77" *)
  wire has_r;
  (* src = "/home/runner/workspace/hardware/dread.py:43" *)
  wire [14:0] imm;
  (* src = "/home/runner/workspace/hardware/dread.py:68" *)
  reg [14:0] imm_reg = 15'h0000;
  (* src = "/home/runner/workspace/hardware/dread.py:84" *)
  wire in_bounds;
  (* src = "/home/runner/workspace/hardware/dread.py:78" *)
  wire [15:0] limit;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/dread.py:37" *)
  input start;
  wire start;
  assign gt_null = ! (* src = "/home/runner/workspace/hardware/dread.py:87" *) cr_rd_data[31:0];
  assign \$1  = ~ (* src = "/home/runner/workspace/hardware/dread.py:88" *) cr_rd_data[27];
  assign has_r = \$1  & (* src = "/home/runner/workspace/hardware/dread.py:88" *) cr_rd_data[28];
  assign \$2  = imm_reg[13:4] + (* src = "/home/runner/workspace/hardware/dread.py:92" *) drx_val_reg;
  assign eff_off = imm_reg[14] ? (* src = "/home/runner/workspace/hardware/dread.py:90" *) { 19'h00000, imm_reg[13:0] } : \$2 ;
  assign in_bounds = eff_off <= (* src = "/home/runner/workspace/hardware/dread.py:93" *) cr_rd_data[79:64];
  assign cr_rd_addr = busy ? (* src = "/home/runner/workspace/hardware/dread.py:97" *) cr_src_reg : \port$5930$0 [18:15];
  assign \$3  = cr_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/dread.py:128" *) 2'h3;
  assign \$4  = ~ (* src = "/home/runner/workspace/hardware/dread.py:131" *) has_r;
  assign \$5  = ~ (* src = "/home/runner/workspace/hardware/dread.py:134" *) in_bounds;
  assign \$6  = | (* src = "/home/runner/workspace/hardware/dread.py:156" *) dr_dst_reg;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) dread_fsm_state;
  assign \$8  = dread_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = dread_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = dread_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = dread_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$12  = ~ (* src = "/home/runner/workspace/hardware/dread.py:110" *) \port$5930$0 [14];
  assign \$13  = ! (* src = "/home/runner/workspace/hardware/dread.py:120" *) imm_reg[3:0];
  assign \$14  = \$13  ? (* src = "/home/runner/workspace/hardware/dread.py:120" *) 32'd0 : dr_rd_data;
  assign \$15  = cr_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/dread.py:128" *) 2'h3;
  assign \$16  = ~ (* src = "/home/runner/workspace/hardware/dread.py:131" *) has_r;
  assign \$17  = ~ (* src = "/home/runner/workspace/hardware/dread.py:134" *) in_bounds;
  assign \$18  = cr_rd_data[63:32] + (* src = "/home/runner/workspace/hardware/dread.py:140" *) { eff_off[15:0], 2'h0 };
  (* src = "/home/runner/workspace/hardware/dread.py:66" *)
  always @(posedge clk)
    cr_src_reg <= \$19 ;
  (* src = "/home/runner/workspace/hardware/dread.py:67" *)
  always @(posedge clk)
    dr_dst_reg <= \$20 ;
  (* src = "/home/runner/workspace/hardware/dread.py:68" *)
  always @(posedge clk)
    imm_reg <= \$21 ;
  (* src = "/home/runner/workspace/hardware/dread.py:70" *)
  always @(posedge clk)
    drx_val_reg <= \$22 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    dread_fsm_state <= \$23 ;
  (* src = "/home/runner/workspace/hardware/dread.py:69" *)
  always @(posedge clk)
    addr_reg <= \$24 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    busy = 1'h0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          busy = 1'h1;
      3'h2:
          busy = 1'h1;
      3'h3:
          busy = 1'h1;
      3'h4:
          busy = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    fault = 1'h0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          if (gt_null) begin
            fault = 1'h1;
          end else if (\$3 ) begin
            fault = 1'h1;
          end else if (\$4 ) begin
            fault = 1'h1;
          end else if (\$5 ) begin
            fault = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    fault_type = 5'h00;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          if (gt_null) begin
            fault_type = 5'h07;
          end else if (\$3 ) begin
            fault_type = 5'h0b;
          end else if (\$4 ) begin
            fault_type = 5'h01;
          end else if (\$5 ) begin
            fault_type = 5'h08;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    dmem_addr = 32'd0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          dmem_addr = addr_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    dmem_rd_en = 1'h0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          dmem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    dr_wr_addr = 4'h0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          dr_wr_addr = dr_dst_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    dr_wr_data = 32'd0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          dr_wr_data = dmem_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    dr_wr_en = 1'h0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          dr_wr_en = \$6 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    done = 1'h0;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    \$19  = cr_src_reg;
    casez (dread_fsm_state)
      3'h0:
          if (start) begin
            \$19  = \port$5930$0 [18:15];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    \$20  = dr_dst_reg;
    casez (dread_fsm_state)
      3'h0:
          if (start) begin
            \$20  = \port$5930$0 [22:19];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    \$21  = imm_reg;
    casez (dread_fsm_state)
      3'h0:
          if (start) begin
            \$21  = \port$5930$0 [14:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    \$22  = drx_val_reg;
    casez (dread_fsm_state)
      3'h0:
          if (start) begin
            \$22  = 32'd0;
          end
      3'h1:
          \$22  = \$14 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    \$23  = dread_fsm_state;
    casez (dread_fsm_state)
      3'h0:
          if (start) begin
            (* full_case = 32'd1 *)
            if (\$12 ) begin
              \$23  = 3'h1;
            end else begin
              \$23  = 3'h2;
            end
          end
      3'h1:
          \$23  = 3'h2;
      3'h2:
          (* full_case = 32'd1 *)
          if (gt_null) begin
            \$23  = 3'h0;
          end else if (\$15 ) begin
            \$23  = 3'h0;
          end else if (\$16 ) begin
            \$23  = 3'h0;
          end else if (\$17 ) begin
            \$23  = 3'h0;
          end else begin
            \$23  = 3'h3;
          end
      3'h3:
          \$23  = 3'h4;
      3'h4:
          \$23  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$51 ) begin end
    \$24  = addr_reg;
    casez (dread_fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          (* full_case = 32'd1 *)
          if (gt_null) begin
          end else if (\$15 ) begin
          end else if (\$16 ) begin
          end else if (\$17 ) begin
          end else begin
            \$24  = \$18 [31:0];
          end
    endcase
  end
  assign limit = cr_rd_data[79:64];
  assign cr_src = \port$5930$0 [18:15];
  
  assign dr_dst = \port$5930$0 [22:19];
  assign imm = \port$5930$0 [14:0];
  assign dr_rd_addr = imm_reg[3:0];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
endmodule

(* src = "/home/runner/workspace/hardware/dwrite.py:63" *)
(* generator = "Amaranth" *)
module \top.core.u_dwrite (clk, cr_rd_data, dr_rd_data2, dr_rd_data, cr_rd_addr, dr_rd_addr, busy, fault, fault_type, dmem_addr, dmem_wr_data, dmem_wr_en, dr_rd_addr2, \port$5930$0 , start);
  reg \$auto$verilog_backend.cc:2355:dump_module$52  = 0;
  wire \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire [31:0] \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire [32:0] \$16 ;
  reg [3:0] \$17 ;
  reg [3:0] \$18 ;
  reg [14:0] \$19 ;
  wire [32:0] \$2 ;
  reg [31:0] \$20 ;
  reg [1:0] \$21 ;
  reg [31:0] \$22 ;
  reg [31:0] \$23 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:68" *)
  reg [31:0] addr_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/dwrite.py:37" *)
  output busy;
  reg busy;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/dwrite.py:47" *)
  output [3:0] cr_rd_addr;
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:48" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:40" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/dwrite.py:65" *)
  reg [3:0] cr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/dwrite.py:58" *)
  output [31:0] dmem_addr;
  reg [31:0] dmem_addr;
  (* src = "/home/runner/workspace/hardware/dwrite.py:59" *)
  output [31:0] dmem_wr_data;
  reg [31:0] dmem_wr_data;
  (* src = "/home/runner/workspace/hardware/dwrite.py:60" *)
  output dmem_wr_en;
  reg dmem_wr_en;
  (* src = "/home/runner/workspace/hardware/dwrite.py:38" *)
  reg done;
  (* src = "/home/runner/workspace/hardware/dwrite.py:69" *)
  reg [31:0] dr_data_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/dwrite.py:51" *)
  output [3:0] dr_rd_addr;
  wire [3:0] dr_rd_addr;
  (* src = "/home/runner/workspace/hardware/dwrite.py:55" *)
  output [3:0] dr_rd_addr2;
  wire [3:0] dr_rd_addr2;
  (* src = "/home/runner/workspace/hardware/dwrite.py:52" *)
  input [31:0] dr_rd_data;
  wire [31:0] dr_rd_data;
  (* src = "/home/runner/workspace/hardware/dwrite.py:56" *)
  input [31:0] dr_rd_data2;
  wire [31:0] dr_rd_data2;
  (* src = "/home/runner/workspace/hardware/dwrite.py:41" *)
  wire [3:0] dr_src;
  (* src = "/home/runner/workspace/hardware/dwrite.py:66" *)
  reg [3:0] dr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/dwrite.py:70" *)
  reg [31:0] drx_val_reg = 32'd0;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [1:0] dwrite_fsm_state = 2'h0;
  (* src = "/home/runner/workspace/hardware/dwrite.py:82" *)
  wire [32:0] eff_off;
  (* src = "/home/runner/workspace/hardware/dwrite.py:44" *)
  output fault;
  reg fault;
  (* src = "/home/runner/workspace/hardware/dwrite.py:45" *)
  output [4:0] fault_type;
  reg [4:0] fault_type;
  (* src = "/home/runner/workspace/hardware/dwrite.py:76" *)
  wire gt_null;
  (* src = "/home/runner/workspace/hardware/dwrite.py:77" *)
  wire has_w;
  (* src = "/home/runner/workspace/hardware/dwrite.py:42" *)
  wire [14:0] imm;
  (* src = "/home/runner/workspace/hardware/dwrite.py:67" *)
  reg [14:0] imm_reg = 15'h0000;
  (* src = "/home/runner/workspace/hardware/dwrite.py:83" *)
  wire in_bounds;
  (* src = "/home/runner/workspace/hardware/dwrite.py:78" *)
  wire [15:0] limit;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:36" *)
  input start;
  wire start;
  assign gt_null = ! (* src = "/home/runner/workspace/hardware/dwrite.py:86" *) cr_rd_data[31:0];
  assign \$1  = ~ (* src = "/home/runner/workspace/hardware/dwrite.py:87" *) cr_rd_data[27];
  assign has_w = \$1  & (* src = "/home/runner/workspace/hardware/dwrite.py:87" *) cr_rd_data[29];
  assign \$2  = imm_reg[13:4] + (* src = "/home/runner/workspace/hardware/dwrite.py:91" *) drx_val_reg;
  assign eff_off = imm_reg[14] ? (* src = "/home/runner/workspace/hardware/dwrite.py:89" *) { 19'h00000, imm_reg[13:0] } : \$2 ;
  assign in_bounds = eff_off <= (* src = "/home/runner/workspace/hardware/dwrite.py:92" *) cr_rd_data[79:64];
  assign cr_rd_addr = busy ? (* src = "/home/runner/workspace/hardware/dwrite.py:96" *) cr_src_reg : \port$5930$0 [18:15];
  assign dr_rd_addr = busy ? (* src = "/home/runner/workspace/hardware/dwrite.py:98" *) dr_src_reg : \port$5930$0 [22:19];
  assign \$3  = cr_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/dwrite.py:130" *) 2'h3;
  assign \$4  = ~ (* src = "/home/runner/workspace/hardware/dwrite.py:133" *) has_w;
  assign \$5  = ~ (* src = "/home/runner/workspace/hardware/dwrite.py:136" *) in_bounds;
  assign \$6  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) dwrite_fsm_state;
  assign \$7  = dwrite_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$8  = dwrite_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$9  = dwrite_fsm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$10  = ~ (* src = "/home/runner/workspace/hardware/dwrite.py:112" *) \port$5930$0 [14];
  assign \$11  = ! (* src = "/home/runner/workspace/hardware/dwrite.py:122" *) imm_reg[3:0];
  assign \$12  = \$11  ? (* src = "/home/runner/workspace/hardware/dwrite.py:122" *) 32'd0 : dr_rd_data2;
  assign \$13  = cr_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/dwrite.py:130" *) 2'h3;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/dwrite.py:133" *) has_w;
  assign \$15  = ~ (* src = "/home/runner/workspace/hardware/dwrite.py:136" *) in_bounds;
  assign \$16  = cr_rd_data[63:32] + (* src = "/home/runner/workspace/hardware/dwrite.py:143" *) { eff_off[15:0], 2'h0 };
  (* src = "/home/runner/workspace/hardware/dwrite.py:65" *)
  always @(posedge clk)
    cr_src_reg <= \$17 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:66" *)
  always @(posedge clk)
    dr_src_reg <= \$18 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:67" *)
  always @(posedge clk)
    imm_reg <= \$19 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:70" *)
  always @(posedge clk)
    drx_val_reg <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    dwrite_fsm_state <= \$21 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:68" *)
  always @(posedge clk)
    addr_reg <= \$22 ;
  (* src = "/home/runner/workspace/hardware/dwrite.py:69" *)
  always @(posedge clk)
    dr_data_reg <= \$23 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    busy = 1'h0;
    (* full_case = 32'd1 *)
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          busy = 1'h1;
      2'h2:
          busy = 1'h1;
      2'h3:
          busy = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    fault = 1'h0;
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          if (gt_null) begin
            fault = 1'h1;
          end else if (\$3 ) begin
            fault = 1'h1;
          end else if (\$4 ) begin
            fault = 1'h1;
          end else if (\$5 ) begin
            fault = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    fault_type = 5'h00;
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          if (gt_null) begin
            fault_type = 5'h07;
          end else if (\$3 ) begin
            fault_type = 5'h0b;
          end else if (\$4 ) begin
            fault_type = 5'h02;
          end else if (\$5 ) begin
            fault_type = 5'h08;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    dmem_addr = 32'd0;
    (* full_case = 32'd1 *)
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          /* empty */;
      2'h3:
          dmem_addr = addr_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    dmem_wr_data = 32'd0;
    (* full_case = 32'd1 *)
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          /* empty */;
      2'h3:
          dmem_wr_data = dr_data_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    dmem_wr_en = 1'h0;
    (* full_case = 32'd1 *)
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          /* empty */;
      2'h3:
          dmem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    done = 1'h0;
    (* full_case = 32'd1 *)
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          /* empty */;
      2'h3:
          done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    \$17  = cr_src_reg;
    casez (dwrite_fsm_state)
      2'h0:
          if (start) begin
            \$17  = \port$5930$0 [18:15];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    \$18  = dr_src_reg;
    casez (dwrite_fsm_state)
      2'h0:
          if (start) begin
            \$18  = \port$5930$0 [22:19];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    \$19  = imm_reg;
    casez (dwrite_fsm_state)
      2'h0:
          if (start) begin
            \$19  = \port$5930$0 [14:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    \$20  = drx_val_reg;
    casez (dwrite_fsm_state)
      2'h0:
          if (start) begin
            \$20  = 32'd0;
          end
      2'h1:
          \$20  = \$12 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    \$21  = dwrite_fsm_state;
    (* full_case = 32'd1 *)
    casez (dwrite_fsm_state)
      2'h0:
          if (start) begin
            (* full_case = 32'd1 *)
            if (\$10 ) begin
              \$21  = 2'h1;
            end else begin
              \$21  = 2'h2;
            end
          end
      2'h1:
          \$21  = 2'h2;
      2'h2:
          (* full_case = 32'd1 *)
          if (gt_null) begin
            \$21  = 2'h0;
          end else if (\$13 ) begin
            \$21  = 2'h0;
          end else if (\$14 ) begin
            \$21  = 2'h0;
          end else if (\$15 ) begin
            \$21  = 2'h0;
          end else begin
            \$21  = 2'h3;
          end
      2'h3:
          \$21  = 2'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    \$22  = addr_reg;
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          (* full_case = 32'd1 *)
          if (gt_null) begin
          end else if (\$13 ) begin
          end else if (\$14 ) begin
          end else if (\$15 ) begin
          end else begin
            \$22  = \$16 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$52 ) begin end
    \$23  = dr_data_reg;
    casez (dwrite_fsm_state)
      2'h0:
          /* empty */;
      2'h1:
          /* empty */;
      2'h2:
          (* full_case = 32'd1 *)
          if (gt_null) begin
          end else if (\$13 ) begin
          end else if (\$14 ) begin
          end else if (\$15 ) begin
          end else begin
            \$23  = dr_rd_data;
          end
    endcase
  end
  assign limit = cr_rd_data[79:64];
  assign cr_src = \port$5930$0 [18:15];
  assign dr_src = \port$5930$0 [22:19];
  
  assign imm = \port$5930$0 [14:0];
  assign dr_rd_addr2 = imm_reg[3:0];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
endmodule

(* src = "/home/runner/workspace/hardware/fused_unit.py:61" *)
(* generator = "Amaranth" *)
module \top.core.u_eloadcall (clk, mem_rd_valid, start, cr_rd_data, cr_rd_addr, nia_computed, busy, lazy_resolve_irq, complete, pet_name_rd_data, cr15_namespace, fault, fault_type, lazy_resolve_slot, cr_wr_addr, cr_wr_data, cr_wr_en, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$53  = 0;
  wire [4:0] \$1 ;
  wire [32:0] \$10 ;
  wire [17:0] \$11 ;
  wire [32:0] \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [5:0] \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  wire \$25 ;
  wire \$26 ;
  wire \$27 ;
  wire \$28 ;
  wire \$29 ;
  wire \$3 ;
  reg [1:0] \$30 ;
  reg \$31 ;
  reg [3:0] \$32 ;
  reg \$33 ;
  reg \$34 ;
  reg [15:0] \$35 ;
  reg [14:0] \$36 ;
  reg [15:0] \$37 ;
  reg [3:0] \$38 ;
  reg \$39 ;
  wire [32:0] \$4 ;
  reg [95:0] \$40 ;
  reg [95:0] \$41 ;
  reg [31:0] \$42 ;
  wire [34:0] \$5 ;
  wire [35:0] \$6 ;
  wire [35:0] \$7 ;
  wire \$8 ;
  wire [17:0] \$9 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:20" *)
  output busy;
  wire busy;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:19" *)
  wire [14:0] call_imm;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:71" *)
  reg [14:0] call_imm_latched = 15'h0000;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:41" *)
  output complete;
  wire complete;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  reg [95:0] cr14_latched = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire [31:0] \cr14_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire \cr14_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire \cr14_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire [8:0] \cr14_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire [1:0] \cr14_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire [2:0] \cr14_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire [15:0] \cr14_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire [31:0] \cr14_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  wire [31:0] \cr14_latched.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [95:0] \cr15_namespace$21 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [31:0] \cr15_namespace$21.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire \cr15_namespace$21.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire \cr15_namespace$21.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [8:0] \cr15_namespace$21.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [1:0] \cr15_namespace$21.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [2:0] \cr15_namespace$21.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [15:0] \cr15_namespace$21.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [31:0] \cr15_namespace$21.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:30" *)
  wire [31:0] \cr15_namespace$21.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:162" *)
  wire [15:0] cr_clear_computed;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:44" *)
  wire [15:0] cr_clear_mask;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:16" *)
  wire [3:0] cr_dst;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:25" *)
  output [3:0] cr_rd_addr;
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  wire [3:0] \cr_rd_addr$46 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [95:0] \cr_rd_data$19 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [31:0] \cr_rd_data$19.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire \cr_rd_data$19.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire \cr_rd_data$19.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [8:0] \cr_rd_data$19.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [1:0] \cr_rd_data$19.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [2:0] \cr_rd_data$19.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [15:0] \cr_rd_data$19.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [31:0] \cr_rd_data$19.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:26" *)
  wire [31:0] \cr_rd_data$19.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:15" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  wire [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  wire [3:0] \cr_wr_addr$27 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  wire [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [95:0] \cr_wr_data$29 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$29.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$29.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$29.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data$29.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data$29.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data$29.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data$29.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$29.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$29.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:28" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  wire cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  wire \cr_wr_en$31 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:161" *)
  wire [15:0] dr_clear_computed;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:43" *)
  wire [15:0] dr_clear_mask;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] eloadcall_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:72" *)
  output fault;
  reg fault = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:72" *)
  wire fault_latched;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:73" *)
  output [3:0] fault_type;
  reg [3:0] fault_type = 4'h0;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:73" *)
  wire [3:0] fault_type_latched;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:17" *)
  wire [15:0] index;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:95" *)
  wire [15:0] index_latched;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:92" *)
  wire is_null;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:49" *)
  output lazy_resolve_irq;
  wire lazy_resolve_irq;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:57" *)
  output [15:0] lazy_resolve_slot;
  reg [15:0] lazy_resolve_slot = 16'h0000;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  reg [95:0] loaded_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire [31:0] \loaded_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire \loaded_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire \loaded_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire [8:0] \loaded_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire [1:0] \loaded_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire [2:0] \loaded_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire [15:0] \loaded_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire [31:0] \loaded_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  wire [31:0] \loaded_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:87" *)
  reg [3:0] local_cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:86" *)
  reg local_cr_rd_en;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:18" *)
  wire [15:0] mask;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:70" *)
  reg [15:0] mask_latched = 16'h0000;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:32" *)
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  wire [31:0] \mem_addr$34 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:34" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:34" *)
  wire [31:0] \mem_rd_data$23 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:33" *)
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  wire \mem_rd_en$37 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:35" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:35" *)
  wire \mem_rd_valid$25 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:84" *)
  reg [31:0] method_entry_addr_sig;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:83" *)
  reg method_entry_reading;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:82" *)
  reg [31:0] method_entry_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:101" *)
  reg [3:0] mload_dst;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:102" *)
  reg [15:0] mload_index;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:100" *)
  reg [3:0] mload_src;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:42" *)
  output [31:0] nia_computed;
  wire [31:0] nia_computed;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:41" *)
  wire nia_set;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:42" *)
  wire [31:0] nia_value;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:81" *)
  wire [31:0] ns_base;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:57" *)
  wire [15:0] pet_name_rd_addr;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:58" *)
  input pet_name_rd_data;
  wire pet_name_rd_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:68" *)
  reg [1:0] phase = 2'h0;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:97" *)
  wire src_in_range;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:14" *)
  input start;
  wire start;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:76" *)
  reg sub_done_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:77" *)
  reg sub_fault_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:47" *)
  wire [4:0] sub_fault_type;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  reg sub_start = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:74" *)
  wire \sub_start$11 ;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:75" *)
  wire sub_start_reg;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:39" *)
  wire [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  wire [31:0] \thread_wr_data$43 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:37" *)
  wire thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  wire \thread_wr_en$39 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:38" *)
  wire [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  wire [3:0] \thread_wr_idx$41 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:70" *)
  always @(posedge clk)
    mask_latched <= \$35 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:71" *)
  always @(posedge clk)
    call_imm_latched <= \$36 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:95" *)
  always @(posedge clk)
    lazy_resolve_slot <= \$37 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    eloadcall_state <= \$38 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:75" *)
  always @(posedge clk)
    sub_start <= \$39 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:69" *)
  always @(posedge clk)
    loaded_cap <= \$40 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:79" *)
  always @(posedge clk)
    cr14_latched <= \$41 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:82" *)
  always @(posedge clk)
    method_entry_reg <= \$42 ;
  assign is_null = ! (* src = "/home/runner/workspace/hardware/fused_unit.py:93" *) loaded_cap[26:25];
  assign src_in_range = \port$5930$0 [18:15] <= (* src = "/home/runner/workspace/hardware/fused_unit.py:98" *) 3'h5;
  assign sub_m_elevated = mload_src == (* src = "/home/runner/workspace/hardware/fused_unit.py:129" *) 3'h6;
  assign mem_addr = method_entry_reading ? (* src = "/home/runner/workspace/hardware/fused_unit.py:142" *) method_entry_addr_sig : \mem_addr$34 ;
  assign mem_rd_en = method_entry_reading | (* src = "/home/runner/workspace/hardware/fused_unit.py:143" *) \mem_rd_en$37 ;
  assign cr_rd_addr = local_cr_rd_en ? (* src = "/home/runner/workspace/hardware/fused_unit.py:150" *) local_cr_rd_addr : \cr_rd_addr$46 ;
  assign \$1  = ~ (* src = "/home/runner/workspace/hardware/fused_unit.py:165" *) mask_latched[4:0];
  assign \$2  = ~ (* src = "/home/runner/workspace/hardware/fused_unit.py:166" *) mask_latched[10:5];
  assign \$3  = ! (* src = "/home/runner/workspace/hardware/fused_unit.py:170" *) call_imm_latched;
  assign \$4  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/fused_unit.py:170" *) 3'h4;
  assign \$6  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/fused_unit.py:170" *) \$5 ;
  assign \$7  = \$3  ? (* src = "/home/runner/workspace/hardware/fused_unit.py:170" *) { 3'h0, \$4  } : \$6 ;
  assign \$8  = ! (* src = "/home/runner/workspace/hardware/fused_unit.py:288" *) call_imm_latched;
  assign \$10  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/fused_unit.py:295" *) \$9 ;
  assign \$12  = cr14_latched[63:32] + (* src = "/home/runner/workspace/hardware/fused_unit.py:303" *) \$11 ;
  assign busy = ~ (* src = "/home/runner/workspace/hardware/fused_unit.py:330" *) \$13 ;
  assign dr_clear_mask = complete ? (* src = "/home/runner/workspace/hardware/fused_unit.py:336" *) { 10'h3ff, \$1 , 1'h0 } : 16'h0000;
  assign cr_clear_mask = complete ? (* src = "/home/runner/workspace/hardware/fused_unit.py:337" *) { 10'h000, \$2  } : 16'h0000;
  assign \$13  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) eloadcall_state;
  assign \$14  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$15  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$16  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$17  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$18  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign lazy_resolve_irq = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$19  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$20  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$21  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$22  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$23  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign complete = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$24  = eloadcall_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$25  = ~ (* src = "/home/runner/workspace/hardware/fused_unit.py:190" *) src_in_range;
  assign \$26  = loaded_cap[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) loaded_cap[30];
  assign \$27  = ~ (* src = "/home/runner/workspace/hardware/fused_unit.py:234" *) \$26 ;
  assign \$28  = ! (* src = "/home/runner/workspace/hardware/fused_unit.py:288" *) call_imm_latched;
  assign \$29  = ! (* src = "/home/runner/workspace/hardware/fused_unit.py:306" *) mem_rd_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:68" *)
  always @(posedge clk)
    phase <= \$30 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:72" *)
  always @(posedge clk)
    fault <= \$31 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:73" *)
  always @(posedge clk)
    fault_type <= \$32 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:76" *)
  always @(posedge clk)
    sub_done_latched <= \$33 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:77" *)
  always @(posedge clk)
    sub_fault_latched <= \$34 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:66" *)
  \top.core.u_eloadcall.u_mload  u_mload (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$46 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(cr_wr_addr),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .mem_addr(\mem_addr$34 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$37 ),
    .\mem_rd_valid$23 (mem_rd_valid),
    .sub_cr_dst(mload_dst),
    .sub_cr_src(mload_src),
    .sub_done(sub_done),
    .sub_fault(sub_fault),
    .sub_fault_type(sub_fault_type),
    .sub_index(mload_index),
    .sub_m_elevated(sub_m_elevated),
    .sub_start(sub_start),
    .thread_wr_data(thread_wr_data),
    .thread_wr_en(thread_wr_en),
    .thread_wr_idx(thread_wr_idx)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$35  = mask_latched;
    casez (eloadcall_state)
      4'h0:
          if (start) begin
            \$35  = 16'h0000;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$36  = call_imm_latched;
    casez (eloadcall_state)
      4'h0:
          if (start) begin
            \$36  = { 8'h00, \port$5930$0 [14:8] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$37  = lazy_resolve_slot;
    casez (eloadcall_state)
      4'h0:
          if (start) begin
            \$37  = { 8'h00, \port$5930$0 [7:0] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$38  = eloadcall_state;
    casez (eloadcall_state)
      4'h0:
          if (start) begin
            \$38  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (\$25 ) begin
            \$38  = 4'h2;
          end else begin
            \$38  = 4'h3;
          end
      4'h3:
          if (sub_fault_latched) begin
            \$38  = 4'h2;
          end else if (sub_done_latched) begin
            \$38  = 4'h4;
          end
      4'h4:
          \$38  = 4'h5;
      4'h5:
          (* full_case = 32'd1 *)
          if (is_null) begin
            (* full_case = 32'd1 *)
            if (pet_name_rd_data) begin
              \$38  = 4'h6;
            end else begin
              \$38  = 4'h2;
            end
          end else if (\$27 ) begin
            \$38  = 4'h2;
          end else begin
            \$38  = 4'h7;
          end
      4'h7:
          if (sub_fault_latched) begin
            \$38  = 4'h2;
          end else if (sub_done_latched) begin
            \$38  = 4'h8;
          end
      4'h8:
          \$38  = 4'h9;
      4'h9:
          if (sub_fault_latched) begin
            \$38  = 4'h2;
          end else if (sub_done_latched) begin
            \$38  = 4'ha;
          end
      4'ha:
          \$38  = 4'hb;
      4'hb:
          (* full_case = 32'd1 *)
          if (\$28 ) begin
            \$38  = 4'hc;
          end else begin
            \$38  = 4'hd;
          end
      4'hd:
          if (mem_rd_valid) begin
            (* full_case = 32'd1 *)
            if (\$29 ) begin
              \$38  = 4'h2;
            end else begin
              \$38  = 4'hc;
            end
          end
      4'hc:
          \$38  = 4'h0;
      4'h2:
          \$38  = 4'h0;
      4'h6:
          \$38  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$39  = sub_start;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (\$25 ) begin
          end else begin
            \$39  = 1'h1;
          end
      4'h3:
          \$39  = 1'h0;
      4'h4:
          /* empty */;
      4'h5:
          (* full_case = 32'd1 *)
          if (is_null) begin
          end else if (\$27 ) begin
          end else begin
            \$39  = 1'h1;
          end
      4'h7:
          \$39  = 1'h0;
      4'h8:
          \$39  = 1'h1;
      4'h9:
          \$39  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$40  = loaded_cap;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          \$40  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$41  = cr14_latched;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          \$41  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$42  = method_entry_reg;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hd:
          if (mem_rd_valid) begin
            (* full_case = 32'd1 *)
            if (\$29 ) begin
            end else begin
              \$42  = mem_rd_data;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    (* full_case = 32'd1 *)
    casez (phase)
      2'h0:
          mload_src = \port$5930$0 [18:15];
      2'h1:
          mload_src = \port$5930$0 [22:19];
      default:
          mload_src = 4'h6;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    (* full_case = 32'd1 *)
    casez (phase)
      2'h0:
          mload_dst = \port$5930$0 [22:19];
      2'h1:
          mload_dst = 4'h6;
      default:
          mload_dst = 4'h7;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    (* full_case = 32'd1 *)
    casez (phase)
      2'h0:
          mload_index = { 8'h00, \port$5930$0 [7:0] };
      2'h1:
          mload_index = 16'h0000;
      default:
          mload_index = 16'h0000;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    local_cr_rd_en = 1'h0;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          local_cr_rd_en = 1'h1;
      4'h5:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          local_cr_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    local_cr_rd_addr = 4'h0;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          local_cr_rd_addr = \port$5930$0 [22:19];
      4'h5:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          local_cr_rd_addr = 4'he;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    method_entry_reading = 1'h0;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          (* full_case = 32'd1 *)
          if (\$8 ) begin
          end else begin
            method_entry_reading = 1'h1;
          end
      4'hd:
          method_entry_reading = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    method_entry_addr_sig = 32'd0;
    casez (eloadcall_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          (* full_case = 32'd1 *)
          if (\$8 ) begin
          end else begin
            method_entry_addr_sig = \$10 [31:0];
          end
      4'hd:
          method_entry_addr_sig = \$12 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$30  = phase;
    casez (eloadcall_state)
      4'h0:
          \$30  = 2'h0;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          (* full_case = 32'd1 *)
          if (is_null) begin
          end else if (\$27 ) begin
          end else begin
            \$30  = 2'h1;
          end
      4'h7:
          /* empty */;
      4'h8:
          \$30  = 2'h2;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$31  = fault;
    casez (eloadcall_state)
      4'h0:
          \$31  = 1'h0;
      4'h1:
          if (\$25 ) begin
            \$31  = 1'h1;
          end
      4'h3:
          if (sub_fault) begin
            \$31  = 1'h1;
          end
      4'h4:
          /* empty */;
      4'h5:
          if (is_null) begin
            (* full_case = 32'd1 *)
            if (pet_name_rd_data) begin
            end else begin
              \$31  = 1'h1;
            end
          end else if (\$27 ) begin
            \$31  = 1'h1;
          end
      4'h7:
          if (sub_fault) begin
            \$31  = 1'h1;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (sub_fault) begin
            \$31  = 1'h1;
          end
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hd:
          if (mem_rd_valid) begin
            if (\$29 ) begin
              \$31  = 1'h1;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$32  = fault_type;
    casez (eloadcall_state)
      4'h0:
          \$32  = 4'h0;
      4'h1:
          if (\$25 ) begin
            \$32  = 4'h4;
          end
      4'h3:
          if (sub_fault) begin
            \$32  = sub_fault_type[3:0];
          end
      4'h4:
          /* empty */;
      4'h5:
          if (is_null) begin
            (* full_case = 32'd1 *)
            if (pet_name_rd_data) begin
            end else begin
              \$32  = 4'h7;
            end
          end else if (\$27 ) begin
            \$32  = 4'h6;
          end
      4'h7:
          if (sub_fault) begin
            \$32  = sub_fault_type[3:0];
          end
      4'h8:
          /* empty */;
      4'h9:
          if (sub_fault) begin
            \$32  = sub_fault_type[3:0];
          end
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hd:
          if (mem_rd_valid) begin
            if (\$29 ) begin
              \$32  = 4'h6;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$33  = sub_done_latched;
    casez (eloadcall_state)
      4'h0:
          \$33  = 1'h0;
      4'h1:
          /* empty */;
      4'h3:
          if (sub_done) begin
            \$33  = 1'h1;
          end
      4'h4:
          /* empty */;
      4'h5:
          (* full_case = 32'd1 *)
          if (is_null) begin
          end else if (\$27 ) begin
          end else begin
            \$33  = 1'h0;
          end
      4'h7:
          if (sub_done) begin
            \$33  = 1'h1;
          end
      4'h8:
          \$33  = 1'h0;
      4'h9:
          if (sub_done) begin
            \$33  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$53 ) begin end
    \$34  = sub_fault_latched;
    casez (eloadcall_state)
      4'h0:
          \$34  = 1'h0;
      4'h1:
          /* empty */;
      4'h3:
          if (sub_fault) begin
            \$34  = 1'h1;
          end
      4'h4:
          /* empty */;
      4'h5:
          (* full_case = 32'd1 *)
          if (is_null) begin
          end else if (\$27 ) begin
          end else begin
            \$34  = 1'h0;
          end
      4'h7:
          if (sub_fault) begin
            \$34  = 1'h1;
          end
      4'h8:
          \$34  = 1'h0;
      4'h9:
          if (sub_fault) begin
            \$34  = 1'h1;
          end
    endcase
  end
  assign cr_src = \port$5930$0 [18:15];
  assign cr_dst = \port$5930$0 [22:19];
  assign index = { 8'h00, \port$5930$0 [7:0] };
  assign \sub_start$11  = sub_start;
  assign sub_cr_src = mload_src;
  assign sub_cr_dst = mload_dst;
  assign sub_index = mload_index;
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign \cr_rd_data$19  = cr_rd_data;
  assign \cr15_namespace$21  = cr15_namespace;
  assign \mem_rd_data$23  = mem_rd_data;
  assign \mem_rd_valid$25  = mem_rd_valid;
  assign \cr_wr_addr$27  = cr_wr_addr;
  assign \cr_wr_data$29  = cr_wr_data;
  assign \cr_wr_en$31  = cr_wr_en;
  assign \thread_wr_en$39  = thread_wr_en;
  assign \thread_wr_idx$41  = thread_wr_idx;
  assign \thread_wr_data$43  = thread_wr_data;
  assign sub_start_reg = sub_start;
  assign ns_base = cr14_latched[63:32];
  assign dr_clear_computed = { 10'h3ff, \$1 , 1'h0 };
  assign cr_clear_computed = { 10'h000, \$2  };
  assign fault_latched = fault;
  assign fault_type_latched = fault_type;
  assign nia_set = complete;
  assign nia_value = \$7 [31:0];
  assign index_latched = lazy_resolve_slot;
  assign pet_name_rd_addr = lazy_resolve_slot;
  
  assign mask = 16'h0000;
  assign call_imm = { 8'h00, \port$5930$0 [14:8] };
  assign nia_computed = \$7 [31:0];
  assign \loaded_cap.word0_gt  = loaded_cap[31:0];
  assign \loaded_cap.word0_gt.slot_id  = loaded_cap[15:0];
  assign \loaded_cap.word0_gt.gt_seq  = loaded_cap[24:16];
  assign \loaded_cap.word0_gt.gt_type  = loaded_cap[26:25];
  assign \loaded_cap.word0_gt.dom  = loaded_cap[27];
  assign \loaded_cap.word0_gt.perm  = loaded_cap[30:28];
  assign \loaded_cap.word0_gt.b_flag  = loaded_cap[31];
  assign \loaded_cap.word1_location  = loaded_cap[63:32];
  assign \loaded_cap.word2_w2  = loaded_cap[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$19.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$19.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$19.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$19.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$19.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$19.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$19.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$19.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$19.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$21.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$21.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$21.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$21.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$21.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$21.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$21.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$21.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$21.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_wr_data$29.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data$29.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data$29.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data$29.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data$29.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data$29.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data$29.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data$29.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data$29.word2_w2  = cr_wr_data[95:64];
  assign \cr14_latched.word0_gt  = cr14_latched[31:0];
  assign \cr14_latched.word0_gt.slot_id  = cr14_latched[15:0];
  assign \cr14_latched.word0_gt.gt_seq  = cr14_latched[24:16];
  assign \cr14_latched.word0_gt.gt_type  = cr14_latched[26:25];
  assign \cr14_latched.word0_gt.dom  = cr14_latched[27];
  assign \cr14_latched.word0_gt.perm  = cr14_latched[30:28];
  assign \cr14_latched.word0_gt.b_flag  = cr14_latched[31];
  assign \cr14_latched.word1_location  = cr14_latched[63:32];
  assign \cr14_latched.word2_w2  = cr14_latched[95:64];
  assign \$5  = { 1'h0, method_entry_reg, 2'h0 };
  assign \$9  = { 1'h0, call_imm_latched, 2'h0 };
  assign \$11  = { 1'h0, call_imm_latched, 2'h0 };
endmodule

(* src = "/home/runner/workspace/hardware/mload.py:88" *)
(* generator = "Amaranth" *)
module \top.core.u_eloadcall.u_mload (clk, \mem_rd_valid$23 , cr_rd_data, sub_m_elevated, mem_addr, mem_rd_en, sub_fault, sub_done, cr15_namespace, sub_cr_src, sub_cr_dst, sub_index, sub_start, cr_rd_addr, thread_wr_en, thread_wr_idx, thread_wr_data, cr_wr_addr, cr_wr_data, cr_wr_en, sub_fault_type, mem_rd_data
);
  reg \$auto$verilog_backend.cc:2355:dump_module$54  = 0;
  wire [18:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [32:0] \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  reg [3:0] \$25 ;
  reg [3:0] \$26 ;
  reg [15:0] \$27 ;
  reg \$28 ;
  reg [31:0] \$29 ;
  wire [32:0] \$3 ;
  reg \$30 ;
  reg [95:0] \$31 ;
  reg [4:0] \$32 ;
  reg [3:0] \$33 ;
  reg [95:0] \$34 ;
  reg [31:0] \$35 ;
  reg [31:0] \$36 ;
  reg [15:0] \$37 ;
  reg [31:0] \$38 ;
  wire [32:0] \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/mload.py:115" *)
  wire bounds_ok;
  (* src = "/home/runner/workspace/hardware/mload.py:119" *)
  wire [31:0] clist_gt_addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [95:0] \cr15_namespace$8 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace$8.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace$8.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace$8.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace$8.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  reg [3:0] cr_dst_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  reg [3:0] cr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  reg [31:0] direct_gt_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  reg direct_mode = 1'h0;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:253" *)
  reg [31:0] gbit_cleared_w1;
  (* src = "/home/runner/workspace/hardware/mload.py:66" *)
  reg gbit_reset_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  reg [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  reg [15:0] index_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/mload.py:135" *)
  reg [31:0] local_mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:136" *)
  reg local_mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:138" *)
  wire [31:0] local_mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:137" *)
  wire local_mem_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  reg m_elevated_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  output [31:0] mem_addr;
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  wire [31:0] \mem_addr$12 ;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  wire [31:0] \mem_rd_data$21 ;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  output mem_rd_en;
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  wire \mem_rd_en$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/mload.py:61" *)
  input \mem_rd_valid$23 ;
  wire \mem_rd_valid$23 ;
  (* src = "/home/runner/workspace/hardware/mload.py:63" *)
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:62" *)
  reg mem_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] mload_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:85" *)
  wire [31:0] ns_abstract_gt;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:71" *)
  wire [31:0] \ns_abstract_gt$56 ;
  (* src = "/home/runner/workspace/hardware/mload.py:65" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] \ns_entry_addr_out$25 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:64" *)
  wire [4:0] ns_gate_fault_type;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  reg ns_gate_start;
  (* src = "/home/runner/workspace/hardware/mload.py:125" *)
  wire ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  reg [31:0] ns_w1_saved = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:79" *)
  reg [31:0] outform_clist_addr = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  wire [31:0] outform_clist_addr_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:81" *)
  wire outform_done_in;
  (* src = "/home/runner/workspace/hardware/mload.py:82" *)
  wire outform_fault_in;
  (* src = "/home/runner/workspace/hardware/mload.py:83" *)
  wire [4:0] outform_fault_type_in;
  (* src = "/home/runner/workspace/hardware/mload.py:77" *)
  reg [31:0] outform_gt_raw = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  wire [31:0] outform_gt_raw_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:78" *)
  reg [15:0] outform_slot_id = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  wire [15:0] outform_slot_id_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:76" *)
  wire outform_start_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  reg [95:0] result_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [8:0] \result_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [1:0] \result_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [2:0] \result_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [15:0] \result_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  reg [95:0] src_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [8:0] \src_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [1:0] \src_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [2:0] \src_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [15:0] \src_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:112" *)
  wire src_is_null;
  (* src = "/home/runner/workspace/hardware/mload.py:44" *)
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  input [3:0] sub_cr_dst;
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  input [3:0] sub_cr_src;
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  output sub_done;
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  output sub_fault;
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  output [4:0] sub_fault_type;
  reg [4:0] sub_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  input [15:0] sub_index;
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  input sub_m_elevated;
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  input sub_start;
  wire sub_start;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  output [31:0] thread_wr_data;
  reg [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  output thread_wr_en;
  reg thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  output [3:0] thread_wr_idx;
  reg [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  always @(posedge clk)
    m_elevated_reg <= \$30 ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  always @(posedge clk)
    result_cap <= \$31 ;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  always @(posedge clk)
    sub_fault_type <= \$32 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    mload_state <= \$33 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  always @(posedge clk)
    src_cap <= \$34 ;
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  always @(posedge clk)
    outform_clist_addr <= \$35 ;
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  always @(posedge clk)
    outform_gt_raw <= \$36 ;
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  always @(posedge clk)
    outform_slot_id <= \$37 ;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  always @(posedge clk)
    ns_w1_saved <= \$38 ;
  assign src_is_null = ! (* src = "/home/runner/workspace/hardware/mload.py:113" *) src_cap[26:25];
  assign bounds_ok = index_reg < (* src = "/home/runner/workspace/hardware/mload.py:117" *) src_cap[79:64];
  assign \$2  = src_cap[63:32] + (* src = "/home/runner/workspace/hardware/mload.py:120" *) \$1 ;
  assign ns_index_in_bounds = result_cap[15:0] < (* src = "/home/runner/workspace/hardware/mload.py:126" *) cr15_namespace[79:64];
  assign mem_addr = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:144" *) \mem_addr$12  : local_mem_addr;
  assign mem_rd_en = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:147" *) \mem_rd_en$15  : local_mem_rd_en;
  assign mem_rd_valid = ns_gate_busy & (* src = "/home/runner/workspace/hardware/mload.py:152" *) \mem_rd_valid$23 ;
  assign \$4  = ns_entry_addr_out + (* src = "/home/runner/workspace/hardware/mload.py:256" *) 3'h4;
  assign \$5  = cr_dst_reg <= (* src = "/home/runner/workspace/hardware/mload.py:264" *) 3'h7;
  assign sub_busy = ~ (* src = "/home/runner/workspace/hardware/mload.py:302" *) \$6 ;
  assign ns_abstract_gt = m_elevated_reg ? (* src = "/home/runner/workspace/hardware/mload.py:310" *) \ns_abstract_gt$56  : 32'd0;
  assign \$6  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) mload_state;
  assign \$7  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$8  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$9  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign sub_fault = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$10  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$11  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign outform_start_out = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$12  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$13  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$14  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$15  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign sub_done = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$16  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$17  = src_cap[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) src_cap[28];
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$17 ;
  assign \$19  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) sub_m_elevated;
  assign \$20  = \$18  & (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$19 ;
  assign \$21  = ~ (* src = "/home/runner/workspace/hardware/mload.py:192" *) bounds_ok;
  assign \$22  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:205" *) 2'h3;
  assign \$23  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:212" *) 2'h2;
  assign \$24  = ~ (* src = "/home/runner/workspace/hardware/mload.py:223" *) ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  always @(posedge clk)
    cr_src_reg <= \$25 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  always @(posedge clk)
    cr_dst_reg <= \$26 ;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  always @(posedge clk)
    index_reg <= \$27 ;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  always @(posedge clk)
    direct_mode <= \$28 ;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  always @(posedge clk)
    direct_gt_reg <= \$29 ;
  (* src = "/home/runner/workspace/hardware/mload.py:90" *)
  \top.core.u_eloadcall.u_mload.u_ns_gate  u_ns_gate (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .gt_word0(gt_word0),
    .mem_addr(\mem_addr$12 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$15 ),
    .mem_rd_valid(mem_rd_valid),
    .ns_abstract_gt(\ns_abstract_gt$56 ),
    .ns_entry_addr(ns_entry_addr_out),
    .ns_gate_busy(ns_gate_busy),
    .ns_gate_done(ns_gate_done),
    .ns_gate_fault(ns_gate_fault),
    .ns_gate_fault_type(ns_gate_fault_type),
    .ns_gate_start(ns_gate_start),
    .raw_base_reg(raw_base),
    .raw_w2_reg(raw_w2)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$31  = result_cap;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$31  = 96'h000000000000000000000000;
          end
      4'h1:
          if (direct_mode) begin
            \$31 [31:0] = direct_gt_reg;
          end
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            \$31 [31:0] = mem_rd_data;
          end
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$31 [63:32] = raw_base;
            \$31 [95:64] = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$32  = sub_fault_type;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$32  = 5'h00;
          end
      4'h1:
          /* empty */;
      4'h3:
          if (src_is_null) begin
            \$32  = 5'h07;
          end else if (\$20 ) begin
            \$32  = 5'h04;
          end
      4'h5:
          if (\$21 ) begin
            \$32  = 5'h08;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
              \$32  = 5'h0b;
            end
          end
      4'h2:
          if (\$24 ) begin
            \$32  = 5'h08;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
            \$32  = ns_gate_fault_type;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$33  = mload_state;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$33  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
            \$33  = 4'h2;
          end else begin
            \$33  = 4'h3;
          end
      4'h3:
          (* full_case = 32'd1 *)
          if (src_is_null) begin
            \$33  = 4'h4;
          end else if (\$20 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$21 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h6;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            (* full_case = 32'd1 *)
            if (\$22 ) begin
              \$33  = 4'h4;
            end else if (\$23 ) begin
              \$33  = 4'h7;
            end else begin
              \$33  = 4'h2;
            end
          end
      4'h2:
          (* full_case = 32'd1 *)
          if (\$24 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h8;
          end
      4'h8:
          \$33  = 4'h9;
      4'h9:
          if (ns_gate_fault) begin
            \$33  = 4'h4;
          end else if (ns_gate_done) begin
            \$33  = 4'ha;
          end
      4'ha:
          \$33  = 4'hb;
      4'hb:
          \$33  = 4'hc;
      4'hc:
          \$33  = 4'h0;
      4'h4:
          \$33  = 4'h0;
      4'h7:
          \$33  = 4'hd;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$34  = src_cap;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            \$34  = cr_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$35  = outform_clist_addr;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$35  = \$2 [31:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$36  = outform_gt_raw;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$36  = mem_rd_data;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$37  = outform_slot_id;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$37  = mem_rd_data[15:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$38  = ns_w1_saved;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$38  = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    cr_rd_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            cr_rd_addr = cr_src_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    local_mem_addr = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_addr = \$2 [31:0];
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          local_mem_addr = \$4 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    local_mem_rd_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    ns_gate_start = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          ns_gate_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    gt_word0 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          gt_word0 = result_cap[31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    gbit_cleared_w1 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_cleared_w1 = \$3 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    mem_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    mem_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_data = gbit_cleared_w1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    gbit_reset_done = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_reset_done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    thread_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    thread_wr_idx = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_idx = cr_dst_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    thread_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_data = result_cap[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    cr_wr_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_addr = cr_dst_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_data = result_cap;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    cr_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$25  = cr_src_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$25  = sub_cr_src;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$26  = cr_dst_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$26  = sub_cr_dst;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$27  = index_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$27  = sub_index;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$28  = direct_mode;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$28  = 1'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$29  = direct_gt_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$29  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$54 ) begin end
    \$30  = m_elevated_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$30  = sub_m_elevated;
          end
    endcase
  end
  assign clist_gt_addr = \$2 [31:0];
  assign \cr15_namespace$8  = cr15_namespace;
  assign local_mem_wr_en = mem_wr_en;
  assign local_mem_wr_data = mem_wr_data;
  assign \mem_rd_data$21  = mem_rd_data;
  assign \ns_entry_addr_out$25  = ns_entry_addr_out;
  assign fault_type_reg = sub_fault_type;
  assign outform_gt_raw_reg = outform_gt_raw;
  assign outform_slot_id_reg = outform_slot_id;
  assign outform_clist_addr_reg = outform_clist_addr;
  
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign outform_fault_in = 1'h0;
  assign outform_done_in = 1'h0;
  assign outform_fault_type_in = 5'h00;
  assign \src_cap.word0_gt  = src_cap[31:0];
  assign \src_cap.word0_gt.slot_id  = src_cap[15:0];
  assign \src_cap.word0_gt.gt_seq  = src_cap[24:16];
  assign \src_cap.word0_gt.gt_type  = src_cap[26:25];
  assign \src_cap.word0_gt.dom  = src_cap[27];
  assign \src_cap.word0_gt.perm  = src_cap[30:28];
  assign \src_cap.word0_gt.b_flag  = src_cap[31];
  assign \src_cap.word1_location  = src_cap[63:32];
  assign \src_cap.word2_w2  = src_cap[95:64];
  assign \result_cap.word0_gt  = result_cap[31:0];
  assign \result_cap.word0_gt.slot_id  = result_cap[15:0];
  assign \result_cap.word0_gt.gt_seq  = result_cap[24:16];
  assign \result_cap.word0_gt.gt_type  = result_cap[26:25];
  assign \result_cap.word0_gt.dom  = result_cap[27];
  assign \result_cap.word0_gt.perm  = result_cap[30:28];
  assign \result_cap.word0_gt.b_flag  = result_cap[31];
  assign \result_cap.word1_location  = result_cap[63:32];
  assign \result_cap.word2_w2  = result_cap[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$8.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$8.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$8.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$8.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$8.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$8.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$8.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$8.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$8.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \$1  = { 1'h0, index_reg, 2'h0 };
  assign \$3 [30] = 1'h0;
  assign { \$3 [32:31], \$3 [29:0] } = { 1'h0, ns_w1_saved[31], ns_w1_saved[29:0] };
endmodule

(* src = "/home/runner/workspace/hardware/ns_gate.py:80" *)
(* generator = "Amaranth" *)
module \top.core.u_eloadcall.u_mload.u_ns_gate (clk, mem_rd_valid, ns_entry_addr, ns_gate_busy, ns_gate_fault, ns_gate_done, cr15_namespace, ns_gate_start, gt_word0, mem_addr, mem_rd_en, raw_base_reg, raw_w2_reg, ns_abstract_gt, ns_gate_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$55  = 0;
  wire [22:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  reg [31:0] \$15 ;
  reg [31:0] \$16 ;
  reg [31:0] \$17 ;
  reg [31:0] \$18 ;
  reg [4:0] \$19 ;
  wire [32:0] \$2 ;
  reg [31:0] \$20 ;
  reg [2:0] \$21 ;
  wire [31:0] \$3 ;
  wire [32:0] \$4 ;
  wire [32:0] \$5 ;
  wire [32:0] \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$24 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:103" *)
  wire [31:0] computed_integrity;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  reg [31:0] gt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:99" *)
  wire gt_seq_match;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  input [31:0] gt_word0;
  wire [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  output [31:0] mem_addr;
  reg [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:76" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  output [31:0] ns_abstract_gt;
  reg [31:0] ns_abstract_gt = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  output [31:0] ns_entry_addr;
  wire [31:0] ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  output ns_gate_busy;
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  output ns_gate_done;
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  output ns_gate_fault;
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  output [4:0] ns_gate_fault_type;
  reg [4:0] ns_gate_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  input ns_gate_start;
  wire ns_gate_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] ns_gate_state = 3'h0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  output [31:0] raw_base_reg;
  reg [31:0] raw_base_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  reg [31:0] raw_integrity_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  output [31:0] raw_w2_reg;
  reg [31:0] raw_w2_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  wire [31:0] raw_w3_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:106" *)
  wire seal_ok;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  assign \$2  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/ns_gate.py:93" *) \$1 ;
  assign gt_seq_match = gt_latched[24:16] == (* src = "/home/runner/workspace/hardware/ns_gate.py:100" *) raw_w2_reg[29:21];
  assign \$3  = { raw_base_reg[24:0], raw_base_reg[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign seal_ok = computed_integrity == (* src = "/home/runner/workspace/hardware/ns_gate.py:107" *) raw_integrity_reg;
  assign \$4  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:135" *) 3'h4;
  assign \$5  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:148" *) 4'h8;
  assign \$6  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:170" *) 4'hc;
  assign ns_gate_busy = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:184" *) \$7 ;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) ns_gate_state;
  assign \$8  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign ns_gate_fault = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$12  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign ns_gate_done = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:156" *) gt_seq_match;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:159" *) seal_ok;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  always @(posedge clk)
    gt_latched <= \$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:86" *)
  always @(posedge clk)
    raw_base_reg <= \$16 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:87" *)
  always @(posedge clk)
    raw_w2_reg <= \$17 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  always @(posedge clk)
    ns_abstract_gt <= \$18 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  always @(posedge clk)
    ns_gate_fault_type <= \$19 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  always @(posedge clk)
    raw_integrity_reg <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    ns_gate_state <= \$21 ;
  assign \$auto$rtlil.cc:2739:Not$24  = ~ { \$3 [31:30], \$3 [28:25], \$3 [23], \$3 [21], \$3 [19:18], \$3 [16:15], \$3 [13:9], \$3 [7:5], \$3 [3:0] };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    mem_addr = 32'd0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_addr = \$2 [31:0];
      3'h2:
          mem_addr = \$4 [31:0];
      3'h3:
          mem_addr = \$5 [31:0];
      3'h4:
          /* empty */;
      3'h6:
          mem_addr = \$6 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    mem_rd_en = 1'h0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_en = 1'h1;
      3'h2:
          mem_rd_en = 1'h1;
      3'h3:
          mem_rd_en = 1'h1;
      3'h4:
          /* empty */;
      3'h6:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    \$15  = gt_latched;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$15  = gt_word0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    \$16  = raw_base_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$16  = 32'd0;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$16  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    \$17  = raw_w2_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$17  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          if (mem_rd_valid) begin
            \$17  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    \$18  = ns_abstract_gt;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$18  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          if (mem_rd_valid) begin
            \$18  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    \$19  = ns_gate_fault_type;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$19  = 5'h00;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (\$13 ) begin
            \$19  = 5'h09;
          end else if (\$14 ) begin
            \$19  = 5'h0a;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    \$20  = raw_integrity_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$20  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          if (mem_rd_valid) begin
            \$20  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$55 ) begin end
    \$21  = ns_gate_state;
    (* full_case = 32'd1 *)
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$21  = 3'h1;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$21  = 3'h2;
          end
      3'h2:
          if (mem_rd_valid) begin
            \$21  = 3'h3;
          end
      3'h3:
          if (mem_rd_valid) begin
            \$21  = 3'h4;
          end
      3'h4:
          (* full_case = 32'd1 *)
          if (\$13 ) begin
            \$21  = 3'h5;
          end else if (\$14 ) begin
            \$21  = 3'h5;
          end else begin
            \$21  = 3'h6;
          end
      3'h6:
          if (mem_rd_valid) begin
            \$21  = 3'h7;
          end
      3'h7:
          \$21  = 3'h0;
      3'h5:
          \$21  = 3'h0;
    endcase
  end
  assign w0_rot = { raw_base_reg[24:0], raw_base_reg[31:25] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign fault_type_reg = ns_gate_fault_type;
  assign raw_base = raw_base_reg;
  assign raw_w2 = raw_w2_reg;
  assign raw_w3_reg = ns_abstract_gt;
  assign ns_entry_addr_out = \$2 [31:0];
  
  assign ns_entry_addr = \$2 [31:0];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \$1  = { 3'h0, gt_latched[15:0], 4'h0 };
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = raw_w2_reg[29:0];
  assign { computed_integrity[29], computed_integrity[24], computed_integrity[22], computed_integrity[20], computed_integrity[17], computed_integrity[14], computed_integrity[8], computed_integrity[4] } = { \$3 [29], \$3 [24], \$3 [22], \$3 [20], \$3 [17], \$3 [14], \$3 [8], \$3 [4] };
  assign { computed_integrity[31:30], computed_integrity[28:25], computed_integrity[23], computed_integrity[21], computed_integrity[19:18], computed_integrity[16:15], computed_integrity[13:9], computed_integrity[7:5], computed_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$24 ;
endmodule

(* src = "/home/runner/workspace/hardware/gc_unit.py:33" *)
(* generator = "Amaranth" *)
module \top.core.u_gc_unit (clk, \port$4577$0 , g_bit_reset, ns_addr, ns_rd_en, ns_wr_data, ns_wr_en, garbage_count, gc_busy);
  reg \$auto$verilog_backend.cc:2355:dump_module$56  = 0;
  wire [9:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire [32:0] \$13 ;
  wire [16:0] \$14 ;
  wire \$15 ;
  wire [32:0] \$16 ;
  wire [16:0] \$17 ;
  wire \$18 ;
  wire [16:0] \$19 ;
  wire \$2 ;
  wire \$20 ;
  reg [15:0] \$21 ;
  reg [31:0] \$22 ;
  reg [31:0] \$23 ;
  reg [2:0] \$24 ;
  reg [95:0] \$25 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:35" *)
  reg [15:0] current_index = 16'h0000;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:28" *)
  input g_bit_reset;
  wire g_bit_reset;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:37" *)
  output [31:0] garbage_count;
  reg [31:0] garbage_count = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/gc_unit.py:37" *)
  wire [31:0] garbage_counter;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:13" *)
  output gc_busy;
  wire gc_busy;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:14" *)
  wire gc_done;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:11" *)
  wire gc_mark_en;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:10" *)
  wire gc_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] gc_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:12" *)
  wire gc_sweep_en;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:45" *)
  reg [95:0] latched_entry = 96'h000000000000000000000000;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/gc_unit.py:36" *)
  wire [31:0] mark_counter;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:25" *)
  reg [31:0] marked_count = 32'd0;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:50" *)
  wire [6:0] next_version;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:16" *)
  output [31:0] ns_addr;
  reg [31:0] ns_addr;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:23" *)
  wire [15:0] ns_end_index;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:18" *)
  wire [95:0] ns_rd_data;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:17" *)
  output ns_rd_en;
  reg ns_rd_en;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:22" *)
  wire [15:0] ns_start_index;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:19" *)
  output [95:0] ns_wr_data;
  reg [95:0] ns_wr_data;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:20" *)
  output ns_wr_en;
  reg ns_wr_en;
  input [31:0] \port$4577$0 ;
  wire [31:0] \port$4577$0 ;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:125" *)
  reg [95:0] swept_entry;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:28" *)
  wire valid_key_access;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:79" *)
  reg [95:0] wr_entry;
  assign \$1  = latched_entry[61:53] + (* src = "/home/runner/workspace/hardware/gc_unit.py:51" *) 1'h1;
  assign \$2  = ~ (* src = "/home/runner/workspace/hardware/gc_unit.py:148" *) \$4 ;
  assign \$3  = ~ (* src = "/home/runner/workspace/hardware/gc_unit.py:148" *) gc_done;
  assign gc_busy = \$2  & (* src = "/home/runner/workspace/hardware/gc_unit.py:148" *) \$3 ;
  assign \$4  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) gc_state;
  assign \$5  = gc_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$6  = gc_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$7  = gc_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign gc_done = gc_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$8  = gc_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$9  = gc_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$12  = ~ (* src = "/home/runner/workspace/hardware/gc_unit.py:91" *) latched_entry[62];
  assign \$13  = marked_count + (* src = "/home/runner/workspace/hardware/gc_unit.py:92" *) 1'h1;
  assign \$14  = current_index + (* src = "/home/runner/workspace/hardware/gc_unit.py:94" *) 1'h1;
  assign \$15  = current_index >= (* src = "/home/runner/workspace/hardware/gc_unit.py:96" *) 13'h1000;
  assign \$16  = garbage_count + (* src = "/home/runner/workspace/hardware/gc_unit.py:115" *) 1'h1;
  assign \$17  = current_index + (* src = "/home/runner/workspace/hardware/gc_unit.py:118" *) 1'h1;
  assign \$18  = current_index >= (* src = "/home/runner/workspace/hardware/gc_unit.py:119" *) 13'h1000;
  assign \$19  = current_index + (* src = "/home/runner/workspace/hardware/gc_unit.py:138" *) 1'h1;
  assign \$20  = current_index >= (* src = "/home/runner/workspace/hardware/gc_unit.py:139" *) 13'h1000;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:35" *)
  always @(posedge clk)
    current_index <= \$21 ;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:36" *)
  always @(posedge clk)
    marked_count <= \$22 ;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:37" *)
  always @(posedge clk)
    garbage_count <= \$23 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    gc_state <= \$24 ;
  (* src = "/home/runner/workspace/hardware/gc_unit.py:45" *)
  always @(posedge clk)
    latched_entry <= \$25 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    ns_addr = 32'd0;
    casez (gc_state)
      3'h0:
          /* empty */;
      3'h1:
          ns_addr = { 16'h0000, current_index };
      3'h3:
          ns_addr = { 16'h0000, current_index };
      3'h2:
          ns_addr = { 16'h0000, current_index };
      3'h5:
          /* empty */;
      3'h6:
          ns_addr = { 16'h0000, current_index };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    ns_rd_en = 1'h0;
    casez (gc_state)
      3'h0:
          /* empty */;
      3'h1:
          ns_rd_en = 1'h1;
      3'h3:
          /* empty */;
      3'h2:
          ns_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    wr_entry = 96'h000000000000000000000000;
    casez (gc_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
        begin
          { wr_entry[95:63], wr_entry[61:0] } = { latched_entry[95:63], latched_entry[61:0] };
          wr_entry[62] = 1'h1;
        end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    ns_wr_data = 96'h000000000000000000000000;
    casez (gc_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          ns_wr_data = wr_entry;
      3'h2:
          /* empty */;
      3'h5:
          /* empty */;
      3'h6:
          ns_wr_data = swept_entry;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    ns_wr_en = 1'h0;
    casez (gc_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          ns_wr_en = 1'h1;
      3'h2:
          /* empty */;
      3'h5:
          /* empty */;
      3'h6:
          ns_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    swept_entry = 96'h000000000000000000000000;
    casez (gc_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          /* empty */;
      3'h2:
          /* empty */;
      3'h5:
          /* empty */;
      3'h6:
        begin
          { swept_entry[95:62], swept_entry[52:0] } = 87'h0000000000000000000000;
          swept_entry[61:53] = { 2'h0, \$1 [6:0] };
        end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    \$21  = current_index;
    casez (gc_state)
      3'h0:
          if (\$10 ) begin
            \$21  = 16'h0001;
          end else if (\$11 ) begin
            \$21  = 16'h0001;
          end
      3'h1:
          /* empty */;
      3'h3:
        begin
          \$21  = \$14 [15:0];
          if (\$15 ) begin
            \$21  = 16'h0001;
          end
        end
      3'h2:
          /* empty */;
      3'h5:
          (* full_case = 32'd1 *)
          if (latched_entry[62]) begin
          end else begin
            \$21  = \$17 [15:0];
          end
      3'h6:
          \$21  = \$19 [15:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    \$22  = marked_count;
    casez (gc_state)
      3'h0:
          if (\$10 ) begin
            \$22  = 32'd0;
          end else if (\$11 ) begin
            \$22  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h3:
          if (\$12 ) begin
            \$22  = \$13 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    \$23  = garbage_count;
    casez (gc_state)
      3'h0:
          if (\$10 ) begin
            \$23  = 32'd0;
          end else if (\$11 ) begin
            \$23  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h3:
          /* empty */;
      3'h2:
          /* empty */;
      3'h5:
          if (latched_entry[62]) begin
            \$23  = \$16 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    \$24  = gc_state;
    casez (gc_state)
      3'h0:
          if (\$10 ) begin
            \$24  = 3'h1;
          end else if (\$11 ) begin
            \$24  = 3'h2;
          end
      3'h1:
          \$24  = 3'h3;
      3'h3:
          (* full_case = 32'd1 *)
          if (\$15 ) begin
            \$24  = 3'h2;
          end else begin
            \$24  = 3'h1;
          end
      3'h2:
          \$24  = 3'h5;
      3'h5:
          (* full_case = 32'd1 *)
          if (latched_entry[62]) begin
            \$24  = 3'h6;
          end else begin
            (* full_case = 32'd1 *)
            if (\$18 ) begin
              \$24  = 3'h4;
            end else begin
              \$24  = 3'h2;
            end
          end
      3'h6:
          (* full_case = 32'd1 *)
          if (\$20 ) begin
            \$24  = 3'h4;
          end else begin
            \$24  = 3'h2;
          end
      3'h4:
          \$24  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$56 ) begin end
    \$25  = latched_entry;
    casez (gc_state)
      3'h0:
          /* empty */;
      3'h1:
          \$25  = { 64'h0000000000000000, \port$4577$0  };
      3'h3:
          /* empty */;
      3'h2:
          \$25  = { 64'h0000000000000000, \port$4577$0  };
    endcase
  end
  assign next_version = \$1 [6:0];
  assign mark_counter = marked_count;
  assign garbage_counter = garbage_count;
  assign valid_key_access = g_bit_reset;
  
  assign gc_start = 1'h0;
  assign gc_mark_en = 1'h1;
  assign gc_sweep_en = 1'h1;
  assign ns_start_index = 16'h0001;
  assign ns_rd_data = { 64'h0000000000000000, \port$4577$0  };
  assign ns_end_index = 16'h1000;
  assign \$10  = 1'h0;
  assign \$11  = 1'h0;
endmodule

(* src = "/home/runner/workspace/hardware/irq_dispatch.py:56" *)
(* generator = "Amaranth" *)
module \top.core.u_irq_dispatch (clk, mem_rd_valid, irq_reason, irq_slot, start, nia_value, busy, complete, cr15_namespace, mem_rd_addr, mem_rd_en, dr_wr_en, dr1_wr_en, reason_lat, slot_lat, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$57  = 0;
  wire [32:0] \$1 ;
  reg [1:0] \$10 ;
  reg [15:0] \$11 ;
  reg [2:0] \$12 ;
  reg [31:0] \$13 ;
  reg [31:0] \$14 ;
  wire [34:0] \$2 ;
  wire [35:0] \$3 ;
  wire [32:0] \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:33" *)
  output busy;
  wire busy;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:52" *)
  output complete;
  wire complete;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:36" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:50" *)
  wire [31:0] dr1_wr_data;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:49" *)
  output dr1_wr_en;
  reg dr1_wr_en;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:45" *)
  wire [3:0] dr_wr_addr;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:46" *)
  wire [31:0] dr_wr_data;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:44" *)
  output dr_wr_en;
  reg dr_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] irq_dispatch_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:67" *)
  wire [31:0] irq_ns_addr;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:31" *)
  input [1:0] irq_reason;
  wire [1:0] irq_reason;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:32" *)
  input [15:0] irq_slot;
  wire [15:0] irq_slot;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:38" *)
  output [31:0] mem_rd_addr;
  reg [31:0] mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:40" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:39" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:41" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:61" *)
  reg [31:0] method_entry = 32'd0;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:52" *)
  wire nia_set;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:53" *)
  output [31:0] nia_value;
  wire [31:0] nia_value;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:60" *)
  reg [31:0] ns_base = 32'd0;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:58" *)
  output [1:0] reason_lat;
  reg [1:0] reason_lat = 2'h0;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:59" *)
  output [15:0] slot_lat;
  reg [15:0] slot_lat = 16'h0000;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:30" *)
  input start;
  wire start;
  assign \$1  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/irq_dispatch.py:69" *) 8'h80;
  assign \$3  = ns_base + (* src = "/home/runner/workspace/hardware/irq_dispatch.py:76" *) \$2 ;
  assign \$4  = ns_base + (* src = "/home/runner/workspace/hardware/irq_dispatch.py:102" *) 5'h14;
  assign busy = ~ (* src = "/home/runner/workspace/hardware/irq_dispatch.py:123" *) \$5 ;
  assign \$5  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) irq_dispatch_state;
  assign \$6  = irq_dispatch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$7  = irq_dispatch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$8  = irq_dispatch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$9  = irq_dispatch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign complete = irq_dispatch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:58" *)
  always @(posedge clk)
    reason_lat <= \$10 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:59" *)
  always @(posedge clk)
    slot_lat <= \$11 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    irq_dispatch_state <= \$12 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:60" *)
  always @(posedge clk)
    ns_base <= \$13 ;
  (* src = "/home/runner/workspace/hardware/irq_dispatch.py:61" *)
  always @(posedge clk)
    method_entry <= \$14 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    mem_rd_addr = 32'd0;
    casez (irq_dispatch_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_addr = \$1 [31:0];
      3'h2:
          mem_rd_addr = \$4 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    mem_rd_en = 1'h0;
    casez (irq_dispatch_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_en = 1'h1;
      3'h2:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    dr_wr_en = 1'h0;
    casez (irq_dispatch_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          dr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    dr1_wr_en = 1'h0;
    casez (irq_dispatch_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          dr1_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    \$10  = reason_lat;
    casez (irq_dispatch_state)
      3'h0:
          if (start) begin
            \$10  = irq_reason;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    \$11  = slot_lat;
    casez (irq_dispatch_state)
      3'h0:
          if (start) begin
            \$11  = irq_slot;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    \$12  = irq_dispatch_state;
    casez (irq_dispatch_state)
      3'h0:
          if (start) begin
            \$12  = 3'h1;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$12  = 3'h2;
          end
      3'h2:
          if (mem_rd_valid) begin
            \$12  = 3'h3;
          end
      3'h3:
          \$12  = 3'h4;
      3'h4:
          \$12  = 3'h5;
      3'h5:
          \$12  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    \$13  = ns_base;
    casez (irq_dispatch_state)
      3'h0:
          /* empty */;
      3'h1:
          if (mem_rd_valid) begin
            \$13  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$57 ) begin end
    \$14  = method_entry;
    casez (irq_dispatch_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          if (mem_rd_valid) begin
            \$14  = mem_rd_data;
          end
    endcase
  end
  assign irq_ns_addr = \$1 [31:0];
  assign dr_wr_addr = 4'h0;
  assign dr_wr_data = { 30'h00000000, reason_lat };
  assign dr1_wr_data = { 16'h0000, slot_lat };
  assign nia_set = complete;
  
  assign nia_value = \$3 [31:0];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \$2  = { 1'h0, method_entry, 2'h0 };
endmodule

(* src = "/home/runner/workspace/hardware/lambda_unit.py:25" *)
(* generator = "Amaranth" *)
module \top.core.u_lambda (clk, cr_rd_data, lambda_busy, lambda_complete, cr_rd_addr, nia_set, nia_value, lambda_fault, fault_type, cr_target, lambda_start);
  reg \$auto$verilog_backend.cc:2355:dump_module$58  = 0;
  wire \$1 ;
  reg [3:0] \$10 ;
  reg [2:0] \$11 ;
  reg [95:0] \$12 ;
  wire \$2 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  reg \$9 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:17" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:18" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:11" *)
  input [3:0] cr_target;
  wire [3:0] cr_target;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:35" *)
  wire fault_flag;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:36" *)
  wire [3:0] fault_latched;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:36" *)
  output [3:0] fault_type;
  reg [3:0] fault_type = 4'h0;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:32" *)
  wire is_null;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:12" *)
  output lambda_busy;
  wire lambda_busy;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:13" *)
  output lambda_complete;
  wire lambda_complete;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:35" *)
  output lambda_fault;
  reg lambda_fault = 1'h0;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:10" *)
  input lambda_start;
  wire lambda_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] lambda_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:20" *)
  output nia_set;
  reg nia_set;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:21" *)
  output [31:0] nia_value;
  reg [31:0] nia_value;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  reg [95:0] target_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire [31:0] \target_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire \target_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire \target_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire [8:0] \target_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire [1:0] \target_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire [2:0] \target_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire [15:0] \target_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire [31:0] \target_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  wire [31:0] \target_cap.word2_w2 ;
  assign is_null = ! (* src = "/home/runner/workspace/hardware/lambda_unit.py:33" *) target_cap[26:25];
  assign lambda_busy = ~ (* src = "/home/runner/workspace/hardware/lambda_unit.py:74" *) \$1 ;
  assign \$1  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) lambda_state;
  assign \$2  = lambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$3  = lambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$4  = lambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$5  = lambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign lambda_complete = lambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$6  = ~ (* src = "/home/runner/workspace/hardware/lambda_unit.py:31" *) target_cap[27];
  assign \$7  = \$6  & (* src = "/home/runner/workspace/hardware/lambda_unit.py:31" *) target_cap[30];
  assign \$8  = ~ (* src = "/home/runner/workspace/hardware/lambda_unit.py:54" *) \$7 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:35" *)
  always @(posedge clk)
    lambda_fault <= \$9 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:36" *)
  always @(posedge clk)
    fault_type <= \$10 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    lambda_state <= \$11 ;
  (* src = "/home/runner/workspace/hardware/lambda_unit.py:27" *)
  always @(posedge clk)
    target_cap <= \$12 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$58 ) begin end
    cr_rd_addr = 4'h0;
    casez (lambda_state)
      3'h0:
          if (lambda_start) begin
            cr_rd_addr = cr_target;
          end
      3'h1:
          cr_rd_addr = cr_target;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$58 ) begin end
    nia_set = 1'h0;
    casez (lambda_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          nia_set = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$58 ) begin end
    nia_value = 32'd0;
    casez (lambda_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          nia_value = target_cap[63:32];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$58 ) begin end
    \$9  = lambda_fault;
    casez (lambda_state)
      3'h0:
          \$9  = 1'h0;
      3'h1:
          /* empty */;
      3'h2:
          if (is_null) begin
            \$9  = 1'h1;
          end else if (\$8 ) begin
            \$9  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$58 ) begin end
    \$10  = fault_type;
    casez (lambda_state)
      3'h0:
          \$10  = 4'h0;
      3'h1:
          /* empty */;
      3'h2:
          if (is_null) begin
            \$10  = 4'h7;
          end else if (\$8 ) begin
            \$10  = 4'h3;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$58 ) begin end
    \$11  = lambda_state;
    casez (lambda_state)
      3'h0:
          if (lambda_start) begin
            \$11  = 3'h1;
          end
      3'h1:
          \$11  = 3'h2;
      3'h2:
          (* full_case = 32'd1 *)
          if (is_null) begin
            \$11  = 3'h3;
          end else if (\$8 ) begin
            \$11  = 3'h3;
          end else begin
            \$11  = 3'h4;
          end
      3'h4:
          \$11  = 3'h5;
      3'h5:
          \$11  = 3'h0;
      3'h3:
          \$11  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$58 ) begin end
    \$12  = target_cap;
    casez (lambda_state)
      3'h0:
          /* empty */;
      3'h1:
          \$12  = cr_rd_data;
    endcase
  end
  assign fault_flag = lambda_fault;
  assign fault_latched = fault_type;
  
  assign \target_cap.word0_gt  = target_cap[31:0];
  assign \target_cap.word0_gt.slot_id  = target_cap[15:0];
  assign \target_cap.word0_gt.gt_seq  = target_cap[24:16];
  assign \target_cap.word0_gt.gt_type  = target_cap[26:25];
  assign \target_cap.word0_gt.dom  = target_cap[27];
  assign \target_cap.word0_gt.perm  = target_cap[30:28];
  assign \target_cap.word0_gt.b_flag  = target_cap[31];
  assign \target_cap.word1_location  = target_cap[63:32];
  assign \target_cap.word2_w2  = target_cap[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
endmodule

(* src = "/home/runner/workspace/hardware/load.py:31" *)
(* generator = "Amaranth" *)
module \top.core.u_load (clk, mload_m_elevated, load_busy, load_fault, mload_busy, mload_fault, mload_done, mload_start, fault_type, \port$5930$0 , load_start);
  reg \$auto$verilog_backend.cc:2355:dump_module$59  = 0;
  wire \$1 ;
  wire \$2 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  reg [1:0] \$6 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/load.py:10" *)
  wire [3:0] cr_dst;
  (* src = "/home/runner/workspace/hardware/load.py:9" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/load.py:28" *)
  input [4:0] fault_type;
  wire [4:0] fault_type;
  (* src = "/home/runner/workspace/hardware/load.py:11" *)
  wire [15:0] index;
  (* src = "/home/runner/workspace/hardware/load.py:12" *)
  output load_busy;
  wire load_busy;
  (* src = "/home/runner/workspace/hardware/load.py:13" *)
  wire load_complete;
  (* src = "/home/runner/workspace/hardware/load.py:14" *)
  output load_fault;
  wire load_fault;
  (* src = "/home/runner/workspace/hardware/load.py:8" *)
  input load_start;
  wire load_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [1:0] load_wrapper_state = 2'h0;
  (* src = "/home/runner/workspace/hardware/load.py:25" *)
  input mload_busy;
  wire mload_busy;
  (* src = "/home/runner/workspace/hardware/load.py:19" *)
  wire [3:0] mload_cr_dst;
  (* src = "/home/runner/workspace/hardware/load.py:18" *)
  wire [3:0] mload_cr_src;
  (* src = "/home/runner/workspace/hardware/load.py:21" *)
  wire mload_direct;
  (* src = "/home/runner/workspace/hardware/load.py:22" *)
  wire [31:0] mload_direct_gt;
  (* src = "/home/runner/workspace/hardware/load.py:26" *)
  input mload_done;
  wire mload_done;
  (* src = "/home/runner/workspace/hardware/load.py:27" *)
  input mload_fault;
  wire mload_fault;
  (* src = "/home/runner/workspace/hardware/load.py:28" *)
  wire [4:0] mload_fault_type;
  (* src = "/home/runner/workspace/hardware/load.py:20" *)
  wire [15:0] mload_index;
  (* src = "/home/runner/workspace/hardware/load.py:23" *)
  output mload_m_elevated;
  wire mload_m_elevated;
  (* src = "/home/runner/workspace/hardware/load.py:17" *)
  output mload_start;
  reg mload_start;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  assign load_fault = \$4  & (* src = "/home/runner/workspace/hardware/load.py:60" *) mload_fault;
  assign \$1  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) load_wrapper_state;
  assign \$2  = load_wrapper_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$3  = load_wrapper_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$4  = load_wrapper_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$5  = mload_done | (* src = "/home/runner/workspace/hardware/load.py:54" *) mload_fault;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    load_wrapper_state <= \$6 ;
  assign mload_m_elevated = \port$5930$0 [18:15] == (* src = "/home/runner/workspace/hardware/load.py:39" *) 3'h6;
  assign load_busy = ~ (* src = "/home/runner/workspace/hardware/load.py:58" *) \$1 ;
  assign load_complete = \$4  & (* src = "/home/runner/workspace/hardware/load.py:59" *) mload_done;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$59 ) begin end
    mload_start = 1'h0;
    casez (load_wrapper_state)
      2'h0:
          /* empty */;
      2'h1:
          mload_start = 1'h1;
      2'h2:
          mload_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$59 ) begin end
    \$6  = load_wrapper_state;
    (* full_case = 32'd1 *)
    casez (load_wrapper_state)
      2'h0:
          if (load_start) begin
            \$6  = 2'h1;
          end
      2'h1:
          \$6  = 2'h2;
      2'h2:
          if (mload_busy) begin
            \$6  = 2'h3;
          end
      2'h3:
          if (\$5 ) begin
            \$6  = 2'h0;
          end
    endcase
  end
  assign mload_cr_src = \port$5930$0 [18:15];
  assign cr_src = \port$5930$0 [18:15];
  assign mload_cr_dst = \port$5930$0 [22:19];
  assign cr_dst = \port$5930$0 [22:19];
  assign mload_index = { 1'h0, \port$5930$0 [14:0] };
  assign index = { 1'h0, \port$5930$0 [14:0] };
  assign mload_direct = 1'h0;
  assign mload_direct_gt = 32'd0;
  assign mload_fault_type = fault_type;
  
endmodule

(* src = "/home/runner/workspace/hardware/outform.py:126" *)
(* generator = "Amaranth" *)
module \top.core.u_outform (clk, gt_raw, slot_id, alloc_done, alloc_fault, alloc_base, mint_done, mint_result_gt, mint_fault, tx_byte, outform_busy, tx_valid, alloc_req, alloc_n, mem_wr_addr, mem_wr_data, mem_wr_en, mint_call, outform_done, outform_fault, result_gt, outform_fault_type
, mint_base, outform_start);
  reg \$auto$verilog_backend.cc:2355:dump_module$60  = 0;
  wire [31:0] \$1 ;
  wire [31:0] \$10 ;
  wire \$100 ;
  wire \$101 ;
  wire [32:0] \$102 ;
  wire [32:0] \$103 ;
  wire \$104 ;
  wire [2:0] \$105 ;
  wire \$106 ;
  wire \$107 ;
  wire \$108 ;
  wire \$109 ;
  wire [31:0] \$11 ;
  wire [31:0] \$110 ;
  wire [6:0] \$111 ;
  wire \$112 ;
  wire [38:0] \$113 ;
  wire [38:0] \$114 ;
  wire [6:0] \$115 ;
  wire [32:0] \$116 ;
  wire \$117 ;
  wire \$118 ;
  wire \$119 ;
  wire [31:0] \$12 ;
  wire \$120 ;
  wire \$121 ;
  wire \$122 ;
  wire \$123 ;
  wire \$124 ;
  wire \$125 ;
  wire \$126 ;
  wire \$127 ;
  wire \$128 ;
  wire \$129 ;
  wire [31:0] \$13 ;
  wire \$130 ;
  wire \$131 ;
  wire \$132 ;
  wire \$133 ;
  wire \$134 ;
  wire \$135 ;
  wire \$136 ;
  wire \$137 ;
  wire \$138 ;
  wire \$139 ;
  wire [31:0] \$14 ;
  wire \$140 ;
  wire \$141 ;
  wire \$142 ;
  wire \$143 ;
  wire [9:0] \$144 ;
  wire [31:0] \$145 ;
  wire [6:0] \$146 ;
  wire \$147 ;
  wire \$148 ;
  wire \$149 ;
  wire [31:0] \$15 ;
  wire \$150 ;
  wire [7:0] \$151 ;
  wire [8:0] \$152 ;
  wire [31:0] \$153 ;
  wire [6:0] \$154 ;
  wire [8:0] \$155 ;
  wire [10:0] \$156 ;
  wire [8:0] \$157 ;
  wire [9:0] \$158 ;
  wire [31:0] \$159 ;
  wire [31:0] \$16 ;
  wire [6:0] \$160 ;
  wire [9:0] \$161 ;
  wire [10:0] \$162 ;
  wire [31:0] \$163 ;
  wire [6:0] \$164 ;
  wire [38:0] \$165 ;
  wire [38:0] \$166 ;
  wire [6:0] \$167 ;
  wire [32:0] \$168 ;
  wire [11:0] \$169 ;
  wire \$17 ;
  wire [32:0] \$170 ;
  wire \$171 ;
  wire [32:0] \$172 ;
  wire [32:0] \$173 ;
  wire \$174 ;
  wire [2:0] \$175 ;
  wire \$176 ;
  wire \$177 ;
  wire \$178 ;
  wire \$179 ;
  wire [32:0] \$18 ;
  reg [8:0] \$180 ;
  reg [8:0] \$181 ;
  wire [9:0] \$182 ;
  wire [31:0] \$183 ;
  wire [6:0] \$184 ;
  reg [8:0] \$185 ;
  wire [9:0] \$186 ;
  wire [31:0] \$187 ;
  wire [6:0] \$188 ;
  reg [8:0] \$189 ;
  wire [32:0] \$19 ;
  wire [9:0] \$190 ;
  wire [31:0] \$191 ;
  wire [6:0] \$192 ;
  reg [8:0] \$193 ;
  wire [9:0] \$194 ;
  wire [31:0] \$195 ;
  wire [6:0] \$196 ;
  reg [8:0] \$197 ;
  wire [9:0] \$198 ;
  wire [31:0] \$199 ;
  wire [31:0] \$2 ;
  wire \$20 ;
  wire [6:0] \$200 ;
  wire [38:0] \$201 ;
  wire [38:0] \$202 ;
  wire [6:0] \$203 ;
  wire [32:0] \$204 ;
  wire \$205 ;
  wire \$206 ;
  wire \$207 ;
  wire \$208 ;
  wire [31:0] \$209 ;
  wire \$21 ;
  wire [6:0] \$210 ;
  wire \$211 ;
  wire [38:0] \$212 ;
  wire [38:0] \$213 ;
  wire [6:0] \$214 ;
  wire [32:0] \$215 ;
  wire \$216 ;
  wire \$217 ;
  wire \$218 ;
  wire \$219 ;
  wire \$22 ;
  reg [14:0] \$220 ;
  reg [14:0] \$221 ;
  wire [15:0] \$222 ;
  wire [31:0] \$223 ;
  wire [6:0] \$224 ;
  reg [14:0] \$225 ;
  wire [15:0] \$226 ;
  wire [31:0] \$227 ;
  wire [6:0] \$228 ;
  reg [14:0] \$229 ;
  wire \$23 ;
  wire [15:0] \$230 ;
  wire [31:0] \$231 ;
  wire [6:0] \$232 ;
  reg [14:0] \$233 ;
  wire [15:0] \$234 ;
  wire [31:0] \$235 ;
  wire [6:0] \$236 ;
  reg [14:0] \$237 ;
  wire [15:0] \$238 ;
  wire [31:0] \$239 ;
  wire \$24 ;
  wire [6:0] \$240 ;
  reg [14:0] \$241 ;
  wire [15:0] \$242 ;
  wire [31:0] \$243 ;
  wire [6:0] \$244 ;
  reg [14:0] \$245 ;
  wire [15:0] \$246 ;
  wire [31:0] \$247 ;
  wire [6:0] \$248 ;
  reg [14:0] \$249 ;
  wire \$25 ;
  wire [15:0] \$250 ;
  wire [31:0] \$251 ;
  wire [6:0] \$252 ;
  reg [14:0] \$253 ;
  wire [15:0] \$254 ;
  wire [31:0] \$255 ;
  wire [6:0] \$256 ;
  wire [38:0] \$257 ;
  wire [38:0] \$258 ;
  wire [6:0] \$259 ;
  wire [34:0] \$26 ;
  wire [32:0] \$260 ;
  wire \$261 ;
  wire \$262 ;
  wire \$263 ;
  wire \$264 ;
  wire \$265 ;
  wire [11:0] \$266 ;
  wire [32:0] \$267 ;
  wire [9:0] \$268 ;
  wire \$269 ;
  wire [35:0] \$27 ;
  wire [32:0] \$270 ;
  wire [32:0] \$271 ;
  wire \$272 ;
  wire [9:0] \$273 ;
  wire \$274 ;
  wire [2:0] \$275 ;
  wire [9:0] \$276 ;
  wire \$277 ;
  wire \$278 ;
  wire [32:0] \$279 ;
  wire \$28 ;
  wire \$280 ;
  wire \$281 ;
  wire \$282 ;
  wire \$283 ;
  wire [32:0] \$284 ;
  wire \$285 ;
  wire [32:0] \$286 ;
  wire \$287 ;
  wire [8:0] \$288 ;
  wire \$289 ;
  wire \$29 ;
  wire [32:0] \$290 ;
  wire [32:0] \$291 ;
  wire \$292 ;
  wire \$293 ;
  wire [2:0] \$294 ;
  wire \$295 ;
  wire \$296 ;
  wire [32:0] \$297 ;
  wire \$298 ;
  reg [5:0] \$299 ;
  wire [31:0] \$3 ;
  wire \$30 ;
  reg [2:0] \$300 ;
  reg [15:0] \$301 ;
  reg [15:0] \$302 ;
  reg [31:0] \$303 ;
  reg [15:0] \$304 ;
  reg [15:0] \$305 ;
  reg [31:0] \$306 ;
  reg [31:0] \$307 ;
  reg [31:0] \$308 ;
  reg [15:0] \$309 ;
  wire \$31 ;
  reg [15:0] \$310 ;
  reg [31:0] \$311 ;
  reg [4:0] \$312 ;
  reg [31:0] \$313 ;
  reg [31:0] \$314 ;
  reg [31:0] \$315 ;
  reg [23:0] \$316 ;
  reg [1:0] \$317 ;
  reg [31:0] \$318 ;
  reg [31:0] \$319 ;
  wire \$32 ;
  reg [5:0] \$320 ;
  reg \$321 ;
  reg [8:0] \$322 ;
  reg [8:0] \$323 ;
  reg [11:0] \$324 ;
  reg [8:0] \$325 ;
  reg [10:0] \$326 ;
  reg [4:0] \$327 ;
  reg [4:0] \$328 ;
  reg [7:0] \$329 ;
  wire [34:0] \$33 ;
  reg [7:0] \$330 ;
  reg [7:0] \$331 ;
  reg [4:0] \$332 ;
  reg [4:0] \$333 ;
  reg [31:0] \$334 ;
  reg [31:0] \$335 ;
  reg [31:0] \$336 ;
  reg [31:0] \$337 ;
  wire [35:0] \$34 ;
  reg [2:0] \$35 ;
  reg [3:0] \$36 ;
  wire \$37 ;
  wire [31:0] \$38 ;
  wire \$39 ;
  wire [31:0] \$4 ;
  wire \$40 ;
  wire \$41 ;
  wire \$42 ;
  wire \$43 ;
  wire [12:0] \$44 ;
  wire [12:0] \$45 ;
  wire \$46 ;
  wire [34:0] \$47 ;
  wire [35:0] \$48 ;
  wire \$49 ;
  wire [31:0] \$5 ;
  wire [34:0] \$50 ;
  wire [35:0] \$51 ;
  wire [31:0] \$52 ;
  wire \$53 ;
  wire \$54 ;
  wire \$55 ;
  wire \$56 ;
  wire \$57 ;
  wire \$58 ;
  wire \$59 ;
  wire [31:0] \$6 ;
  wire \$60 ;
  wire \$61 ;
  wire \$62 ;
  wire \$63 ;
  wire \$64 ;
  wire \$65 ;
  wire \$66 ;
  wire \$67 ;
  wire \$68 ;
  wire \$69 ;
  wire [31:0] \$7 ;
  wire \$70 ;
  wire \$71 ;
  wire \$72 ;
  wire \$73 ;
  wire \$74 ;
  wire \$75 ;
  wire \$76 ;
  wire \$77 ;
  wire \$78 ;
  wire \$79 ;
  wire [31:0] \$8 ;
  wire \$80 ;
  wire \$81 ;
  wire \$82 ;
  wire [3:0] \$83 ;
  wire [6:0] \$84 ;
  wire \$85 ;
  wire \$86 ;
  wire \$87 ;
  wire [31:0] \$88 ;
  wire \$89 ;
  wire [31:0] \$9 ;
  wire \$90 ;
  wire \$91 ;
  wire \$92 ;
  wire \$93 ;
  wire \$94 ;
  wire [16:0] \$95 ;
  wire \$96 ;
  wire [16:0] \$97 ;
  wire \$98 ;
  wire \$99 ;
  wire [31:0] \$auto$rtlil.cc:2739:Not$18 ;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs0;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs1;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs2;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs3;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs4;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs5;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs6;
  (* src = "/home/runner/workspace/hardware/outform.py:119" *)
  wire [31:0] _cs7;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb0;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb1;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb2;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb3;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb4;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb5;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb6;
  (* src = "/home/runner/workspace/hardware/outform.py:118" *)
  wire _cxb7;
  (* src = "/home/runner/workspace/hardware/outform.py:98" *)
  input [31:0] alloc_base;
  wire [31:0] alloc_base;
  (* src = "/home/runner/workspace/hardware/outform.py:96" *)
  input alloc_done;
  wire alloc_done;
  (* src = "/home/runner/workspace/hardware/outform.py:97" *)
  input alloc_fault;
  wire alloc_fault;
  (* src = "/home/runner/workspace/hardware/outform.py:95" *)
  output [4:0] alloc_n;
  reg [4:0] alloc_n;
  (* src = "/home/runner/workspace/hardware/outform.py:94" *)
  output alloc_req;
  reg alloc_req;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/outform.py:146" *)
  wire [31:0] base_reg;
  (* src = "/home/runner/workspace/hardware/outform.py:446" *)
  reg [1:0] btype;
  (* src = "/home/runner/workspace/hardware/outform.py:148" *)
  reg [23:0] byte_buf = 24'h000000;
  (* src = "/home/runner/workspace/hardware/outform.py:149" *)
  reg [1:0] byte_buf_cnt = 2'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/outform.py:194" *)
  wire [6:0] code7_rev;
  (* src = "/home/runner/workspace/hardware/outform.py:195" *)
  wire [7:0] code8_rev;
  (* src = "/home/runner/workspace/hardware/outform.py:196" *)
  wire [8:0] code9_rev;
  (* src = "/home/runner/workspace/hardware/outform.py:137" *)
  reg [31:0] comp_size_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:136" *)
  reg [31:0] crc32_stored = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:156" *)
  reg [31:0] crc_acc = 32'd4294967295;
  (* src = "/home/runner/workspace/hardware/outform.py:153" *)
  reg [7:0] crc_byte_in;
  (* src = "/home/runner/workspace/hardware/outform.py:800" *)
  reg [31:0] crc_final;
  (* src = "/home/runner/workspace/hardware/outform.py:157" *)
  wire [31:0] crc_next;
  (* src = "/home/runner/workspace/hardware/outform.py:173" *)
  reg defl_bfinal = 1'h0;
  (* src = "/home/runner/workspace/hardware/outform.py:172" *)
  reg [5:0] defl_bit_cnt = 6'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:171" *)
  reg [31:0] defl_bits = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:182" *)
  reg [31:0] defl_bytes_out = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:176" *)
  reg [11:0] defl_copy_dist = 12'h000;
  (* src = "/home/runner/workspace/hardware/outform.py:177" *)
  reg [8:0] defl_copy_idx = 9'h000;
  (* src = "/home/runner/workspace/hardware/outform.py:175" *)
  reg [8:0] defl_copy_len = 9'h000;
  (* src = "/home/runner/workspace/hardware/outform.py:180" *)
  reg [4:0] defl_dist_code = 5'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:663" *)
  reg [31:0] defl_hist_depth;
  (* src = "/home/runner/workspace/hardware/outform.py:179" *)
  reg [4:0] defl_len_idx = 5'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:181" *)
  reg [31:0] defl_rx_count = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:174" *)
  reg [8:0] defl_symbol = 9'h000;
  (* src = "/home/runner/workspace/hardware/outform.py:178" *)
  reg [10:0] defl_win_pos = 11'h000;
  (* src = "/home/runner/workspace/hardware/outform.py:197" *)
  wire [4:0] dist5_rev;
  (* src = "/home/runner/workspace/hardware/outform.py:636" *)
  reg [3:0] dist_extra_needed;
  (* src = "/home/runner/workspace/hardware/outform.py:131" *)
  reg [15:0] extra_cnt = 16'h0000;
  (* src = "/home/runner/workspace/hardware/outform.py:140" *)
  reg [15:0] extra_len_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/outform.py:134" *)
  reg [15:0] flags_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/outform.py:130" *)
  reg [15:0] fname_cnt = 16'h0000;
  (* src = "/home/runner/workspace/hardware/outform.py:139" *)
  reg [15:0] fname_len_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/outform.py:85" *)
  input [31:0] gt_raw;
  wire [31:0] gt_raw;
  (* src = "/home/runner/workspace/hardware/outform.py:128" *)
  reg [5:0] hdr_byte_cnt = 6'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:222" *)
  wire [31:0] inflate_word;
  (* src = "/home/runner/workspace/hardware/outform.py:344" *)
  reg is_pow2;
  (* src = "/home/runner/workspace/hardware/outform.py:564" *)
  reg [3:0] len_extra_needed;
  (* src = "/home/runner/workspace/hardware/outform.py:100" *)
  output [31:0] mem_wr_addr;
  reg [31:0] mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/outform.py:101" *)
  output [31:0] mem_wr_data;
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/outform.py:102" *)
  output mem_wr_en;
  reg mem_wr_en;
  (* src = "/home/runner/workspace/hardware/outform.py:135" *)
  reg [15:0] method_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/outform.py:146" *)
  output [31:0] mint_base;
  reg [31:0] mint_base = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:104" *)
  output mint_call;
  reg mint_call;
  (* src = "/home/runner/workspace/hardware/outform.py:107" *)
  input mint_done;
  wire mint_done;
  (* src = "/home/runner/workspace/hardware/outform.py:108" *)
  input mint_fault;
  wire mint_fault;
  (* src = "/home/runner/workspace/hardware/outform.py:106" *)
  reg [4:0] mint_n = 5'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:109" *)
  input [31:0] mint_result_gt;
  wire [31:0] mint_result_gt;
  (* src = "/home/runner/workspace/hardware/outform.py:349" *)
  reg [4:0] n_computed;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/outform.py:143" *)
  wire [4:0] n_reg;
  (* src = "/home/runner/workspace/hardware/outform.py:80" *)
  output outform_busy;
  reg outform_busy;
  (* src = "/home/runner/workspace/hardware/outform.py:81" *)
  output outform_done;
  reg outform_done;
  (* src = "/home/runner/workspace/hardware/outform.py:82" *)
  output outform_fault;
  reg outform_fault;
  (* src = "/home/runner/workspace/hardware/outform.py:83" *)
  output [4:0] outform_fault_type;
  reg [4:0] outform_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:79" *)
  input outform_start;
  wire outform_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [4:0] outform_state = 5'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:151" *)
  output [31:0] result_gt;
  reg [31:0] result_gt = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/outform.py:151" *)
  wire [31:0] result_gt_reg;
  (* src = "/home/runner/workspace/hardware/outform.py:185" *)
  reg [7:0] rle_count = 8'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:186" *)
  reg [7:0] rle_literal = 8'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:187" *)
  reg [7:0] rle_remaining = 8'h00;
  (* src = "/home/runner/workspace/hardware/outform.py:183" *)
  reg [31:0] rle_rx_count = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:92" *)
  wire [7:0] rx_data;
  (* src = "/home/runner/workspace/hardware/outform.py:91" *)
  wire rx_valid;
  (* src = "/home/runner/workspace/hardware/outform.py:133" *)
  reg [31:0] sig_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:86" *)
  input [15:0] slot_id;
  wire [15:0] slot_id;
  (* src = "/home/runner/workspace/hardware/outform.py:144" *)
  reg [31:0] total_words = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:89" *)
  output [7:0] tx_byte;
  reg [7:0] tx_byte;
  (* src = "/home/runner/workspace/hardware/outform.py:129" *)
  reg [2:0] tx_byte_cnt = 3'h0;
  (* src = "/home/runner/workspace/hardware/outform.py:89" *)
  wire [7:0] tx_data;
  (* src = "/home/runner/workspace/hardware/outform.py:88" *)
  output tx_valid;
  reg tx_valid;
  (* src = "/home/runner/workspace/hardware/outform.py:138" *)
  reg [31:0] ucomp_size_reg = 32'd0;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:240" *)
  reg [10:0] win_rd__addr;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:241" *)
  wire [7:0] win_rd__data;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:401" *)
  reg [10:0] win_wr__addr;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:402" *)
  reg [7:0] win_wr__data;
  (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/memory.py:400" *)
  reg win_wr__en;
  (* src = "/home/runner/workspace/hardware/outform.py:142" *)
  reg [31:0] word_count_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:147" *)
  reg [31:0] wr_word_cnt = 32'd0;
  (* src = "/home/runner/workspace/hardware/outform.py:160" *)
  reg [7:0] win_mem [2047:0];
  initial begin
    win_mem[0] = 8'h00;
    win_mem[1] = 8'h00;
    win_mem[2] = 8'h00;
    win_mem[3] = 8'h00;
    win_mem[4] = 8'h00;
    win_mem[5] = 8'h00;
    win_mem[6] = 8'h00;
    win_mem[7] = 8'h00;
    win_mem[8] = 8'h00;
    win_mem[9] = 8'h00;
    win_mem[10] = 8'h00;
    win_mem[11] = 8'h00;
    win_mem[12] = 8'h00;
    win_mem[13] = 8'h00;
    win_mem[14] = 8'h00;
    win_mem[15] = 8'h00;
    win_mem[16] = 8'h00;
    win_mem[17] = 8'h00;
    win_mem[18] = 8'h00;
    win_mem[19] = 8'h00;
    win_mem[20] = 8'h00;
    win_mem[21] = 8'h00;
    win_mem[22] = 8'h00;
    win_mem[23] = 8'h00;
    win_mem[24] = 8'h00;
    win_mem[25] = 8'h00;
    win_mem[26] = 8'h00;
    win_mem[27] = 8'h00;
    win_mem[28] = 8'h00;
    win_mem[29] = 8'h00;
    win_mem[30] = 8'h00;
    win_mem[31] = 8'h00;
    win_mem[32] = 8'h00;
    win_mem[33] = 8'h00;
    win_mem[34] = 8'h00;
    win_mem[35] = 8'h00;
    win_mem[36] = 8'h00;
    win_mem[37] = 8'h00;
    win_mem[38] = 8'h00;
    win_mem[39] = 8'h00;
    win_mem[40] = 8'h00;
    win_mem[41] = 8'h00;
    win_mem[42] = 8'h00;
    win_mem[43] = 8'h00;
    win_mem[44] = 8'h00;
    win_mem[45] = 8'h00;
    win_mem[46] = 8'h00;
    win_mem[47] = 8'h00;
    win_mem[48] = 8'h00;
    win_mem[49] = 8'h00;
    win_mem[50] = 8'h00;
    win_mem[51] = 8'h00;
    win_mem[52] = 8'h00;
    win_mem[53] = 8'h00;
    win_mem[54] = 8'h00;
    win_mem[55] = 8'h00;
    win_mem[56] = 8'h00;
    win_mem[57] = 8'h00;
    win_mem[58] = 8'h00;
    win_mem[59] = 8'h00;
    win_mem[60] = 8'h00;
    win_mem[61] = 8'h00;
    win_mem[62] = 8'h00;
    win_mem[63] = 8'h00;
    win_mem[64] = 8'h00;
    win_mem[65] = 8'h00;
    win_mem[66] = 8'h00;
    win_mem[67] = 8'h00;
    win_mem[68] = 8'h00;
    win_mem[69] = 8'h00;
    win_mem[70] = 8'h00;
    win_mem[71] = 8'h00;
    win_mem[72] = 8'h00;
    win_mem[73] = 8'h00;
    win_mem[74] = 8'h00;
    win_mem[75] = 8'h00;
    win_mem[76] = 8'h00;
    win_mem[77] = 8'h00;
    win_mem[78] = 8'h00;
    win_mem[79] = 8'h00;
    win_mem[80] = 8'h00;
    win_mem[81] = 8'h00;
    win_mem[82] = 8'h00;
    win_mem[83] = 8'h00;
    win_mem[84] = 8'h00;
    win_mem[85] = 8'h00;
    win_mem[86] = 8'h00;
    win_mem[87] = 8'h00;
    win_mem[88] = 8'h00;
    win_mem[89] = 8'h00;
    win_mem[90] = 8'h00;
    win_mem[91] = 8'h00;
    win_mem[92] = 8'h00;
    win_mem[93] = 8'h00;
    win_mem[94] = 8'h00;
    win_mem[95] = 8'h00;
    win_mem[96] = 8'h00;
    win_mem[97] = 8'h00;
    win_mem[98] = 8'h00;
    win_mem[99] = 8'h00;
    win_mem[100] = 8'h00;
    win_mem[101] = 8'h00;
    win_mem[102] = 8'h00;
    win_mem[103] = 8'h00;
    win_mem[104] = 8'h00;
    win_mem[105] = 8'h00;
    win_mem[106] = 8'h00;
    win_mem[107] = 8'h00;
    win_mem[108] = 8'h00;
    win_mem[109] = 8'h00;
    win_mem[110] = 8'h00;
    win_mem[111] = 8'h00;
    win_mem[112] = 8'h00;
    win_mem[113] = 8'h00;
    win_mem[114] = 8'h00;
    win_mem[115] = 8'h00;
    win_mem[116] = 8'h00;
    win_mem[117] = 8'h00;
    win_mem[118] = 8'h00;
    win_mem[119] = 8'h00;
    win_mem[120] = 8'h00;
    win_mem[121] = 8'h00;
    win_mem[122] = 8'h00;
    win_mem[123] = 8'h00;
    win_mem[124] = 8'h00;
    win_mem[125] = 8'h00;
    win_mem[126] = 8'h00;
    win_mem[127] = 8'h00;
    win_mem[128] = 8'h00;
    win_mem[129] = 8'h00;
    win_mem[130] = 8'h00;
    win_mem[131] = 8'h00;
    win_mem[132] = 8'h00;
    win_mem[133] = 8'h00;
    win_mem[134] = 8'h00;
    win_mem[135] = 8'h00;
    win_mem[136] = 8'h00;
    win_mem[137] = 8'h00;
    win_mem[138] = 8'h00;
    win_mem[139] = 8'h00;
    win_mem[140] = 8'h00;
    win_mem[141] = 8'h00;
    win_mem[142] = 8'h00;
    win_mem[143] = 8'h00;
    win_mem[144] = 8'h00;
    win_mem[145] = 8'h00;
    win_mem[146] = 8'h00;
    win_mem[147] = 8'h00;
    win_mem[148] = 8'h00;
    win_mem[149] = 8'h00;
    win_mem[150] = 8'h00;
    win_mem[151] = 8'h00;
    win_mem[152] = 8'h00;
    win_mem[153] = 8'h00;
    win_mem[154] = 8'h00;
    win_mem[155] = 8'h00;
    win_mem[156] = 8'h00;
    win_mem[157] = 8'h00;
    win_mem[158] = 8'h00;
    win_mem[159] = 8'h00;
    win_mem[160] = 8'h00;
    win_mem[161] = 8'h00;
    win_mem[162] = 8'h00;
    win_mem[163] = 8'h00;
    win_mem[164] = 8'h00;
    win_mem[165] = 8'h00;
    win_mem[166] = 8'h00;
    win_mem[167] = 8'h00;
    win_mem[168] = 8'h00;
    win_mem[169] = 8'h00;
    win_mem[170] = 8'h00;
    win_mem[171] = 8'h00;
    win_mem[172] = 8'h00;
    win_mem[173] = 8'h00;
    win_mem[174] = 8'h00;
    win_mem[175] = 8'h00;
    win_mem[176] = 8'h00;
    win_mem[177] = 8'h00;
    win_mem[178] = 8'h00;
    win_mem[179] = 8'h00;
    win_mem[180] = 8'h00;
    win_mem[181] = 8'h00;
    win_mem[182] = 8'h00;
    win_mem[183] = 8'h00;
    win_mem[184] = 8'h00;
    win_mem[185] = 8'h00;
    win_mem[186] = 8'h00;
    win_mem[187] = 8'h00;
    win_mem[188] = 8'h00;
    win_mem[189] = 8'h00;
    win_mem[190] = 8'h00;
    win_mem[191] = 8'h00;
    win_mem[192] = 8'h00;
    win_mem[193] = 8'h00;
    win_mem[194] = 8'h00;
    win_mem[195] = 8'h00;
    win_mem[196] = 8'h00;
    win_mem[197] = 8'h00;
    win_mem[198] = 8'h00;
    win_mem[199] = 8'h00;
    win_mem[200] = 8'h00;
    win_mem[201] = 8'h00;
    win_mem[202] = 8'h00;
    win_mem[203] = 8'h00;
    win_mem[204] = 8'h00;
    win_mem[205] = 8'h00;
    win_mem[206] = 8'h00;
    win_mem[207] = 8'h00;
    win_mem[208] = 8'h00;
    win_mem[209] = 8'h00;
    win_mem[210] = 8'h00;
    win_mem[211] = 8'h00;
    win_mem[212] = 8'h00;
    win_mem[213] = 8'h00;
    win_mem[214] = 8'h00;
    win_mem[215] = 8'h00;
    win_mem[216] = 8'h00;
    win_mem[217] = 8'h00;
    win_mem[218] = 8'h00;
    win_mem[219] = 8'h00;
    win_mem[220] = 8'h00;
    win_mem[221] = 8'h00;
    win_mem[222] = 8'h00;
    win_mem[223] = 8'h00;
    win_mem[224] = 8'h00;
    win_mem[225] = 8'h00;
    win_mem[226] = 8'h00;
    win_mem[227] = 8'h00;
    win_mem[228] = 8'h00;
    win_mem[229] = 8'h00;
    win_mem[230] = 8'h00;
    win_mem[231] = 8'h00;
    win_mem[232] = 8'h00;
    win_mem[233] = 8'h00;
    win_mem[234] = 8'h00;
    win_mem[235] = 8'h00;
    win_mem[236] = 8'h00;
    win_mem[237] = 8'h00;
    win_mem[238] = 8'h00;
    win_mem[239] = 8'h00;
    win_mem[240] = 8'h00;
    win_mem[241] = 8'h00;
    win_mem[242] = 8'h00;
    win_mem[243] = 8'h00;
    win_mem[244] = 8'h00;
    win_mem[245] = 8'h00;
    win_mem[246] = 8'h00;
    win_mem[247] = 8'h00;
    win_mem[248] = 8'h00;
    win_mem[249] = 8'h00;
    win_mem[250] = 8'h00;
    win_mem[251] = 8'h00;
    win_mem[252] = 8'h00;
    win_mem[253] = 8'h00;
    win_mem[254] = 8'h00;
    win_mem[255] = 8'h00;
    win_mem[256] = 8'h00;
    win_mem[257] = 8'h00;
    win_mem[258] = 8'h00;
    win_mem[259] = 8'h00;
    win_mem[260] = 8'h00;
    win_mem[261] = 8'h00;
    win_mem[262] = 8'h00;
    win_mem[263] = 8'h00;
    win_mem[264] = 8'h00;
    win_mem[265] = 8'h00;
    win_mem[266] = 8'h00;
    win_mem[267] = 8'h00;
    win_mem[268] = 8'h00;
    win_mem[269] = 8'h00;
    win_mem[270] = 8'h00;
    win_mem[271] = 8'h00;
    win_mem[272] = 8'h00;
    win_mem[273] = 8'h00;
    win_mem[274] = 8'h00;
    win_mem[275] = 8'h00;
    win_mem[276] = 8'h00;
    win_mem[277] = 8'h00;
    win_mem[278] = 8'h00;
    win_mem[279] = 8'h00;
    win_mem[280] = 8'h00;
    win_mem[281] = 8'h00;
    win_mem[282] = 8'h00;
    win_mem[283] = 8'h00;
    win_mem[284] = 8'h00;
    win_mem[285] = 8'h00;
    win_mem[286] = 8'h00;
    win_mem[287] = 8'h00;
    win_mem[288] = 8'h00;
    win_mem[289] = 8'h00;
    win_mem[290] = 8'h00;
    win_mem[291] = 8'h00;
    win_mem[292] = 8'h00;
    win_mem[293] = 8'h00;
    win_mem[294] = 8'h00;
    win_mem[295] = 8'h00;
    win_mem[296] = 8'h00;
    win_mem[297] = 8'h00;
    win_mem[298] = 8'h00;
    win_mem[299] = 8'h00;
    win_mem[300] = 8'h00;
    win_mem[301] = 8'h00;
    win_mem[302] = 8'h00;
    win_mem[303] = 8'h00;
    win_mem[304] = 8'h00;
    win_mem[305] = 8'h00;
    win_mem[306] = 8'h00;
    win_mem[307] = 8'h00;
    win_mem[308] = 8'h00;
    win_mem[309] = 8'h00;
    win_mem[310] = 8'h00;
    win_mem[311] = 8'h00;
    win_mem[312] = 8'h00;
    win_mem[313] = 8'h00;
    win_mem[314] = 8'h00;
    win_mem[315] = 8'h00;
    win_mem[316] = 8'h00;
    win_mem[317] = 8'h00;
    win_mem[318] = 8'h00;
    win_mem[319] = 8'h00;
    win_mem[320] = 8'h00;
    win_mem[321] = 8'h00;
    win_mem[322] = 8'h00;
    win_mem[323] = 8'h00;
    win_mem[324] = 8'h00;
    win_mem[325] = 8'h00;
    win_mem[326] = 8'h00;
    win_mem[327] = 8'h00;
    win_mem[328] = 8'h00;
    win_mem[329] = 8'h00;
    win_mem[330] = 8'h00;
    win_mem[331] = 8'h00;
    win_mem[332] = 8'h00;
    win_mem[333] = 8'h00;
    win_mem[334] = 8'h00;
    win_mem[335] = 8'h00;
    win_mem[336] = 8'h00;
    win_mem[337] = 8'h00;
    win_mem[338] = 8'h00;
    win_mem[339] = 8'h00;
    win_mem[340] = 8'h00;
    win_mem[341] = 8'h00;
    win_mem[342] = 8'h00;
    win_mem[343] = 8'h00;
    win_mem[344] = 8'h00;
    win_mem[345] = 8'h00;
    win_mem[346] = 8'h00;
    win_mem[347] = 8'h00;
    win_mem[348] = 8'h00;
    win_mem[349] = 8'h00;
    win_mem[350] = 8'h00;
    win_mem[351] = 8'h00;
    win_mem[352] = 8'h00;
    win_mem[353] = 8'h00;
    win_mem[354] = 8'h00;
    win_mem[355] = 8'h00;
    win_mem[356] = 8'h00;
    win_mem[357] = 8'h00;
    win_mem[358] = 8'h00;
    win_mem[359] = 8'h00;
    win_mem[360] = 8'h00;
    win_mem[361] = 8'h00;
    win_mem[362] = 8'h00;
    win_mem[363] = 8'h00;
    win_mem[364] = 8'h00;
    win_mem[365] = 8'h00;
    win_mem[366] = 8'h00;
    win_mem[367] = 8'h00;
    win_mem[368] = 8'h00;
    win_mem[369] = 8'h00;
    win_mem[370] = 8'h00;
    win_mem[371] = 8'h00;
    win_mem[372] = 8'h00;
    win_mem[373] = 8'h00;
    win_mem[374] = 8'h00;
    win_mem[375] = 8'h00;
    win_mem[376] = 8'h00;
    win_mem[377] = 8'h00;
    win_mem[378] = 8'h00;
    win_mem[379] = 8'h00;
    win_mem[380] = 8'h00;
    win_mem[381] = 8'h00;
    win_mem[382] = 8'h00;
    win_mem[383] = 8'h00;
    win_mem[384] = 8'h00;
    win_mem[385] = 8'h00;
    win_mem[386] = 8'h00;
    win_mem[387] = 8'h00;
    win_mem[388] = 8'h00;
    win_mem[389] = 8'h00;
    win_mem[390] = 8'h00;
    win_mem[391] = 8'h00;
    win_mem[392] = 8'h00;
    win_mem[393] = 8'h00;
    win_mem[394] = 8'h00;
    win_mem[395] = 8'h00;
    win_mem[396] = 8'h00;
    win_mem[397] = 8'h00;
    win_mem[398] = 8'h00;
    win_mem[399] = 8'h00;
    win_mem[400] = 8'h00;
    win_mem[401] = 8'h00;
    win_mem[402] = 8'h00;
    win_mem[403] = 8'h00;
    win_mem[404] = 8'h00;
    win_mem[405] = 8'h00;
    win_mem[406] = 8'h00;
    win_mem[407] = 8'h00;
    win_mem[408] = 8'h00;
    win_mem[409] = 8'h00;
    win_mem[410] = 8'h00;
    win_mem[411] = 8'h00;
    win_mem[412] = 8'h00;
    win_mem[413] = 8'h00;
    win_mem[414] = 8'h00;
    win_mem[415] = 8'h00;
    win_mem[416] = 8'h00;
    win_mem[417] = 8'h00;
    win_mem[418] = 8'h00;
    win_mem[419] = 8'h00;
    win_mem[420] = 8'h00;
    win_mem[421] = 8'h00;
    win_mem[422] = 8'h00;
    win_mem[423] = 8'h00;
    win_mem[424] = 8'h00;
    win_mem[425] = 8'h00;
    win_mem[426] = 8'h00;
    win_mem[427] = 8'h00;
    win_mem[428] = 8'h00;
    win_mem[429] = 8'h00;
    win_mem[430] = 8'h00;
    win_mem[431] = 8'h00;
    win_mem[432] = 8'h00;
    win_mem[433] = 8'h00;
    win_mem[434] = 8'h00;
    win_mem[435] = 8'h00;
    win_mem[436] = 8'h00;
    win_mem[437] = 8'h00;
    win_mem[438] = 8'h00;
    win_mem[439] = 8'h00;
    win_mem[440] = 8'h00;
    win_mem[441] = 8'h00;
    win_mem[442] = 8'h00;
    win_mem[443] = 8'h00;
    win_mem[444] = 8'h00;
    win_mem[445] = 8'h00;
    win_mem[446] = 8'h00;
    win_mem[447] = 8'h00;
    win_mem[448] = 8'h00;
    win_mem[449] = 8'h00;
    win_mem[450] = 8'h00;
    win_mem[451] = 8'h00;
    win_mem[452] = 8'h00;
    win_mem[453] = 8'h00;
    win_mem[454] = 8'h00;
    win_mem[455] = 8'h00;
    win_mem[456] = 8'h00;
    win_mem[457] = 8'h00;
    win_mem[458] = 8'h00;
    win_mem[459] = 8'h00;
    win_mem[460] = 8'h00;
    win_mem[461] = 8'h00;
    win_mem[462] = 8'h00;
    win_mem[463] = 8'h00;
    win_mem[464] = 8'h00;
    win_mem[465] = 8'h00;
    win_mem[466] = 8'h00;
    win_mem[467] = 8'h00;
    win_mem[468] = 8'h00;
    win_mem[469] = 8'h00;
    win_mem[470] = 8'h00;
    win_mem[471] = 8'h00;
    win_mem[472] = 8'h00;
    win_mem[473] = 8'h00;
    win_mem[474] = 8'h00;
    win_mem[475] = 8'h00;
    win_mem[476] = 8'h00;
    win_mem[477] = 8'h00;
    win_mem[478] = 8'h00;
    win_mem[479] = 8'h00;
    win_mem[480] = 8'h00;
    win_mem[481] = 8'h00;
    win_mem[482] = 8'h00;
    win_mem[483] = 8'h00;
    win_mem[484] = 8'h00;
    win_mem[485] = 8'h00;
    win_mem[486] = 8'h00;
    win_mem[487] = 8'h00;
    win_mem[488] = 8'h00;
    win_mem[489] = 8'h00;
    win_mem[490] = 8'h00;
    win_mem[491] = 8'h00;
    win_mem[492] = 8'h00;
    win_mem[493] = 8'h00;
    win_mem[494] = 8'h00;
    win_mem[495] = 8'h00;
    win_mem[496] = 8'h00;
    win_mem[497] = 8'h00;
    win_mem[498] = 8'h00;
    win_mem[499] = 8'h00;
    win_mem[500] = 8'h00;
    win_mem[501] = 8'h00;
    win_mem[502] = 8'h00;
    win_mem[503] = 8'h00;
    win_mem[504] = 8'h00;
    win_mem[505] = 8'h00;
    win_mem[506] = 8'h00;
    win_mem[507] = 8'h00;
    win_mem[508] = 8'h00;
    win_mem[509] = 8'h00;
    win_mem[510] = 8'h00;
    win_mem[511] = 8'h00;
    win_mem[512] = 8'h00;
    win_mem[513] = 8'h00;
    win_mem[514] = 8'h00;
    win_mem[515] = 8'h00;
    win_mem[516] = 8'h00;
    win_mem[517] = 8'h00;
    win_mem[518] = 8'h00;
    win_mem[519] = 8'h00;
    win_mem[520] = 8'h00;
    win_mem[521] = 8'h00;
    win_mem[522] = 8'h00;
    win_mem[523] = 8'h00;
    win_mem[524] = 8'h00;
    win_mem[525] = 8'h00;
    win_mem[526] = 8'h00;
    win_mem[527] = 8'h00;
    win_mem[528] = 8'h00;
    win_mem[529] = 8'h00;
    win_mem[530] = 8'h00;
    win_mem[531] = 8'h00;
    win_mem[532] = 8'h00;
    win_mem[533] = 8'h00;
    win_mem[534] = 8'h00;
    win_mem[535] = 8'h00;
    win_mem[536] = 8'h00;
    win_mem[537] = 8'h00;
    win_mem[538] = 8'h00;
    win_mem[539] = 8'h00;
    win_mem[540] = 8'h00;
    win_mem[541] = 8'h00;
    win_mem[542] = 8'h00;
    win_mem[543] = 8'h00;
    win_mem[544] = 8'h00;
    win_mem[545] = 8'h00;
    win_mem[546] = 8'h00;
    win_mem[547] = 8'h00;
    win_mem[548] = 8'h00;
    win_mem[549] = 8'h00;
    win_mem[550] = 8'h00;
    win_mem[551] = 8'h00;
    win_mem[552] = 8'h00;
    win_mem[553] = 8'h00;
    win_mem[554] = 8'h00;
    win_mem[555] = 8'h00;
    win_mem[556] = 8'h00;
    win_mem[557] = 8'h00;
    win_mem[558] = 8'h00;
    win_mem[559] = 8'h00;
    win_mem[560] = 8'h00;
    win_mem[561] = 8'h00;
    win_mem[562] = 8'h00;
    win_mem[563] = 8'h00;
    win_mem[564] = 8'h00;
    win_mem[565] = 8'h00;
    win_mem[566] = 8'h00;
    win_mem[567] = 8'h00;
    win_mem[568] = 8'h00;
    win_mem[569] = 8'h00;
    win_mem[570] = 8'h00;
    win_mem[571] = 8'h00;
    win_mem[572] = 8'h00;
    win_mem[573] = 8'h00;
    win_mem[574] = 8'h00;
    win_mem[575] = 8'h00;
    win_mem[576] = 8'h00;
    win_mem[577] = 8'h00;
    win_mem[578] = 8'h00;
    win_mem[579] = 8'h00;
    win_mem[580] = 8'h00;
    win_mem[581] = 8'h00;
    win_mem[582] = 8'h00;
    win_mem[583] = 8'h00;
    win_mem[584] = 8'h00;
    win_mem[585] = 8'h00;
    win_mem[586] = 8'h00;
    win_mem[587] = 8'h00;
    win_mem[588] = 8'h00;
    win_mem[589] = 8'h00;
    win_mem[590] = 8'h00;
    win_mem[591] = 8'h00;
    win_mem[592] = 8'h00;
    win_mem[593] = 8'h00;
    win_mem[594] = 8'h00;
    win_mem[595] = 8'h00;
    win_mem[596] = 8'h00;
    win_mem[597] = 8'h00;
    win_mem[598] = 8'h00;
    win_mem[599] = 8'h00;
    win_mem[600] = 8'h00;
    win_mem[601] = 8'h00;
    win_mem[602] = 8'h00;
    win_mem[603] = 8'h00;
    win_mem[604] = 8'h00;
    win_mem[605] = 8'h00;
    win_mem[606] = 8'h00;
    win_mem[607] = 8'h00;
    win_mem[608] = 8'h00;
    win_mem[609] = 8'h00;
    win_mem[610] = 8'h00;
    win_mem[611] = 8'h00;
    win_mem[612] = 8'h00;
    win_mem[613] = 8'h00;
    win_mem[614] = 8'h00;
    win_mem[615] = 8'h00;
    win_mem[616] = 8'h00;
    win_mem[617] = 8'h00;
    win_mem[618] = 8'h00;
    win_mem[619] = 8'h00;
    win_mem[620] = 8'h00;
    win_mem[621] = 8'h00;
    win_mem[622] = 8'h00;
    win_mem[623] = 8'h00;
    win_mem[624] = 8'h00;
    win_mem[625] = 8'h00;
    win_mem[626] = 8'h00;
    win_mem[627] = 8'h00;
    win_mem[628] = 8'h00;
    win_mem[629] = 8'h00;
    win_mem[630] = 8'h00;
    win_mem[631] = 8'h00;
    win_mem[632] = 8'h00;
    win_mem[633] = 8'h00;
    win_mem[634] = 8'h00;
    win_mem[635] = 8'h00;
    win_mem[636] = 8'h00;
    win_mem[637] = 8'h00;
    win_mem[638] = 8'h00;
    win_mem[639] = 8'h00;
    win_mem[640] = 8'h00;
    win_mem[641] = 8'h00;
    win_mem[642] = 8'h00;
    win_mem[643] = 8'h00;
    win_mem[644] = 8'h00;
    win_mem[645] = 8'h00;
    win_mem[646] = 8'h00;
    win_mem[647] = 8'h00;
    win_mem[648] = 8'h00;
    win_mem[649] = 8'h00;
    win_mem[650] = 8'h00;
    win_mem[651] = 8'h00;
    win_mem[652] = 8'h00;
    win_mem[653] = 8'h00;
    win_mem[654] = 8'h00;
    win_mem[655] = 8'h00;
    win_mem[656] = 8'h00;
    win_mem[657] = 8'h00;
    win_mem[658] = 8'h00;
    win_mem[659] = 8'h00;
    win_mem[660] = 8'h00;
    win_mem[661] = 8'h00;
    win_mem[662] = 8'h00;
    win_mem[663] = 8'h00;
    win_mem[664] = 8'h00;
    win_mem[665] = 8'h00;
    win_mem[666] = 8'h00;
    win_mem[667] = 8'h00;
    win_mem[668] = 8'h00;
    win_mem[669] = 8'h00;
    win_mem[670] = 8'h00;
    win_mem[671] = 8'h00;
    win_mem[672] = 8'h00;
    win_mem[673] = 8'h00;
    win_mem[674] = 8'h00;
    win_mem[675] = 8'h00;
    win_mem[676] = 8'h00;
    win_mem[677] = 8'h00;
    win_mem[678] = 8'h00;
    win_mem[679] = 8'h00;
    win_mem[680] = 8'h00;
    win_mem[681] = 8'h00;
    win_mem[682] = 8'h00;
    win_mem[683] = 8'h00;
    win_mem[684] = 8'h00;
    win_mem[685] = 8'h00;
    win_mem[686] = 8'h00;
    win_mem[687] = 8'h00;
    win_mem[688] = 8'h00;
    win_mem[689] = 8'h00;
    win_mem[690] = 8'h00;
    win_mem[691] = 8'h00;
    win_mem[692] = 8'h00;
    win_mem[693] = 8'h00;
    win_mem[694] = 8'h00;
    win_mem[695] = 8'h00;
    win_mem[696] = 8'h00;
    win_mem[697] = 8'h00;
    win_mem[698] = 8'h00;
    win_mem[699] = 8'h00;
    win_mem[700] = 8'h00;
    win_mem[701] = 8'h00;
    win_mem[702] = 8'h00;
    win_mem[703] = 8'h00;
    win_mem[704] = 8'h00;
    win_mem[705] = 8'h00;
    win_mem[706] = 8'h00;
    win_mem[707] = 8'h00;
    win_mem[708] = 8'h00;
    win_mem[709] = 8'h00;
    win_mem[710] = 8'h00;
    win_mem[711] = 8'h00;
    win_mem[712] = 8'h00;
    win_mem[713] = 8'h00;
    win_mem[714] = 8'h00;
    win_mem[715] = 8'h00;
    win_mem[716] = 8'h00;
    win_mem[717] = 8'h00;
    win_mem[718] = 8'h00;
    win_mem[719] = 8'h00;
    win_mem[720] = 8'h00;
    win_mem[721] = 8'h00;
    win_mem[722] = 8'h00;
    win_mem[723] = 8'h00;
    win_mem[724] = 8'h00;
    win_mem[725] = 8'h00;
    win_mem[726] = 8'h00;
    win_mem[727] = 8'h00;
    win_mem[728] = 8'h00;
    win_mem[729] = 8'h00;
    win_mem[730] = 8'h00;
    win_mem[731] = 8'h00;
    win_mem[732] = 8'h00;
    win_mem[733] = 8'h00;
    win_mem[734] = 8'h00;
    win_mem[735] = 8'h00;
    win_mem[736] = 8'h00;
    win_mem[737] = 8'h00;
    win_mem[738] = 8'h00;
    win_mem[739] = 8'h00;
    win_mem[740] = 8'h00;
    win_mem[741] = 8'h00;
    win_mem[742] = 8'h00;
    win_mem[743] = 8'h00;
    win_mem[744] = 8'h00;
    win_mem[745] = 8'h00;
    win_mem[746] = 8'h00;
    win_mem[747] = 8'h00;
    win_mem[748] = 8'h00;
    win_mem[749] = 8'h00;
    win_mem[750] = 8'h00;
    win_mem[751] = 8'h00;
    win_mem[752] = 8'h00;
    win_mem[753] = 8'h00;
    win_mem[754] = 8'h00;
    win_mem[755] = 8'h00;
    win_mem[756] = 8'h00;
    win_mem[757] = 8'h00;
    win_mem[758] = 8'h00;
    win_mem[759] = 8'h00;
    win_mem[760] = 8'h00;
    win_mem[761] = 8'h00;
    win_mem[762] = 8'h00;
    win_mem[763] = 8'h00;
    win_mem[764] = 8'h00;
    win_mem[765] = 8'h00;
    win_mem[766] = 8'h00;
    win_mem[767] = 8'h00;
    win_mem[768] = 8'h00;
    win_mem[769] = 8'h00;
    win_mem[770] = 8'h00;
    win_mem[771] = 8'h00;
    win_mem[772] = 8'h00;
    win_mem[773] = 8'h00;
    win_mem[774] = 8'h00;
    win_mem[775] = 8'h00;
    win_mem[776] = 8'h00;
    win_mem[777] = 8'h00;
    win_mem[778] = 8'h00;
    win_mem[779] = 8'h00;
    win_mem[780] = 8'h00;
    win_mem[781] = 8'h00;
    win_mem[782] = 8'h00;
    win_mem[783] = 8'h00;
    win_mem[784] = 8'h00;
    win_mem[785] = 8'h00;
    win_mem[786] = 8'h00;
    win_mem[787] = 8'h00;
    win_mem[788] = 8'h00;
    win_mem[789] = 8'h00;
    win_mem[790] = 8'h00;
    win_mem[791] = 8'h00;
    win_mem[792] = 8'h00;
    win_mem[793] = 8'h00;
    win_mem[794] = 8'h00;
    win_mem[795] = 8'h00;
    win_mem[796] = 8'h00;
    win_mem[797] = 8'h00;
    win_mem[798] = 8'h00;
    win_mem[799] = 8'h00;
    win_mem[800] = 8'h00;
    win_mem[801] = 8'h00;
    win_mem[802] = 8'h00;
    win_mem[803] = 8'h00;
    win_mem[804] = 8'h00;
    win_mem[805] = 8'h00;
    win_mem[806] = 8'h00;
    win_mem[807] = 8'h00;
    win_mem[808] = 8'h00;
    win_mem[809] = 8'h00;
    win_mem[810] = 8'h00;
    win_mem[811] = 8'h00;
    win_mem[812] = 8'h00;
    win_mem[813] = 8'h00;
    win_mem[814] = 8'h00;
    win_mem[815] = 8'h00;
    win_mem[816] = 8'h00;
    win_mem[817] = 8'h00;
    win_mem[818] = 8'h00;
    win_mem[819] = 8'h00;
    win_mem[820] = 8'h00;
    win_mem[821] = 8'h00;
    win_mem[822] = 8'h00;
    win_mem[823] = 8'h00;
    win_mem[824] = 8'h00;
    win_mem[825] = 8'h00;
    win_mem[826] = 8'h00;
    win_mem[827] = 8'h00;
    win_mem[828] = 8'h00;
    win_mem[829] = 8'h00;
    win_mem[830] = 8'h00;
    win_mem[831] = 8'h00;
    win_mem[832] = 8'h00;
    win_mem[833] = 8'h00;
    win_mem[834] = 8'h00;
    win_mem[835] = 8'h00;
    win_mem[836] = 8'h00;
    win_mem[837] = 8'h00;
    win_mem[838] = 8'h00;
    win_mem[839] = 8'h00;
    win_mem[840] = 8'h00;
    win_mem[841] = 8'h00;
    win_mem[842] = 8'h00;
    win_mem[843] = 8'h00;
    win_mem[844] = 8'h00;
    win_mem[845] = 8'h00;
    win_mem[846] = 8'h00;
    win_mem[847] = 8'h00;
    win_mem[848] = 8'h00;
    win_mem[849] = 8'h00;
    win_mem[850] = 8'h00;
    win_mem[851] = 8'h00;
    win_mem[852] = 8'h00;
    win_mem[853] = 8'h00;
    win_mem[854] = 8'h00;
    win_mem[855] = 8'h00;
    win_mem[856] = 8'h00;
    win_mem[857] = 8'h00;
    win_mem[858] = 8'h00;
    win_mem[859] = 8'h00;
    win_mem[860] = 8'h00;
    win_mem[861] = 8'h00;
    win_mem[862] = 8'h00;
    win_mem[863] = 8'h00;
    win_mem[864] = 8'h00;
    win_mem[865] = 8'h00;
    win_mem[866] = 8'h00;
    win_mem[867] = 8'h00;
    win_mem[868] = 8'h00;
    win_mem[869] = 8'h00;
    win_mem[870] = 8'h00;
    win_mem[871] = 8'h00;
    win_mem[872] = 8'h00;
    win_mem[873] = 8'h00;
    win_mem[874] = 8'h00;
    win_mem[875] = 8'h00;
    win_mem[876] = 8'h00;
    win_mem[877] = 8'h00;
    win_mem[878] = 8'h00;
    win_mem[879] = 8'h00;
    win_mem[880] = 8'h00;
    win_mem[881] = 8'h00;
    win_mem[882] = 8'h00;
    win_mem[883] = 8'h00;
    win_mem[884] = 8'h00;
    win_mem[885] = 8'h00;
    win_mem[886] = 8'h00;
    win_mem[887] = 8'h00;
    win_mem[888] = 8'h00;
    win_mem[889] = 8'h00;
    win_mem[890] = 8'h00;
    win_mem[891] = 8'h00;
    win_mem[892] = 8'h00;
    win_mem[893] = 8'h00;
    win_mem[894] = 8'h00;
    win_mem[895] = 8'h00;
    win_mem[896] = 8'h00;
    win_mem[897] = 8'h00;
    win_mem[898] = 8'h00;
    win_mem[899] = 8'h00;
    win_mem[900] = 8'h00;
    win_mem[901] = 8'h00;
    win_mem[902] = 8'h00;
    win_mem[903] = 8'h00;
    win_mem[904] = 8'h00;
    win_mem[905] = 8'h00;
    win_mem[906] = 8'h00;
    win_mem[907] = 8'h00;
    win_mem[908] = 8'h00;
    win_mem[909] = 8'h00;
    win_mem[910] = 8'h00;
    win_mem[911] = 8'h00;
    win_mem[912] = 8'h00;
    win_mem[913] = 8'h00;
    win_mem[914] = 8'h00;
    win_mem[915] = 8'h00;
    win_mem[916] = 8'h00;
    win_mem[917] = 8'h00;
    win_mem[918] = 8'h00;
    win_mem[919] = 8'h00;
    win_mem[920] = 8'h00;
    win_mem[921] = 8'h00;
    win_mem[922] = 8'h00;
    win_mem[923] = 8'h00;
    win_mem[924] = 8'h00;
    win_mem[925] = 8'h00;
    win_mem[926] = 8'h00;
    win_mem[927] = 8'h00;
    win_mem[928] = 8'h00;
    win_mem[929] = 8'h00;
    win_mem[930] = 8'h00;
    win_mem[931] = 8'h00;
    win_mem[932] = 8'h00;
    win_mem[933] = 8'h00;
    win_mem[934] = 8'h00;
    win_mem[935] = 8'h00;
    win_mem[936] = 8'h00;
    win_mem[937] = 8'h00;
    win_mem[938] = 8'h00;
    win_mem[939] = 8'h00;
    win_mem[940] = 8'h00;
    win_mem[941] = 8'h00;
    win_mem[942] = 8'h00;
    win_mem[943] = 8'h00;
    win_mem[944] = 8'h00;
    win_mem[945] = 8'h00;
    win_mem[946] = 8'h00;
    win_mem[947] = 8'h00;
    win_mem[948] = 8'h00;
    win_mem[949] = 8'h00;
    win_mem[950] = 8'h00;
    win_mem[951] = 8'h00;
    win_mem[952] = 8'h00;
    win_mem[953] = 8'h00;
    win_mem[954] = 8'h00;
    win_mem[955] = 8'h00;
    win_mem[956] = 8'h00;
    win_mem[957] = 8'h00;
    win_mem[958] = 8'h00;
    win_mem[959] = 8'h00;
    win_mem[960] = 8'h00;
    win_mem[961] = 8'h00;
    win_mem[962] = 8'h00;
    win_mem[963] = 8'h00;
    win_mem[964] = 8'h00;
    win_mem[965] = 8'h00;
    win_mem[966] = 8'h00;
    win_mem[967] = 8'h00;
    win_mem[968] = 8'h00;
    win_mem[969] = 8'h00;
    win_mem[970] = 8'h00;
    win_mem[971] = 8'h00;
    win_mem[972] = 8'h00;
    win_mem[973] = 8'h00;
    win_mem[974] = 8'h00;
    win_mem[975] = 8'h00;
    win_mem[976] = 8'h00;
    win_mem[977] = 8'h00;
    win_mem[978] = 8'h00;
    win_mem[979] = 8'h00;
    win_mem[980] = 8'h00;
    win_mem[981] = 8'h00;
    win_mem[982] = 8'h00;
    win_mem[983] = 8'h00;
    win_mem[984] = 8'h00;
    win_mem[985] = 8'h00;
    win_mem[986] = 8'h00;
    win_mem[987] = 8'h00;
    win_mem[988] = 8'h00;
    win_mem[989] = 8'h00;
    win_mem[990] = 8'h00;
    win_mem[991] = 8'h00;
    win_mem[992] = 8'h00;
    win_mem[993] = 8'h00;
    win_mem[994] = 8'h00;
    win_mem[995] = 8'h00;
    win_mem[996] = 8'h00;
    win_mem[997] = 8'h00;
    win_mem[998] = 8'h00;
    win_mem[999] = 8'h00;
    win_mem[1000] = 8'h00;
    win_mem[1001] = 8'h00;
    win_mem[1002] = 8'h00;
    win_mem[1003] = 8'h00;
    win_mem[1004] = 8'h00;
    win_mem[1005] = 8'h00;
    win_mem[1006] = 8'h00;
    win_mem[1007] = 8'h00;
    win_mem[1008] = 8'h00;
    win_mem[1009] = 8'h00;
    win_mem[1010] = 8'h00;
    win_mem[1011] = 8'h00;
    win_mem[1012] = 8'h00;
    win_mem[1013] = 8'h00;
    win_mem[1014] = 8'h00;
    win_mem[1015] = 8'h00;
    win_mem[1016] = 8'h00;
    win_mem[1017] = 8'h00;
    win_mem[1018] = 8'h00;
    win_mem[1019] = 8'h00;
    win_mem[1020] = 8'h00;
    win_mem[1021] = 8'h00;
    win_mem[1022] = 8'h00;
    win_mem[1023] = 8'h00;
    win_mem[1024] = 8'h00;
    win_mem[1025] = 8'h00;
    win_mem[1026] = 8'h00;
    win_mem[1027] = 8'h00;
    win_mem[1028] = 8'h00;
    win_mem[1029] = 8'h00;
    win_mem[1030] = 8'h00;
    win_mem[1031] = 8'h00;
    win_mem[1032] = 8'h00;
    win_mem[1033] = 8'h00;
    win_mem[1034] = 8'h00;
    win_mem[1035] = 8'h00;
    win_mem[1036] = 8'h00;
    win_mem[1037] = 8'h00;
    win_mem[1038] = 8'h00;
    win_mem[1039] = 8'h00;
    win_mem[1040] = 8'h00;
    win_mem[1041] = 8'h00;
    win_mem[1042] = 8'h00;
    win_mem[1043] = 8'h00;
    win_mem[1044] = 8'h00;
    win_mem[1045] = 8'h00;
    win_mem[1046] = 8'h00;
    win_mem[1047] = 8'h00;
    win_mem[1048] = 8'h00;
    win_mem[1049] = 8'h00;
    win_mem[1050] = 8'h00;
    win_mem[1051] = 8'h00;
    win_mem[1052] = 8'h00;
    win_mem[1053] = 8'h00;
    win_mem[1054] = 8'h00;
    win_mem[1055] = 8'h00;
    win_mem[1056] = 8'h00;
    win_mem[1057] = 8'h00;
    win_mem[1058] = 8'h00;
    win_mem[1059] = 8'h00;
    win_mem[1060] = 8'h00;
    win_mem[1061] = 8'h00;
    win_mem[1062] = 8'h00;
    win_mem[1063] = 8'h00;
    win_mem[1064] = 8'h00;
    win_mem[1065] = 8'h00;
    win_mem[1066] = 8'h00;
    win_mem[1067] = 8'h00;
    win_mem[1068] = 8'h00;
    win_mem[1069] = 8'h00;
    win_mem[1070] = 8'h00;
    win_mem[1071] = 8'h00;
    win_mem[1072] = 8'h00;
    win_mem[1073] = 8'h00;
    win_mem[1074] = 8'h00;
    win_mem[1075] = 8'h00;
    win_mem[1076] = 8'h00;
    win_mem[1077] = 8'h00;
    win_mem[1078] = 8'h00;
    win_mem[1079] = 8'h00;
    win_mem[1080] = 8'h00;
    win_mem[1081] = 8'h00;
    win_mem[1082] = 8'h00;
    win_mem[1083] = 8'h00;
    win_mem[1084] = 8'h00;
    win_mem[1085] = 8'h00;
    win_mem[1086] = 8'h00;
    win_mem[1087] = 8'h00;
    win_mem[1088] = 8'h00;
    win_mem[1089] = 8'h00;
    win_mem[1090] = 8'h00;
    win_mem[1091] = 8'h00;
    win_mem[1092] = 8'h00;
    win_mem[1093] = 8'h00;
    win_mem[1094] = 8'h00;
    win_mem[1095] = 8'h00;
    win_mem[1096] = 8'h00;
    win_mem[1097] = 8'h00;
    win_mem[1098] = 8'h00;
    win_mem[1099] = 8'h00;
    win_mem[1100] = 8'h00;
    win_mem[1101] = 8'h00;
    win_mem[1102] = 8'h00;
    win_mem[1103] = 8'h00;
    win_mem[1104] = 8'h00;
    win_mem[1105] = 8'h00;
    win_mem[1106] = 8'h00;
    win_mem[1107] = 8'h00;
    win_mem[1108] = 8'h00;
    win_mem[1109] = 8'h00;
    win_mem[1110] = 8'h00;
    win_mem[1111] = 8'h00;
    win_mem[1112] = 8'h00;
    win_mem[1113] = 8'h00;
    win_mem[1114] = 8'h00;
    win_mem[1115] = 8'h00;
    win_mem[1116] = 8'h00;
    win_mem[1117] = 8'h00;
    win_mem[1118] = 8'h00;
    win_mem[1119] = 8'h00;
    win_mem[1120] = 8'h00;
    win_mem[1121] = 8'h00;
    win_mem[1122] = 8'h00;
    win_mem[1123] = 8'h00;
    win_mem[1124] = 8'h00;
    win_mem[1125] = 8'h00;
    win_mem[1126] = 8'h00;
    win_mem[1127] = 8'h00;
    win_mem[1128] = 8'h00;
    win_mem[1129] = 8'h00;
    win_mem[1130] = 8'h00;
    win_mem[1131] = 8'h00;
    win_mem[1132] = 8'h00;
    win_mem[1133] = 8'h00;
    win_mem[1134] = 8'h00;
    win_mem[1135] = 8'h00;
    win_mem[1136] = 8'h00;
    win_mem[1137] = 8'h00;
    win_mem[1138] = 8'h00;
    win_mem[1139] = 8'h00;
    win_mem[1140] = 8'h00;
    win_mem[1141] = 8'h00;
    win_mem[1142] = 8'h00;
    win_mem[1143] = 8'h00;
    win_mem[1144] = 8'h00;
    win_mem[1145] = 8'h00;
    win_mem[1146] = 8'h00;
    win_mem[1147] = 8'h00;
    win_mem[1148] = 8'h00;
    win_mem[1149] = 8'h00;
    win_mem[1150] = 8'h00;
    win_mem[1151] = 8'h00;
    win_mem[1152] = 8'h00;
    win_mem[1153] = 8'h00;
    win_mem[1154] = 8'h00;
    win_mem[1155] = 8'h00;
    win_mem[1156] = 8'h00;
    win_mem[1157] = 8'h00;
    win_mem[1158] = 8'h00;
    win_mem[1159] = 8'h00;
    win_mem[1160] = 8'h00;
    win_mem[1161] = 8'h00;
    win_mem[1162] = 8'h00;
    win_mem[1163] = 8'h00;
    win_mem[1164] = 8'h00;
    win_mem[1165] = 8'h00;
    win_mem[1166] = 8'h00;
    win_mem[1167] = 8'h00;
    win_mem[1168] = 8'h00;
    win_mem[1169] = 8'h00;
    win_mem[1170] = 8'h00;
    win_mem[1171] = 8'h00;
    win_mem[1172] = 8'h00;
    win_mem[1173] = 8'h00;
    win_mem[1174] = 8'h00;
    win_mem[1175] = 8'h00;
    win_mem[1176] = 8'h00;
    win_mem[1177] = 8'h00;
    win_mem[1178] = 8'h00;
    win_mem[1179] = 8'h00;
    win_mem[1180] = 8'h00;
    win_mem[1181] = 8'h00;
    win_mem[1182] = 8'h00;
    win_mem[1183] = 8'h00;
    win_mem[1184] = 8'h00;
    win_mem[1185] = 8'h00;
    win_mem[1186] = 8'h00;
    win_mem[1187] = 8'h00;
    win_mem[1188] = 8'h00;
    win_mem[1189] = 8'h00;
    win_mem[1190] = 8'h00;
    win_mem[1191] = 8'h00;
    win_mem[1192] = 8'h00;
    win_mem[1193] = 8'h00;
    win_mem[1194] = 8'h00;
    win_mem[1195] = 8'h00;
    win_mem[1196] = 8'h00;
    win_mem[1197] = 8'h00;
    win_mem[1198] = 8'h00;
    win_mem[1199] = 8'h00;
    win_mem[1200] = 8'h00;
    win_mem[1201] = 8'h00;
    win_mem[1202] = 8'h00;
    win_mem[1203] = 8'h00;
    win_mem[1204] = 8'h00;
    win_mem[1205] = 8'h00;
    win_mem[1206] = 8'h00;
    win_mem[1207] = 8'h00;
    win_mem[1208] = 8'h00;
    win_mem[1209] = 8'h00;
    win_mem[1210] = 8'h00;
    win_mem[1211] = 8'h00;
    win_mem[1212] = 8'h00;
    win_mem[1213] = 8'h00;
    win_mem[1214] = 8'h00;
    win_mem[1215] = 8'h00;
    win_mem[1216] = 8'h00;
    win_mem[1217] = 8'h00;
    win_mem[1218] = 8'h00;
    win_mem[1219] = 8'h00;
    win_mem[1220] = 8'h00;
    win_mem[1221] = 8'h00;
    win_mem[1222] = 8'h00;
    win_mem[1223] = 8'h00;
    win_mem[1224] = 8'h00;
    win_mem[1225] = 8'h00;
    win_mem[1226] = 8'h00;
    win_mem[1227] = 8'h00;
    win_mem[1228] = 8'h00;
    win_mem[1229] = 8'h00;
    win_mem[1230] = 8'h00;
    win_mem[1231] = 8'h00;
    win_mem[1232] = 8'h00;
    win_mem[1233] = 8'h00;
    win_mem[1234] = 8'h00;
    win_mem[1235] = 8'h00;
    win_mem[1236] = 8'h00;
    win_mem[1237] = 8'h00;
    win_mem[1238] = 8'h00;
    win_mem[1239] = 8'h00;
    win_mem[1240] = 8'h00;
    win_mem[1241] = 8'h00;
    win_mem[1242] = 8'h00;
    win_mem[1243] = 8'h00;
    win_mem[1244] = 8'h00;
    win_mem[1245] = 8'h00;
    win_mem[1246] = 8'h00;
    win_mem[1247] = 8'h00;
    win_mem[1248] = 8'h00;
    win_mem[1249] = 8'h00;
    win_mem[1250] = 8'h00;
    win_mem[1251] = 8'h00;
    win_mem[1252] = 8'h00;
    win_mem[1253] = 8'h00;
    win_mem[1254] = 8'h00;
    win_mem[1255] = 8'h00;
    win_mem[1256] = 8'h00;
    win_mem[1257] = 8'h00;
    win_mem[1258] = 8'h00;
    win_mem[1259] = 8'h00;
    win_mem[1260] = 8'h00;
    win_mem[1261] = 8'h00;
    win_mem[1262] = 8'h00;
    win_mem[1263] = 8'h00;
    win_mem[1264] = 8'h00;
    win_mem[1265] = 8'h00;
    win_mem[1266] = 8'h00;
    win_mem[1267] = 8'h00;
    win_mem[1268] = 8'h00;
    win_mem[1269] = 8'h00;
    win_mem[1270] = 8'h00;
    win_mem[1271] = 8'h00;
    win_mem[1272] = 8'h00;
    win_mem[1273] = 8'h00;
    win_mem[1274] = 8'h00;
    win_mem[1275] = 8'h00;
    win_mem[1276] = 8'h00;
    win_mem[1277] = 8'h00;
    win_mem[1278] = 8'h00;
    win_mem[1279] = 8'h00;
    win_mem[1280] = 8'h00;
    win_mem[1281] = 8'h00;
    win_mem[1282] = 8'h00;
    win_mem[1283] = 8'h00;
    win_mem[1284] = 8'h00;
    win_mem[1285] = 8'h00;
    win_mem[1286] = 8'h00;
    win_mem[1287] = 8'h00;
    win_mem[1288] = 8'h00;
    win_mem[1289] = 8'h00;
    win_mem[1290] = 8'h00;
    win_mem[1291] = 8'h00;
    win_mem[1292] = 8'h00;
    win_mem[1293] = 8'h00;
    win_mem[1294] = 8'h00;
    win_mem[1295] = 8'h00;
    win_mem[1296] = 8'h00;
    win_mem[1297] = 8'h00;
    win_mem[1298] = 8'h00;
    win_mem[1299] = 8'h00;
    win_mem[1300] = 8'h00;
    win_mem[1301] = 8'h00;
    win_mem[1302] = 8'h00;
    win_mem[1303] = 8'h00;
    win_mem[1304] = 8'h00;
    win_mem[1305] = 8'h00;
    win_mem[1306] = 8'h00;
    win_mem[1307] = 8'h00;
    win_mem[1308] = 8'h00;
    win_mem[1309] = 8'h00;
    win_mem[1310] = 8'h00;
    win_mem[1311] = 8'h00;
    win_mem[1312] = 8'h00;
    win_mem[1313] = 8'h00;
    win_mem[1314] = 8'h00;
    win_mem[1315] = 8'h00;
    win_mem[1316] = 8'h00;
    win_mem[1317] = 8'h00;
    win_mem[1318] = 8'h00;
    win_mem[1319] = 8'h00;
    win_mem[1320] = 8'h00;
    win_mem[1321] = 8'h00;
    win_mem[1322] = 8'h00;
    win_mem[1323] = 8'h00;
    win_mem[1324] = 8'h00;
    win_mem[1325] = 8'h00;
    win_mem[1326] = 8'h00;
    win_mem[1327] = 8'h00;
    win_mem[1328] = 8'h00;
    win_mem[1329] = 8'h00;
    win_mem[1330] = 8'h00;
    win_mem[1331] = 8'h00;
    win_mem[1332] = 8'h00;
    win_mem[1333] = 8'h00;
    win_mem[1334] = 8'h00;
    win_mem[1335] = 8'h00;
    win_mem[1336] = 8'h00;
    win_mem[1337] = 8'h00;
    win_mem[1338] = 8'h00;
    win_mem[1339] = 8'h00;
    win_mem[1340] = 8'h00;
    win_mem[1341] = 8'h00;
    win_mem[1342] = 8'h00;
    win_mem[1343] = 8'h00;
    win_mem[1344] = 8'h00;
    win_mem[1345] = 8'h00;
    win_mem[1346] = 8'h00;
    win_mem[1347] = 8'h00;
    win_mem[1348] = 8'h00;
    win_mem[1349] = 8'h00;
    win_mem[1350] = 8'h00;
    win_mem[1351] = 8'h00;
    win_mem[1352] = 8'h00;
    win_mem[1353] = 8'h00;
    win_mem[1354] = 8'h00;
    win_mem[1355] = 8'h00;
    win_mem[1356] = 8'h00;
    win_mem[1357] = 8'h00;
    win_mem[1358] = 8'h00;
    win_mem[1359] = 8'h00;
    win_mem[1360] = 8'h00;
    win_mem[1361] = 8'h00;
    win_mem[1362] = 8'h00;
    win_mem[1363] = 8'h00;
    win_mem[1364] = 8'h00;
    win_mem[1365] = 8'h00;
    win_mem[1366] = 8'h00;
    win_mem[1367] = 8'h00;
    win_mem[1368] = 8'h00;
    win_mem[1369] = 8'h00;
    win_mem[1370] = 8'h00;
    win_mem[1371] = 8'h00;
    win_mem[1372] = 8'h00;
    win_mem[1373] = 8'h00;
    win_mem[1374] = 8'h00;
    win_mem[1375] = 8'h00;
    win_mem[1376] = 8'h00;
    win_mem[1377] = 8'h00;
    win_mem[1378] = 8'h00;
    win_mem[1379] = 8'h00;
    win_mem[1380] = 8'h00;
    win_mem[1381] = 8'h00;
    win_mem[1382] = 8'h00;
    win_mem[1383] = 8'h00;
    win_mem[1384] = 8'h00;
    win_mem[1385] = 8'h00;
    win_mem[1386] = 8'h00;
    win_mem[1387] = 8'h00;
    win_mem[1388] = 8'h00;
    win_mem[1389] = 8'h00;
    win_mem[1390] = 8'h00;
    win_mem[1391] = 8'h00;
    win_mem[1392] = 8'h00;
    win_mem[1393] = 8'h00;
    win_mem[1394] = 8'h00;
    win_mem[1395] = 8'h00;
    win_mem[1396] = 8'h00;
    win_mem[1397] = 8'h00;
    win_mem[1398] = 8'h00;
    win_mem[1399] = 8'h00;
    win_mem[1400] = 8'h00;
    win_mem[1401] = 8'h00;
    win_mem[1402] = 8'h00;
    win_mem[1403] = 8'h00;
    win_mem[1404] = 8'h00;
    win_mem[1405] = 8'h00;
    win_mem[1406] = 8'h00;
    win_mem[1407] = 8'h00;
    win_mem[1408] = 8'h00;
    win_mem[1409] = 8'h00;
    win_mem[1410] = 8'h00;
    win_mem[1411] = 8'h00;
    win_mem[1412] = 8'h00;
    win_mem[1413] = 8'h00;
    win_mem[1414] = 8'h00;
    win_mem[1415] = 8'h00;
    win_mem[1416] = 8'h00;
    win_mem[1417] = 8'h00;
    win_mem[1418] = 8'h00;
    win_mem[1419] = 8'h00;
    win_mem[1420] = 8'h00;
    win_mem[1421] = 8'h00;
    win_mem[1422] = 8'h00;
    win_mem[1423] = 8'h00;
    win_mem[1424] = 8'h00;
    win_mem[1425] = 8'h00;
    win_mem[1426] = 8'h00;
    win_mem[1427] = 8'h00;
    win_mem[1428] = 8'h00;
    win_mem[1429] = 8'h00;
    win_mem[1430] = 8'h00;
    win_mem[1431] = 8'h00;
    win_mem[1432] = 8'h00;
    win_mem[1433] = 8'h00;
    win_mem[1434] = 8'h00;
    win_mem[1435] = 8'h00;
    win_mem[1436] = 8'h00;
    win_mem[1437] = 8'h00;
    win_mem[1438] = 8'h00;
    win_mem[1439] = 8'h00;
    win_mem[1440] = 8'h00;
    win_mem[1441] = 8'h00;
    win_mem[1442] = 8'h00;
    win_mem[1443] = 8'h00;
    win_mem[1444] = 8'h00;
    win_mem[1445] = 8'h00;
    win_mem[1446] = 8'h00;
    win_mem[1447] = 8'h00;
    win_mem[1448] = 8'h00;
    win_mem[1449] = 8'h00;
    win_mem[1450] = 8'h00;
    win_mem[1451] = 8'h00;
    win_mem[1452] = 8'h00;
    win_mem[1453] = 8'h00;
    win_mem[1454] = 8'h00;
    win_mem[1455] = 8'h00;
    win_mem[1456] = 8'h00;
    win_mem[1457] = 8'h00;
    win_mem[1458] = 8'h00;
    win_mem[1459] = 8'h00;
    win_mem[1460] = 8'h00;
    win_mem[1461] = 8'h00;
    win_mem[1462] = 8'h00;
    win_mem[1463] = 8'h00;
    win_mem[1464] = 8'h00;
    win_mem[1465] = 8'h00;
    win_mem[1466] = 8'h00;
    win_mem[1467] = 8'h00;
    win_mem[1468] = 8'h00;
    win_mem[1469] = 8'h00;
    win_mem[1470] = 8'h00;
    win_mem[1471] = 8'h00;
    win_mem[1472] = 8'h00;
    win_mem[1473] = 8'h00;
    win_mem[1474] = 8'h00;
    win_mem[1475] = 8'h00;
    win_mem[1476] = 8'h00;
    win_mem[1477] = 8'h00;
    win_mem[1478] = 8'h00;
    win_mem[1479] = 8'h00;
    win_mem[1480] = 8'h00;
    win_mem[1481] = 8'h00;
    win_mem[1482] = 8'h00;
    win_mem[1483] = 8'h00;
    win_mem[1484] = 8'h00;
    win_mem[1485] = 8'h00;
    win_mem[1486] = 8'h00;
    win_mem[1487] = 8'h00;
    win_mem[1488] = 8'h00;
    win_mem[1489] = 8'h00;
    win_mem[1490] = 8'h00;
    win_mem[1491] = 8'h00;
    win_mem[1492] = 8'h00;
    win_mem[1493] = 8'h00;
    win_mem[1494] = 8'h00;
    win_mem[1495] = 8'h00;
    win_mem[1496] = 8'h00;
    win_mem[1497] = 8'h00;
    win_mem[1498] = 8'h00;
    win_mem[1499] = 8'h00;
    win_mem[1500] = 8'h00;
    win_mem[1501] = 8'h00;
    win_mem[1502] = 8'h00;
    win_mem[1503] = 8'h00;
    win_mem[1504] = 8'h00;
    win_mem[1505] = 8'h00;
    win_mem[1506] = 8'h00;
    win_mem[1507] = 8'h00;
    win_mem[1508] = 8'h00;
    win_mem[1509] = 8'h00;
    win_mem[1510] = 8'h00;
    win_mem[1511] = 8'h00;
    win_mem[1512] = 8'h00;
    win_mem[1513] = 8'h00;
    win_mem[1514] = 8'h00;
    win_mem[1515] = 8'h00;
    win_mem[1516] = 8'h00;
    win_mem[1517] = 8'h00;
    win_mem[1518] = 8'h00;
    win_mem[1519] = 8'h00;
    win_mem[1520] = 8'h00;
    win_mem[1521] = 8'h00;
    win_mem[1522] = 8'h00;
    win_mem[1523] = 8'h00;
    win_mem[1524] = 8'h00;
    win_mem[1525] = 8'h00;
    win_mem[1526] = 8'h00;
    win_mem[1527] = 8'h00;
    win_mem[1528] = 8'h00;
    win_mem[1529] = 8'h00;
    win_mem[1530] = 8'h00;
    win_mem[1531] = 8'h00;
    win_mem[1532] = 8'h00;
    win_mem[1533] = 8'h00;
    win_mem[1534] = 8'h00;
    win_mem[1535] = 8'h00;
    win_mem[1536] = 8'h00;
    win_mem[1537] = 8'h00;
    win_mem[1538] = 8'h00;
    win_mem[1539] = 8'h00;
    win_mem[1540] = 8'h00;
    win_mem[1541] = 8'h00;
    win_mem[1542] = 8'h00;
    win_mem[1543] = 8'h00;
    win_mem[1544] = 8'h00;
    win_mem[1545] = 8'h00;
    win_mem[1546] = 8'h00;
    win_mem[1547] = 8'h00;
    win_mem[1548] = 8'h00;
    win_mem[1549] = 8'h00;
    win_mem[1550] = 8'h00;
    win_mem[1551] = 8'h00;
    win_mem[1552] = 8'h00;
    win_mem[1553] = 8'h00;
    win_mem[1554] = 8'h00;
    win_mem[1555] = 8'h00;
    win_mem[1556] = 8'h00;
    win_mem[1557] = 8'h00;
    win_mem[1558] = 8'h00;
    win_mem[1559] = 8'h00;
    win_mem[1560] = 8'h00;
    win_mem[1561] = 8'h00;
    win_mem[1562] = 8'h00;
    win_mem[1563] = 8'h00;
    win_mem[1564] = 8'h00;
    win_mem[1565] = 8'h00;
    win_mem[1566] = 8'h00;
    win_mem[1567] = 8'h00;
    win_mem[1568] = 8'h00;
    win_mem[1569] = 8'h00;
    win_mem[1570] = 8'h00;
    win_mem[1571] = 8'h00;
    win_mem[1572] = 8'h00;
    win_mem[1573] = 8'h00;
    win_mem[1574] = 8'h00;
    win_mem[1575] = 8'h00;
    win_mem[1576] = 8'h00;
    win_mem[1577] = 8'h00;
    win_mem[1578] = 8'h00;
    win_mem[1579] = 8'h00;
    win_mem[1580] = 8'h00;
    win_mem[1581] = 8'h00;
    win_mem[1582] = 8'h00;
    win_mem[1583] = 8'h00;
    win_mem[1584] = 8'h00;
    win_mem[1585] = 8'h00;
    win_mem[1586] = 8'h00;
    win_mem[1587] = 8'h00;
    win_mem[1588] = 8'h00;
    win_mem[1589] = 8'h00;
    win_mem[1590] = 8'h00;
    win_mem[1591] = 8'h00;
    win_mem[1592] = 8'h00;
    win_mem[1593] = 8'h00;
    win_mem[1594] = 8'h00;
    win_mem[1595] = 8'h00;
    win_mem[1596] = 8'h00;
    win_mem[1597] = 8'h00;
    win_mem[1598] = 8'h00;
    win_mem[1599] = 8'h00;
    win_mem[1600] = 8'h00;
    win_mem[1601] = 8'h00;
    win_mem[1602] = 8'h00;
    win_mem[1603] = 8'h00;
    win_mem[1604] = 8'h00;
    win_mem[1605] = 8'h00;
    win_mem[1606] = 8'h00;
    win_mem[1607] = 8'h00;
    win_mem[1608] = 8'h00;
    win_mem[1609] = 8'h00;
    win_mem[1610] = 8'h00;
    win_mem[1611] = 8'h00;
    win_mem[1612] = 8'h00;
    win_mem[1613] = 8'h00;
    win_mem[1614] = 8'h00;
    win_mem[1615] = 8'h00;
    win_mem[1616] = 8'h00;
    win_mem[1617] = 8'h00;
    win_mem[1618] = 8'h00;
    win_mem[1619] = 8'h00;
    win_mem[1620] = 8'h00;
    win_mem[1621] = 8'h00;
    win_mem[1622] = 8'h00;
    win_mem[1623] = 8'h00;
    win_mem[1624] = 8'h00;
    win_mem[1625] = 8'h00;
    win_mem[1626] = 8'h00;
    win_mem[1627] = 8'h00;
    win_mem[1628] = 8'h00;
    win_mem[1629] = 8'h00;
    win_mem[1630] = 8'h00;
    win_mem[1631] = 8'h00;
    win_mem[1632] = 8'h00;
    win_mem[1633] = 8'h00;
    win_mem[1634] = 8'h00;
    win_mem[1635] = 8'h00;
    win_mem[1636] = 8'h00;
    win_mem[1637] = 8'h00;
    win_mem[1638] = 8'h00;
    win_mem[1639] = 8'h00;
    win_mem[1640] = 8'h00;
    win_mem[1641] = 8'h00;
    win_mem[1642] = 8'h00;
    win_mem[1643] = 8'h00;
    win_mem[1644] = 8'h00;
    win_mem[1645] = 8'h00;
    win_mem[1646] = 8'h00;
    win_mem[1647] = 8'h00;
    win_mem[1648] = 8'h00;
    win_mem[1649] = 8'h00;
    win_mem[1650] = 8'h00;
    win_mem[1651] = 8'h00;
    win_mem[1652] = 8'h00;
    win_mem[1653] = 8'h00;
    win_mem[1654] = 8'h00;
    win_mem[1655] = 8'h00;
    win_mem[1656] = 8'h00;
    win_mem[1657] = 8'h00;
    win_mem[1658] = 8'h00;
    win_mem[1659] = 8'h00;
    win_mem[1660] = 8'h00;
    win_mem[1661] = 8'h00;
    win_mem[1662] = 8'h00;
    win_mem[1663] = 8'h00;
    win_mem[1664] = 8'h00;
    win_mem[1665] = 8'h00;
    win_mem[1666] = 8'h00;
    win_mem[1667] = 8'h00;
    win_mem[1668] = 8'h00;
    win_mem[1669] = 8'h00;
    win_mem[1670] = 8'h00;
    win_mem[1671] = 8'h00;
    win_mem[1672] = 8'h00;
    win_mem[1673] = 8'h00;
    win_mem[1674] = 8'h00;
    win_mem[1675] = 8'h00;
    win_mem[1676] = 8'h00;
    win_mem[1677] = 8'h00;
    win_mem[1678] = 8'h00;
    win_mem[1679] = 8'h00;
    win_mem[1680] = 8'h00;
    win_mem[1681] = 8'h00;
    win_mem[1682] = 8'h00;
    win_mem[1683] = 8'h00;
    win_mem[1684] = 8'h00;
    win_mem[1685] = 8'h00;
    win_mem[1686] = 8'h00;
    win_mem[1687] = 8'h00;
    win_mem[1688] = 8'h00;
    win_mem[1689] = 8'h00;
    win_mem[1690] = 8'h00;
    win_mem[1691] = 8'h00;
    win_mem[1692] = 8'h00;
    win_mem[1693] = 8'h00;
    win_mem[1694] = 8'h00;
    win_mem[1695] = 8'h00;
    win_mem[1696] = 8'h00;
    win_mem[1697] = 8'h00;
    win_mem[1698] = 8'h00;
    win_mem[1699] = 8'h00;
    win_mem[1700] = 8'h00;
    win_mem[1701] = 8'h00;
    win_mem[1702] = 8'h00;
    win_mem[1703] = 8'h00;
    win_mem[1704] = 8'h00;
    win_mem[1705] = 8'h00;
    win_mem[1706] = 8'h00;
    win_mem[1707] = 8'h00;
    win_mem[1708] = 8'h00;
    win_mem[1709] = 8'h00;
    win_mem[1710] = 8'h00;
    win_mem[1711] = 8'h00;
    win_mem[1712] = 8'h00;
    win_mem[1713] = 8'h00;
    win_mem[1714] = 8'h00;
    win_mem[1715] = 8'h00;
    win_mem[1716] = 8'h00;
    win_mem[1717] = 8'h00;
    win_mem[1718] = 8'h00;
    win_mem[1719] = 8'h00;
    win_mem[1720] = 8'h00;
    win_mem[1721] = 8'h00;
    win_mem[1722] = 8'h00;
    win_mem[1723] = 8'h00;
    win_mem[1724] = 8'h00;
    win_mem[1725] = 8'h00;
    win_mem[1726] = 8'h00;
    win_mem[1727] = 8'h00;
    win_mem[1728] = 8'h00;
    win_mem[1729] = 8'h00;
    win_mem[1730] = 8'h00;
    win_mem[1731] = 8'h00;
    win_mem[1732] = 8'h00;
    win_mem[1733] = 8'h00;
    win_mem[1734] = 8'h00;
    win_mem[1735] = 8'h00;
    win_mem[1736] = 8'h00;
    win_mem[1737] = 8'h00;
    win_mem[1738] = 8'h00;
    win_mem[1739] = 8'h00;
    win_mem[1740] = 8'h00;
    win_mem[1741] = 8'h00;
    win_mem[1742] = 8'h00;
    win_mem[1743] = 8'h00;
    win_mem[1744] = 8'h00;
    win_mem[1745] = 8'h00;
    win_mem[1746] = 8'h00;
    win_mem[1747] = 8'h00;
    win_mem[1748] = 8'h00;
    win_mem[1749] = 8'h00;
    win_mem[1750] = 8'h00;
    win_mem[1751] = 8'h00;
    win_mem[1752] = 8'h00;
    win_mem[1753] = 8'h00;
    win_mem[1754] = 8'h00;
    win_mem[1755] = 8'h00;
    win_mem[1756] = 8'h00;
    win_mem[1757] = 8'h00;
    win_mem[1758] = 8'h00;
    win_mem[1759] = 8'h00;
    win_mem[1760] = 8'h00;
    win_mem[1761] = 8'h00;
    win_mem[1762] = 8'h00;
    win_mem[1763] = 8'h00;
    win_mem[1764] = 8'h00;
    win_mem[1765] = 8'h00;
    win_mem[1766] = 8'h00;
    win_mem[1767] = 8'h00;
    win_mem[1768] = 8'h00;
    win_mem[1769] = 8'h00;
    win_mem[1770] = 8'h00;
    win_mem[1771] = 8'h00;
    win_mem[1772] = 8'h00;
    win_mem[1773] = 8'h00;
    win_mem[1774] = 8'h00;
    win_mem[1775] = 8'h00;
    win_mem[1776] = 8'h00;
    win_mem[1777] = 8'h00;
    win_mem[1778] = 8'h00;
    win_mem[1779] = 8'h00;
    win_mem[1780] = 8'h00;
    win_mem[1781] = 8'h00;
    win_mem[1782] = 8'h00;
    win_mem[1783] = 8'h00;
    win_mem[1784] = 8'h00;
    win_mem[1785] = 8'h00;
    win_mem[1786] = 8'h00;
    win_mem[1787] = 8'h00;
    win_mem[1788] = 8'h00;
    win_mem[1789] = 8'h00;
    win_mem[1790] = 8'h00;
    win_mem[1791] = 8'h00;
    win_mem[1792] = 8'h00;
    win_mem[1793] = 8'h00;
    win_mem[1794] = 8'h00;
    win_mem[1795] = 8'h00;
    win_mem[1796] = 8'h00;
    win_mem[1797] = 8'h00;
    win_mem[1798] = 8'h00;
    win_mem[1799] = 8'h00;
    win_mem[1800] = 8'h00;
    win_mem[1801] = 8'h00;
    win_mem[1802] = 8'h00;
    win_mem[1803] = 8'h00;
    win_mem[1804] = 8'h00;
    win_mem[1805] = 8'h00;
    win_mem[1806] = 8'h00;
    win_mem[1807] = 8'h00;
    win_mem[1808] = 8'h00;
    win_mem[1809] = 8'h00;
    win_mem[1810] = 8'h00;
    win_mem[1811] = 8'h00;
    win_mem[1812] = 8'h00;
    win_mem[1813] = 8'h00;
    win_mem[1814] = 8'h00;
    win_mem[1815] = 8'h00;
    win_mem[1816] = 8'h00;
    win_mem[1817] = 8'h00;
    win_mem[1818] = 8'h00;
    win_mem[1819] = 8'h00;
    win_mem[1820] = 8'h00;
    win_mem[1821] = 8'h00;
    win_mem[1822] = 8'h00;
    win_mem[1823] = 8'h00;
    win_mem[1824] = 8'h00;
    win_mem[1825] = 8'h00;
    win_mem[1826] = 8'h00;
    win_mem[1827] = 8'h00;
    win_mem[1828] = 8'h00;
    win_mem[1829] = 8'h00;
    win_mem[1830] = 8'h00;
    win_mem[1831] = 8'h00;
    win_mem[1832] = 8'h00;
    win_mem[1833] = 8'h00;
    win_mem[1834] = 8'h00;
    win_mem[1835] = 8'h00;
    win_mem[1836] = 8'h00;
    win_mem[1837] = 8'h00;
    win_mem[1838] = 8'h00;
    win_mem[1839] = 8'h00;
    win_mem[1840] = 8'h00;
    win_mem[1841] = 8'h00;
    win_mem[1842] = 8'h00;
    win_mem[1843] = 8'h00;
    win_mem[1844] = 8'h00;
    win_mem[1845] = 8'h00;
    win_mem[1846] = 8'h00;
    win_mem[1847] = 8'h00;
    win_mem[1848] = 8'h00;
    win_mem[1849] = 8'h00;
    win_mem[1850] = 8'h00;
    win_mem[1851] = 8'h00;
    win_mem[1852] = 8'h00;
    win_mem[1853] = 8'h00;
    win_mem[1854] = 8'h00;
    win_mem[1855] = 8'h00;
    win_mem[1856] = 8'h00;
    win_mem[1857] = 8'h00;
    win_mem[1858] = 8'h00;
    win_mem[1859] = 8'h00;
    win_mem[1860] = 8'h00;
    win_mem[1861] = 8'h00;
    win_mem[1862] = 8'h00;
    win_mem[1863] = 8'h00;
    win_mem[1864] = 8'h00;
    win_mem[1865] = 8'h00;
    win_mem[1866] = 8'h00;
    win_mem[1867] = 8'h00;
    win_mem[1868] = 8'h00;
    win_mem[1869] = 8'h00;
    win_mem[1870] = 8'h00;
    win_mem[1871] = 8'h00;
    win_mem[1872] = 8'h00;
    win_mem[1873] = 8'h00;
    win_mem[1874] = 8'h00;
    win_mem[1875] = 8'h00;
    win_mem[1876] = 8'h00;
    win_mem[1877] = 8'h00;
    win_mem[1878] = 8'h00;
    win_mem[1879] = 8'h00;
    win_mem[1880] = 8'h00;
    win_mem[1881] = 8'h00;
    win_mem[1882] = 8'h00;
    win_mem[1883] = 8'h00;
    win_mem[1884] = 8'h00;
    win_mem[1885] = 8'h00;
    win_mem[1886] = 8'h00;
    win_mem[1887] = 8'h00;
    win_mem[1888] = 8'h00;
    win_mem[1889] = 8'h00;
    win_mem[1890] = 8'h00;
    win_mem[1891] = 8'h00;
    win_mem[1892] = 8'h00;
    win_mem[1893] = 8'h00;
    win_mem[1894] = 8'h00;
    win_mem[1895] = 8'h00;
    win_mem[1896] = 8'h00;
    win_mem[1897] = 8'h00;
    win_mem[1898] = 8'h00;
    win_mem[1899] = 8'h00;
    win_mem[1900] = 8'h00;
    win_mem[1901] = 8'h00;
    win_mem[1902] = 8'h00;
    win_mem[1903] = 8'h00;
    win_mem[1904] = 8'h00;
    win_mem[1905] = 8'h00;
    win_mem[1906] = 8'h00;
    win_mem[1907] = 8'h00;
    win_mem[1908] = 8'h00;
    win_mem[1909] = 8'h00;
    win_mem[1910] = 8'h00;
    win_mem[1911] = 8'h00;
    win_mem[1912] = 8'h00;
    win_mem[1913] = 8'h00;
    win_mem[1914] = 8'h00;
    win_mem[1915] = 8'h00;
    win_mem[1916] = 8'h00;
    win_mem[1917] = 8'h00;
    win_mem[1918] = 8'h00;
    win_mem[1919] = 8'h00;
    win_mem[1920] = 8'h00;
    win_mem[1921] = 8'h00;
    win_mem[1922] = 8'h00;
    win_mem[1923] = 8'h00;
    win_mem[1924] = 8'h00;
    win_mem[1925] = 8'h00;
    win_mem[1926] = 8'h00;
    win_mem[1927] = 8'h00;
    win_mem[1928] = 8'h00;
    win_mem[1929] = 8'h00;
    win_mem[1930] = 8'h00;
    win_mem[1931] = 8'h00;
    win_mem[1932] = 8'h00;
    win_mem[1933] = 8'h00;
    win_mem[1934] = 8'h00;
    win_mem[1935] = 8'h00;
    win_mem[1936] = 8'h00;
    win_mem[1937] = 8'h00;
    win_mem[1938] = 8'h00;
    win_mem[1939] = 8'h00;
    win_mem[1940] = 8'h00;
    win_mem[1941] = 8'h00;
    win_mem[1942] = 8'h00;
    win_mem[1943] = 8'h00;
    win_mem[1944] = 8'h00;
    win_mem[1945] = 8'h00;
    win_mem[1946] = 8'h00;
    win_mem[1947] = 8'h00;
    win_mem[1948] = 8'h00;
    win_mem[1949] = 8'h00;
    win_mem[1950] = 8'h00;
    win_mem[1951] = 8'h00;
    win_mem[1952] = 8'h00;
    win_mem[1953] = 8'h00;
    win_mem[1954] = 8'h00;
    win_mem[1955] = 8'h00;
    win_mem[1956] = 8'h00;
    win_mem[1957] = 8'h00;
    win_mem[1958] = 8'h00;
    win_mem[1959] = 8'h00;
    win_mem[1960] = 8'h00;
    win_mem[1961] = 8'h00;
    win_mem[1962] = 8'h00;
    win_mem[1963] = 8'h00;
    win_mem[1964] = 8'h00;
    win_mem[1965] = 8'h00;
    win_mem[1966] = 8'h00;
    win_mem[1967] = 8'h00;
    win_mem[1968] = 8'h00;
    win_mem[1969] = 8'h00;
    win_mem[1970] = 8'h00;
    win_mem[1971] = 8'h00;
    win_mem[1972] = 8'h00;
    win_mem[1973] = 8'h00;
    win_mem[1974] = 8'h00;
    win_mem[1975] = 8'h00;
    win_mem[1976] = 8'h00;
    win_mem[1977] = 8'h00;
    win_mem[1978] = 8'h00;
    win_mem[1979] = 8'h00;
    win_mem[1980] = 8'h00;
    win_mem[1981] = 8'h00;
    win_mem[1982] = 8'h00;
    win_mem[1983] = 8'h00;
    win_mem[1984] = 8'h00;
    win_mem[1985] = 8'h00;
    win_mem[1986] = 8'h00;
    win_mem[1987] = 8'h00;
    win_mem[1988] = 8'h00;
    win_mem[1989] = 8'h00;
    win_mem[1990] = 8'h00;
    win_mem[1991] = 8'h00;
    win_mem[1992] = 8'h00;
    win_mem[1993] = 8'h00;
    win_mem[1994] = 8'h00;
    win_mem[1995] = 8'h00;
    win_mem[1996] = 8'h00;
    win_mem[1997] = 8'h00;
    win_mem[1998] = 8'h00;
    win_mem[1999] = 8'h00;
    win_mem[2000] = 8'h00;
    win_mem[2001] = 8'h00;
    win_mem[2002] = 8'h00;
    win_mem[2003] = 8'h00;
    win_mem[2004] = 8'h00;
    win_mem[2005] = 8'h00;
    win_mem[2006] = 8'h00;
    win_mem[2007] = 8'h00;
    win_mem[2008] = 8'h00;
    win_mem[2009] = 8'h00;
    win_mem[2010] = 8'h00;
    win_mem[2011] = 8'h00;
    win_mem[2012] = 8'h00;
    win_mem[2013] = 8'h00;
    win_mem[2014] = 8'h00;
    win_mem[2015] = 8'h00;
    win_mem[2016] = 8'h00;
    win_mem[2017] = 8'h00;
    win_mem[2018] = 8'h00;
    win_mem[2019] = 8'h00;
    win_mem[2020] = 8'h00;
    win_mem[2021] = 8'h00;
    win_mem[2022] = 8'h00;
    win_mem[2023] = 8'h00;
    win_mem[2024] = 8'h00;
    win_mem[2025] = 8'h00;
    win_mem[2026] = 8'h00;
    win_mem[2027] = 8'h00;
    win_mem[2028] = 8'h00;
    win_mem[2029] = 8'h00;
    win_mem[2030] = 8'h00;
    win_mem[2031] = 8'h00;
    win_mem[2032] = 8'h00;
    win_mem[2033] = 8'h00;
    win_mem[2034] = 8'h00;
    win_mem[2035] = 8'h00;
    win_mem[2036] = 8'h00;
    win_mem[2037] = 8'h00;
    win_mem[2038] = 8'h00;
    win_mem[2039] = 8'h00;
    win_mem[2040] = 8'h00;
    win_mem[2041] = 8'h00;
    win_mem[2042] = 8'h00;
    win_mem[2043] = 8'h00;
    win_mem[2044] = 8'h00;
    win_mem[2045] = 8'h00;
    win_mem[2046] = 8'h00;
    win_mem[2047] = 8'h00;
  end
  always @(posedge clk) begin
    if (win_wr__en)
      win_mem[win_wr__addr] <= win_wr__data;
  end
  reg [7:0] _0_;
  always @(posedge clk) begin
    _0_ <= win_mem[win_rd__addr];
  end
  assign win_rd__data = _0_;
  assign _cxb0 = crc_acc[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[0];
  assign \$2  = _cxb0 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs0 = \$1  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$2 ;
  assign _cxb1 = _cs0[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[1];
  assign \$4  = _cxb1 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs1 = \$3  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$4 ;
  assign _cxb2 = _cs1[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[2];
  assign \$6  = _cxb2 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs2 = \$5  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$6 ;
  assign _cxb3 = _cs2[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[3];
  assign \$8  = _cxb3 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs3 = \$7  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$8 ;
  assign _cxb4 = _cs3[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[4];
  assign \$10  = _cxb4 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs4 = \$9  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$10 ;
  assign _cxb5 = _cs4[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[5];
  assign \$12  = _cxb5 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs5 = \$11  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$12 ;
  assign _cxb6 = _cs5[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[6];
  assign \$14  = _cxb6 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs6 = \$13  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$14 ;
  assign _cxb7 = _cs6[0] ^ (* src = "/home/runner/workspace/hardware/outform.py:120" *) crc_byte_in[7];
  assign \$16  = _cxb7 ? (* src = "/home/runner/workspace/hardware/outform.py:121" *) 32'd3988292384 : 32'd0;
  assign _cs7 = \$15  ^ (* src = "/home/runner/workspace/hardware/outform.py:121" *) \$16 ;
  assign \$17  = | (* src = "/home/runner/workspace/hardware/outform.py:346" *) word_count_reg;
  assign \$18  = word_count_reg - (* src = "/home/runner/workspace/hardware/outform.py:347" *) 1'h1;
  assign \$19  = { 1'h0, word_count_reg } & (* src = "/home/runner/workspace/hardware/outform.py:347" *) \$18 ;
  assign \$20  = ! (* src = "/home/runner/workspace/hardware/outform.py:347" *) \$19 ;
  assign \$21  = \$17  & (* src = "/home/runner/workspace/hardware/outform.py:346" *) \$20 ;
  assign \$22  = ! (* src = "/home/runner/workspace/hardware/outform.py:403" *) method_reg;
  assign \$23  = method_reg == (* src = "/home/runner/workspace/hardware/outform.py:425" *) 4'h8;
  assign \$24  = method_reg == (* src = "/home/runner/workspace/hardware/outform.py:434" *) 5'h10;
  assign \$25  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:406" *) 2'h3;
  assign \$27  = mint_base + (* src = "/home/runner/workspace/hardware/outform.py:408" *) \$26 ;
  assign \$28  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:445" *) 2'h3;
  assign \$29  = defl_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:458" *) comp_size_reg;
  assign \$30  = defl_bit_cnt <= (* src = "/home/runner/workspace/hardware/outform.py:461" *) 5'h18;
  assign \$32  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:539" *) 2'h3;
  assign \$34  = mint_base + (* src = "/home/runner/workspace/hardware/outform.py:541" *) \$33 ;
  assign \$37  = defl_bytes_out >= (* src = "/home/runner/workspace/hardware/outform.py:664" *) 12'h800;
  assign \$38  = \$37  ? (* src = "/home/runner/workspace/hardware/outform.py:664" *) 32'd2048 : defl_bytes_out;
  assign \$39  = ! (* src = "/home/runner/workspace/hardware/outform.py:665" *) defl_copy_idx;
  assign \$40  = ! (* src = "/home/runner/workspace/hardware/outform.py:665" *) defl_copy_dist;
  assign \$41  = defl_copy_dist > (* src = "/home/runner/workspace/hardware/outform.py:665" *) defl_hist_depth;
  assign \$42  = \$40  | (* src = "/home/runner/workspace/hardware/outform.py:665" *) \$41 ;
  assign \$43  = \$39  & (* src = "/home/runner/workspace/hardware/outform.py:665" *) \$42 ;
  assign \$44  = defl_win_pos - (* src = "/home/runner/workspace/hardware/outform.py:669" *) defl_copy_dist;
  assign \$46  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:686" *) 2'h3;
  assign \$48  = mint_base + (* src = "/home/runner/workspace/hardware/outform.py:688" *) \$47 ;
  assign \$49  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:763" *) 2'h3;
  assign \$51  = mint_base + (* src = "/home/runner/workspace/hardware/outform.py:765" *) \$50 ;
  assign \$53  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) outform_state;
  assign \$54  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$55  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$56  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$57  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$58  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$59  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$60  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$61  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$62  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$63  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$64  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign \$65  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$66  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$67  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'he;
  assign \$68  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hf;
  assign \$69  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h10;
  assign \$70  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h11;
  assign \$71  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h12;
  assign \$72  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h13;
  assign \$73  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h14;
  assign \$74  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h15;
  assign \$75  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h16;
  assign \$76  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h17;
  assign \$77  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h18;
  assign \$78  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h19;
  assign \$79  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1a;
  assign \$80  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1b;
  assign \$81  = outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 5'h1c;
  assign \$82  = tx_byte_cnt == (* src = "/home/runner/workspace/hardware/outform.py:279" *) 3'h5;
  assign \$83  = tx_byte_cnt + (* src = "/home/runner/workspace/hardware/outform.py:283" *) 1'h1;
  assign \$84  = hdr_byte_cnt + (* src = "/home/runner/workspace/hardware/outform.py:313" *) 1'h1;
  assign \$85  = hdr_byte_cnt == (* src = "/home/runner/workspace/hardware/outform.py:314" *) 5'h1f;
  assign \$86  = sig_reg != (* src = "/home/runner/workspace/hardware/outform.py:319" *) 27'h4034b50;
  assign \$87  = | (* src = "/home/runner/workspace/hardware/outform.py:335" *) ucomp_size_reg[1:0];
  assign \$89  = ~ (* src = "/home/runner/workspace/hardware/outform.py:356" *) is_pow2;
  assign \$90  = n_computed < (* src = "/home/runner/workspace/hardware/outform.py:356" *) 3'h6;
  assign \$91  = \$89  | (* src = "/home/runner/workspace/hardware/outform.py:356" *) \$90 ;
  assign \$92  = n_computed > (* src = "/home/runner/workspace/hardware/outform.py:356" *) 4'he;
  assign \$93  = \$91  | (* src = "/home/runner/workspace/hardware/outform.py:356" *) \$92 ;
  assign \$94  = ! (* src = "/home/runner/workspace/hardware/outform.py:388" *) fname_cnt;
  assign \$95  = fname_cnt - (* src = "/home/runner/workspace/hardware/outform.py:392" *) 1'h1;
  assign \$96  = ! (* src = "/home/runner/workspace/hardware/outform.py:396" *) extra_cnt;
  assign \$97  = extra_cnt - (* src = "/home/runner/workspace/hardware/outform.py:399" *) 1'h1;
  assign \$98  = ! (* src = "/home/runner/workspace/hardware/outform.py:403" *) method_reg;
  assign \$99  = method_reg == (* src = "/home/runner/workspace/hardware/outform.py:425" *) 4'h8;
  assign \$100  = method_reg == (* src = "/home/runner/workspace/hardware/outform.py:434" *) 5'h10;
  assign \$101  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:406" *) 2'h3;
  assign \$102  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:413" *) 1'h1;
  assign \$103  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:417" *) 1'h1;
  assign \$104  = \$103  == (* src = "/home/runner/workspace/hardware/outform.py:417" *) total_words;
  assign \$105  = byte_buf_cnt + (* src = "/home/runner/workspace/hardware/outform.py:424" *) 1'h1;
  assign \$106  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:445" *) 2'h3;
  assign \$107  = defl_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:458" *) comp_size_reg;
  assign \$108  = defl_bit_cnt <= (* src = "/home/runner/workspace/hardware/outform.py:461" *) 5'h18;
  assign \$111  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:451" *) 2'h3;
  assign \$112  = btype == (* src = "/home/runner/workspace/hardware/outform.py:453" *) 1'h1;
  assign \$113  = 1'h0 << (* src = "/home/runner/workspace/hardware/outform.py:463" *) defl_bit_cnt[4:0];
  assign \$114  = { 7'h00, defl_bits } | (* src = "/home/runner/workspace/hardware/outform.py:463" *) \$113 ;
  assign \$115  = defl_bit_cnt + (* src = "/home/runner/workspace/hardware/outform.py:464" *) 4'h8;
  assign \$116  = defl_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:465" *) 1'h1;
  assign \$117  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:470" *) 3'h7;
  assign \$118  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6] } <= (* src = "/home/runner/workspace/hardware/outform.py:470" *) 5'h17;
  assign \$119  = \$117  & (* src = "/home/runner/workspace/hardware/outform.py:470" *) \$118 ;
  assign \$120  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:488" *) 4'h8;
  assign \$121  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } >= (* src = "/home/runner/workspace/hardware/outform.py:488" *) 6'h30;
  assign \$122  = \$120  & (* src = "/home/runner/workspace/hardware/outform.py:488" *) \$121 ;
  assign \$123  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } <= (* src = "/home/runner/workspace/hardware/outform.py:488" *) 8'hbf;
  assign \$124  = \$122  & (* src = "/home/runner/workspace/hardware/outform.py:488" *) \$123 ;
  assign \$125  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:495" *) 4'h8;
  assign \$126  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } >= (* src = "/home/runner/workspace/hardware/outform.py:495" *) 8'hc0;
  assign \$127  = \$125  & (* src = "/home/runner/workspace/hardware/outform.py:495" *) \$126 ;
  assign \$128  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } <= (* src = "/home/runner/workspace/hardware/outform.py:495" *) 8'hc5;
  assign \$129  = \$127  & (* src = "/home/runner/workspace/hardware/outform.py:495" *) \$128 ;
  assign \$130  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:503" *) 4'h8;
  assign \$131  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } >= (* src = "/home/runner/workspace/hardware/outform.py:503" *) 8'hc6;
  assign \$132  = \$130  & (* src = "/home/runner/workspace/hardware/outform.py:503" *) \$131 ;
  assign \$133  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } <= (* src = "/home/runner/workspace/hardware/outform.py:503" *) 8'hc7;
  assign \$134  = \$132  & (* src = "/home/runner/workspace/hardware/outform.py:503" *) \$133 ;
  assign \$135  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:506" *) 4'h9;
  assign \$136  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7], defl_bits[8] } >= (* src = "/home/runner/workspace/hardware/outform.py:506" *) 9'h190;
  assign \$137  = \$135  & (* src = "/home/runner/workspace/hardware/outform.py:506" *) \$136 ;
  assign \$138  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7], defl_bits[8] } <= (* src = "/home/runner/workspace/hardware/outform.py:506" *) 9'h1ff;
  assign \$139  = \$137  & (* src = "/home/runner/workspace/hardware/outform.py:506" *) \$138 ;
  assign \$140  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:513" *) 4'h9;
  assign \$141  = defl_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:516" *) comp_size_reg;
  assign \$142  = defl_bit_cnt <= (* src = "/home/runner/workspace/hardware/outform.py:519" *) 5'h18;
  assign \$144  = 9'h100 + (* src = "/home/runner/workspace/hardware/outform.py:472" *) { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6] };
  assign \$146  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:474" *) 3'h7;
  assign \$147  = ! (* src = "/home/runner/workspace/hardware/outform.py:476" *) { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6] };
  assign \$148  = wr_word_cnt == (* src = "/home/runner/workspace/hardware/outform.py:478" *) total_words;
  assign \$149  = ! (* src = "/home/runner/workspace/hardware/outform.py:478" *) byte_buf_cnt;
  assign \$150  = \$148  & (* src = "/home/runner/workspace/hardware/outform.py:478" *) \$149 ;
  assign \$151  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6] } - (* src = "/home/runner/workspace/hardware/outform.py:486" *) 1'h1;
  assign \$152  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } - (* src = "/home/runner/workspace/hardware/outform.py:490" *) 6'h30;
  assign \$154  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:492" *) 4'h8;
  assign \$155  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } - (* src = "/home/runner/workspace/hardware/outform.py:497" *) 8'hc0;
  assign \$156  = $signed(\$155 ) + (* src = "/home/runner/workspace/hardware/outform.py:497" *) $signed(10'h118);
  assign \$157  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] } - (* src = "/home/runner/workspace/hardware/outform.py:498" *) 8'hc0;
  assign \$158  = $signed(\$157 ) + (* src = "/home/runner/workspace/hardware/outform.py:498" *) $signed(6'h17);
  assign \$160  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:500" *) 4'h8;
  assign \$161  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7], defl_bits[8] } - (* src = "/home/runner/workspace/hardware/outform.py:508" *) 9'h190;
  assign \$162  = $signed(\$161 ) + (* src = "/home/runner/workspace/hardware/outform.py:508" *) $signed(9'h090);
  assign \$164  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:510" *) 4'h9;
  assign \$165  = 1'h0 << (* src = "/home/runner/workspace/hardware/outform.py:521" *) defl_bit_cnt[4:0];
  assign \$166  = { 7'h00, defl_bits } | (* src = "/home/runner/workspace/hardware/outform.py:521" *) \$165 ;
  assign \$167  = defl_bit_cnt + (* src = "/home/runner/workspace/hardware/outform.py:522" *) 4'h8;
  assign \$168  = defl_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:523" *) 1'h1;
  assign \$169  = defl_win_pos + (* src = "/home/runner/workspace/hardware/outform.py:536" *) 1'h1;
  assign \$170  = defl_bytes_out + (* src = "/home/runner/workspace/hardware/outform.py:537" *) 1'h1;
  assign \$171  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:539" *) 2'h3;
  assign \$172  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:546" *) 1'h1;
  assign \$173  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:550" *) 1'h1;
  assign \$174  = \$173  == (* src = "/home/runner/workspace/hardware/outform.py:550" *) total_words;
  assign \$175  = byte_buf_cnt + (* src = "/home/runner/workspace/hardware/outform.py:559" *) 1'h1;
  assign \$176  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:566" *) len_extra_needed;
  assign \$177  = defl_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:601" *) comp_size_reg;
  assign \$178  = defl_bit_cnt <= (* src = "/home/runner/workspace/hardware/outform.py:604" *) 5'h18;
  assign \$182  = \$181  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[0];
  assign \$184  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:574" *) 1'h1;
  assign \$186  = \$185  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[1:0];
  assign \$188  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:580" *) 2'h2;
  assign \$190  = \$189  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[2:0];
  assign \$192  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:586" *) 2'h3;
  assign \$194  = \$193  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[3:0];
  assign \$196  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:592" *) 3'h4;
  assign \$198  = \$197  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[4:0];
  assign \$200  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:598" *) 3'h5;
  assign \$201  = 1'h0 << (* src = "/home/runner/workspace/hardware/outform.py:606" *) defl_bit_cnt[4:0];
  assign \$202  = { 7'h00, defl_bits } | (* src = "/home/runner/workspace/hardware/outform.py:606" *) \$201 ;
  assign \$203  = defl_bit_cnt + (* src = "/home/runner/workspace/hardware/outform.py:607" *) 4'h8;
  assign \$204  = defl_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:608" *) 1'h1;
  assign \$205  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:613" *) 3'h5;
  assign \$206  = defl_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:624" *) comp_size_reg;
  assign \$207  = defl_bit_cnt <= (* src = "/home/runner/workspace/hardware/outform.py:627" *) 5'h18;
  assign \$210  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:617" *) 3'h5;
  assign \$211  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4] } > (* src = "/home/runner/workspace/hardware/outform.py:619" *) 5'h15;
  assign \$212  = 1'h0 << (* src = "/home/runner/workspace/hardware/outform.py:629" *) defl_bit_cnt[4:0];
  assign \$213  = { 7'h00, defl_bits } | (* src = "/home/runner/workspace/hardware/outform.py:629" *) \$212 ;
  assign \$214  = defl_bit_cnt + (* src = "/home/runner/workspace/hardware/outform.py:630" *) 4'h8;
  assign \$215  = defl_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:631" *) 1'h1;
  assign \$216  = defl_bit_cnt >= (* src = "/home/runner/workspace/hardware/outform.py:638" *) dist_extra_needed;
  assign \$217  = defl_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:651" *) comp_size_reg;
  assign \$218  = defl_bit_cnt <= (* src = "/home/runner/workspace/hardware/outform.py:654" *) 5'h18;
  assign \$222  = \$221  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[0];
  assign \$224  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 1'h1;
  assign \$226  = \$225  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[1:0];
  assign \$228  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 2'h2;
  assign \$230  = \$229  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[2:0];
  assign \$232  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 2'h3;
  assign \$234  = \$233  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[3:0];
  assign \$236  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 3'h4;
  assign \$238  = \$237  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[4:0];
  assign \$240  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 3'h5;
  assign \$242  = \$241  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[5:0];
  assign \$244  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 3'h6;
  assign \$246  = \$245  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[6:0];
  assign \$248  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 3'h7;
  assign \$250  = \$249  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[7:0];
  assign \$252  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 4'h8;
  assign \$254  = \$253  + (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_ast.py:2423" *) defl_bits[8:0];
  assign \$256  = defl_bit_cnt - (* src = "/home/runner/workspace/hardware/outform.py:647" *) 4'h9;
  assign \$257  = 1'h0 << (* src = "/home/runner/workspace/hardware/outform.py:656" *) defl_bit_cnt[4:0];
  assign \$258  = { 7'h00, defl_bits } | (* src = "/home/runner/workspace/hardware/outform.py:656" *) \$257 ;
  assign \$259  = defl_bit_cnt + (* src = "/home/runner/workspace/hardware/outform.py:657" *) 4'h8;
  assign \$260  = defl_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:658" *) 1'h1;
  assign \$261  = ! (* src = "/home/runner/workspace/hardware/outform.py:665" *) defl_copy_idx;
  assign \$262  = ! (* src = "/home/runner/workspace/hardware/outform.py:665" *) defl_copy_dist;
  assign \$263  = defl_copy_dist > (* src = "/home/runner/workspace/hardware/outform.py:665" *) defl_hist_depth;
  assign \$264  = \$262  | (* src = "/home/runner/workspace/hardware/outform.py:665" *) \$263 ;
  assign \$265  = \$261  & (* src = "/home/runner/workspace/hardware/outform.py:665" *) \$264 ;
  assign \$266  = defl_win_pos + (* src = "/home/runner/workspace/hardware/outform.py:682" *) 1'h1;
  assign \$267  = defl_bytes_out + (* src = "/home/runner/workspace/hardware/outform.py:683" *) 1'h1;
  assign \$268  = defl_copy_idx + (* src = "/home/runner/workspace/hardware/outform.py:684" *) 1'h1;
  assign \$269  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:686" *) 2'h3;
  assign \$270  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:693" *) 1'h1;
  assign \$271  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:697" *) 1'h1;
  assign \$272  = \$271  == (* src = "/home/runner/workspace/hardware/outform.py:697" *) total_words;
  assign \$273  = defl_copy_idx + (* src = "/home/runner/workspace/hardware/outform.py:699" *) 1'h1;
  assign \$274  = \$273  >= (* src = "/home/runner/workspace/hardware/outform.py:699" *) defl_copy_len;
  assign \$275  = byte_buf_cnt + (* src = "/home/runner/workspace/hardware/outform.py:708" *) 1'h1;
  assign \$276  = defl_copy_idx + (* src = "/home/runner/workspace/hardware/outform.py:709" *) 1'h1;
  assign \$277  = \$276  >= (* src = "/home/runner/workspace/hardware/outform.py:709" *) defl_copy_len;
  assign \$278  = defl_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:716" *) comp_size_reg;
  assign \$279  = defl_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:719" *) 1'h1;
  assign \$280  = rle_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:725" *) comp_size_reg;
  assign \$281  = wr_word_cnt == (* src = "/home/runner/workspace/hardware/outform.py:726" *) total_words;
  assign \$282  = ! (* src = "/home/runner/workspace/hardware/outform.py:726" *) byte_buf_cnt;
  assign \$283  = \$281  & (* src = "/home/runner/workspace/hardware/outform.py:726" *) \$282 ;
  assign \$284  = rle_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:734" *) 1'h1;
  assign \$285  = rle_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:740" *) comp_size_reg;
  assign \$286  = rle_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:747" *) 1'h1;
  assign \$287  = ! (* src = "/home/runner/workspace/hardware/outform.py:749" *) rle_count;
  assign \$288  = rle_remaining - (* src = "/home/runner/workspace/hardware/outform.py:761" *) 1'h1;
  assign \$289  = byte_buf_cnt == (* src = "/home/runner/workspace/hardware/outform.py:763" *) 2'h3;
  assign \$290  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:770" *) 1'h1;
  assign \$291  = wr_word_cnt + (* src = "/home/runner/workspace/hardware/outform.py:774" *) 1'h1;
  assign \$292  = \$291  == (* src = "/home/runner/workspace/hardware/outform.py:774" *) total_words;
  assign \$293  = rle_remaining <= (* src = "/home/runner/workspace/hardware/outform.py:776" *) 1'h1;
  assign \$294  = byte_buf_cnt + (* src = "/home/runner/workspace/hardware/outform.py:785" *) 1'h1;
  assign \$295  = rle_remaining <= (* src = "/home/runner/workspace/hardware/outform.py:786" *) 1'h1;
  assign \$296  = rle_rx_count >= (* src = "/home/runner/workspace/hardware/outform.py:791" *) comp_size_reg;
  assign \$297  = rle_rx_count + (* src = "/home/runner/workspace/hardware/outform.py:794" *) 1'h1;
  assign \$298  = crc_final != (* src = "/home/runner/workspace/hardware/outform.py:802" *) crc32_stored;
  (* src = "/home/runner/workspace/hardware/outform.py:128" *)
  always @(posedge clk)
    hdr_byte_cnt <= \$299 ;
  (* src = "/home/runner/workspace/hardware/outform.py:129" *)
  always @(posedge clk)
    tx_byte_cnt <= \$300 ;
  (* src = "/home/runner/workspace/hardware/outform.py:130" *)
  always @(posedge clk)
    fname_cnt <= \$301 ;
  (* src = "/home/runner/workspace/hardware/outform.py:131" *)
  always @(posedge clk)
    extra_cnt <= \$302 ;
  (* src = "/home/runner/workspace/hardware/outform.py:133" *)
  always @(posedge clk)
    sig_reg <= \$303 ;
  (* src = "/home/runner/workspace/hardware/outform.py:134" *)
  always @(posedge clk)
    flags_reg <= \$304 ;
  (* src = "/home/runner/workspace/hardware/outform.py:135" *)
  always @(posedge clk)
    method_reg <= \$305 ;
  (* src = "/home/runner/workspace/hardware/outform.py:136" *)
  always @(posedge clk)
    crc32_stored <= \$306 ;
  (* src = "/home/runner/workspace/hardware/outform.py:137" *)
  always @(posedge clk)
    comp_size_reg <= \$307 ;
  (* src = "/home/runner/workspace/hardware/outform.py:138" *)
  always @(posedge clk)
    ucomp_size_reg <= \$308 ;
  (* src = "/home/runner/workspace/hardware/outform.py:139" *)
  always @(posedge clk)
    fname_len_reg <= \$309 ;
  (* src = "/home/runner/workspace/hardware/outform.py:140" *)
  always @(posedge clk)
    extra_len_reg <= \$310 ;
  (* src = "/home/runner/workspace/hardware/outform.py:142" *)
  always @(posedge clk)
    word_count_reg <= \$311 ;
  (* src = "/home/runner/workspace/hardware/outform.py:143" *)
  always @(posedge clk)
    mint_n <= \$312 ;
  (* src = "/home/runner/workspace/hardware/outform.py:144" *)
  always @(posedge clk)
    total_words <= \$313 ;
  (* src = "/home/runner/workspace/hardware/outform.py:156" *)
  always @(posedge clk)
    crc_acc <= \$314 ;
  (* src = "/home/runner/workspace/hardware/outform.py:147" *)
  always @(posedge clk)
    wr_word_cnt <= \$315 ;
  (* src = "/home/runner/workspace/hardware/outform.py:148" *)
  always @(posedge clk)
    byte_buf <= \$316 ;
  (* src = "/home/runner/workspace/hardware/outform.py:149" *)
  always @(posedge clk)
    byte_buf_cnt <= \$317 ;
  (* src = "/home/runner/workspace/hardware/outform.py:151" *)
  always @(posedge clk)
    result_gt <= \$318 ;
  (* src = "/home/runner/workspace/hardware/outform.py:171" *)
  always @(posedge clk)
    defl_bits <= \$319 ;
  (* src = "/home/runner/workspace/hardware/outform.py:172" *)
  always @(posedge clk)
    defl_bit_cnt <= \$320 ;
  (* src = "/home/runner/workspace/hardware/outform.py:173" *)
  always @(posedge clk)
    defl_bfinal <= \$321 ;
  (* src = "/home/runner/workspace/hardware/outform.py:174" *)
  always @(posedge clk)
    defl_symbol <= \$322 ;
  (* src = "/home/runner/workspace/hardware/outform.py:175" *)
  always @(posedge clk)
    defl_copy_len <= \$323 ;
  (* src = "/home/runner/workspace/hardware/outform.py:176" *)
  always @(posedge clk)
    defl_copy_dist <= \$324 ;
  (* src = "/home/runner/workspace/hardware/outform.py:177" *)
  always @(posedge clk)
    defl_copy_idx <= \$325 ;
  (* src = "/home/runner/workspace/hardware/outform.py:178" *)
  always @(posedge clk)
    defl_win_pos <= \$326 ;
  (* src = "/home/runner/workspace/hardware/outform.py:179" *)
  always @(posedge clk)
    defl_len_idx <= \$327 ;
  (* src = "/home/runner/workspace/hardware/outform.py:180" *)
  always @(posedge clk)
    defl_dist_code <= \$328 ;
  (* src = "/home/runner/workspace/hardware/outform.py:185" *)
  always @(posedge clk)
    rle_count <= \$329 ;
  (* src = "/home/runner/workspace/hardware/outform.py:186" *)
  always @(posedge clk)
    rle_literal <= \$330 ;
  (* src = "/home/runner/workspace/hardware/outform.py:187" *)
  always @(posedge clk)
    rle_remaining <= \$331 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    outform_state <= \$332 ;
  (* src = "/home/runner/workspace/hardware/outform.py:83" *)
  always @(posedge clk)
    outform_fault_type <= \$333 ;
  (* src = "/home/runner/workspace/hardware/outform.py:146" *)
  always @(posedge clk)
    mint_base <= \$334 ;
  (* src = "/home/runner/workspace/hardware/outform.py:182" *)
  always @(posedge clk)
    defl_bytes_out <= \$335 ;
  (* src = "/home/runner/workspace/hardware/outform.py:181" *)
  always @(posedge clk)
    defl_rx_count <= \$336 ;
  (* src = "/home/runner/workspace/hardware/outform.py:183" *)
  always @(posedge clk)
    rle_rx_count <= \$337 ;
  assign \$auto$rtlil.cc:2739:Not$18  = ~ crc_acc;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$35  = 3'h0;
    casez (defl_len_idx)
      5'h00:
          \$35  = 3'h0;
      5'h01:
          \$35  = 3'h0;
      5'h02:
          \$35  = 3'h0;
      5'h03:
          \$35  = 3'h0;
      5'h04:
          \$35  = 3'h0;
      5'h05:
          \$35  = 3'h0;
      5'h06:
          \$35  = 3'h0;
      5'h07:
          \$35  = 3'h0;
      5'h08:
          \$35  = 3'h1;
      5'h09:
          \$35  = 3'h1;
      5'h0a:
          \$35  = 3'h1;
      5'h0b:
          \$35  = 3'h1;
      5'h0c:
          \$35  = 3'h2;
      5'h0d:
          \$35  = 3'h2;
      5'h0e:
          \$35  = 3'h2;
      5'h0f:
          \$35  = 3'h2;
      5'h10:
          \$35  = 3'h3;
      5'h11:
          \$35  = 3'h3;
      5'h12:
          \$35  = 3'h3;
      5'h13:
          \$35  = 3'h3;
      5'h14:
          \$35  = 3'h4;
      5'h15:
          \$35  = 3'h4;
      5'h16:
          \$35  = 3'h4;
      5'h17:
          \$35  = 3'h4;
      5'h18:
          \$35  = 3'h5;
      5'h19:
          \$35  = 3'h5;
      5'h1a:
          \$35  = 3'h5;
      5'h1b:
          \$35  = 3'h5;
      5'h1c:
          \$35  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$36  = 4'h0;
    casez (defl_dist_code)
      5'h00:
          \$36  = 4'h0;
      5'h01:
          \$36  = 4'h0;
      5'h02:
          \$36  = 4'h0;
      5'h03:
          \$36  = 4'h0;
      5'h04:
          \$36  = 4'h1;
      5'h05:
          \$36  = 4'h1;
      5'h06:
          \$36  = 4'h2;
      5'h07:
          \$36  = 4'h2;
      5'h08:
          \$36  = 4'h3;
      5'h09:
          \$36  = 4'h3;
      5'h0a:
          \$36  = 4'h4;
      5'h0b:
          \$36  = 4'h4;
      5'h0c:
          \$36  = 4'h5;
      5'h0d:
          \$36  = 4'h5;
      5'h0e:
          \$36  = 4'h6;
      5'h0f:
          \$36  = 4'h6;
      5'h10:
          \$36  = 4'h7;
      5'h11:
          \$36  = 4'h7;
      5'h12:
          \$36  = 4'h8;
      5'h13:
          \$36  = 4'h8;
      5'h14:
          \$36  = 4'h9;
      5'h15:
          \$36  = 4'h9;
      5'h16:
          \$36  = 4'ha;
      5'h17:
          \$36  = 4'ha;
      5'h18:
          \$36  = 4'hb;
      5'h19:
          \$36  = 4'hb;
      5'h1a:
          \$36  = 4'hc;
      5'h1b:
          \$36  = 4'hc;
      5'h1c:
          \$36  = 4'hd;
      5'h1d:
          \$36  = 4'hd;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$180  = 9'h000;
    casez (defl_len_idx)
      5'h00:
          \$180  = 9'h003;
      5'h01:
          \$180  = 9'h004;
      5'h02:
          \$180  = 9'h005;
      5'h03:
          \$180  = 9'h006;
      5'h04:
          \$180  = 9'h007;
      5'h05:
          \$180  = 9'h008;
      5'h06:
          \$180  = 9'h009;
      5'h07:
          \$180  = 9'h00a;
      5'h08:
          \$180  = 9'h00b;
      5'h09:
          \$180  = 9'h00d;
      5'h0a:
          \$180  = 9'h00f;
      5'h0b:
          \$180  = 9'h011;
      5'h0c:
          \$180  = 9'h013;
      5'h0d:
          \$180  = 9'h017;
      5'h0e:
          \$180  = 9'h01b;
      5'h0f:
          \$180  = 9'h01f;
      5'h10:
          \$180  = 9'h023;
      5'h11:
          \$180  = 9'h02b;
      5'h12:
          \$180  = 9'h033;
      5'h13:
          \$180  = 9'h03b;
      5'h14:
          \$180  = 9'h043;
      5'h15:
          \$180  = 9'h053;
      5'h16:
          \$180  = 9'h063;
      5'h17:
          \$180  = 9'h073;
      5'h18:
          \$180  = 9'h083;
      5'h19:
          \$180  = 9'h0a3;
      5'h1a:
          \$180  = 9'h0c3;
      5'h1b:
          \$180  = 9'h0e3;
      5'h1c:
          \$180  = 9'h102;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$181  = 9'h000;
    casez (defl_len_idx)
      5'h00:
          \$181  = 9'h003;
      5'h01:
          \$181  = 9'h004;
      5'h02:
          \$181  = 9'h005;
      5'h03:
          \$181  = 9'h006;
      5'h04:
          \$181  = 9'h007;
      5'h05:
          \$181  = 9'h008;
      5'h06:
          \$181  = 9'h009;
      5'h07:
          \$181  = 9'h00a;
      5'h08:
          \$181  = 9'h00b;
      5'h09:
          \$181  = 9'h00d;
      5'h0a:
          \$181  = 9'h00f;
      5'h0b:
          \$181  = 9'h011;
      5'h0c:
          \$181  = 9'h013;
      5'h0d:
          \$181  = 9'h017;
      5'h0e:
          \$181  = 9'h01b;
      5'h0f:
          \$181  = 9'h01f;
      5'h10:
          \$181  = 9'h023;
      5'h11:
          \$181  = 9'h02b;
      5'h12:
          \$181  = 9'h033;
      5'h13:
          \$181  = 9'h03b;
      5'h14:
          \$181  = 9'h043;
      5'h15:
          \$181  = 9'h053;
      5'h16:
          \$181  = 9'h063;
      5'h17:
          \$181  = 9'h073;
      5'h18:
          \$181  = 9'h083;
      5'h19:
          \$181  = 9'h0a3;
      5'h1a:
          \$181  = 9'h0c3;
      5'h1b:
          \$181  = 9'h0e3;
      5'h1c:
          \$181  = 9'h102;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$185  = 9'h000;
    casez (defl_len_idx)
      5'h00:
          \$185  = 9'h003;
      5'h01:
          \$185  = 9'h004;
      5'h02:
          \$185  = 9'h005;
      5'h03:
          \$185  = 9'h006;
      5'h04:
          \$185  = 9'h007;
      5'h05:
          \$185  = 9'h008;
      5'h06:
          \$185  = 9'h009;
      5'h07:
          \$185  = 9'h00a;
      5'h08:
          \$185  = 9'h00b;
      5'h09:
          \$185  = 9'h00d;
      5'h0a:
          \$185  = 9'h00f;
      5'h0b:
          \$185  = 9'h011;
      5'h0c:
          \$185  = 9'h013;
      5'h0d:
          \$185  = 9'h017;
      5'h0e:
          \$185  = 9'h01b;
      5'h0f:
          \$185  = 9'h01f;
      5'h10:
          \$185  = 9'h023;
      5'h11:
          \$185  = 9'h02b;
      5'h12:
          \$185  = 9'h033;
      5'h13:
          \$185  = 9'h03b;
      5'h14:
          \$185  = 9'h043;
      5'h15:
          \$185  = 9'h053;
      5'h16:
          \$185  = 9'h063;
      5'h17:
          \$185  = 9'h073;
      5'h18:
          \$185  = 9'h083;
      5'h19:
          \$185  = 9'h0a3;
      5'h1a:
          \$185  = 9'h0c3;
      5'h1b:
          \$185  = 9'h0e3;
      5'h1c:
          \$185  = 9'h102;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$189  = 9'h000;
    casez (defl_len_idx)
      5'h00:
          \$189  = 9'h003;
      5'h01:
          \$189  = 9'h004;
      5'h02:
          \$189  = 9'h005;
      5'h03:
          \$189  = 9'h006;
      5'h04:
          \$189  = 9'h007;
      5'h05:
          \$189  = 9'h008;
      5'h06:
          \$189  = 9'h009;
      5'h07:
          \$189  = 9'h00a;
      5'h08:
          \$189  = 9'h00b;
      5'h09:
          \$189  = 9'h00d;
      5'h0a:
          \$189  = 9'h00f;
      5'h0b:
          \$189  = 9'h011;
      5'h0c:
          \$189  = 9'h013;
      5'h0d:
          \$189  = 9'h017;
      5'h0e:
          \$189  = 9'h01b;
      5'h0f:
          \$189  = 9'h01f;
      5'h10:
          \$189  = 9'h023;
      5'h11:
          \$189  = 9'h02b;
      5'h12:
          \$189  = 9'h033;
      5'h13:
          \$189  = 9'h03b;
      5'h14:
          \$189  = 9'h043;
      5'h15:
          \$189  = 9'h053;
      5'h16:
          \$189  = 9'h063;
      5'h17:
          \$189  = 9'h073;
      5'h18:
          \$189  = 9'h083;
      5'h19:
          \$189  = 9'h0a3;
      5'h1a:
          \$189  = 9'h0c3;
      5'h1b:
          \$189  = 9'h0e3;
      5'h1c:
          \$189  = 9'h102;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$193  = 9'h000;
    casez (defl_len_idx)
      5'h00:
          \$193  = 9'h003;
      5'h01:
          \$193  = 9'h004;
      5'h02:
          \$193  = 9'h005;
      5'h03:
          \$193  = 9'h006;
      5'h04:
          \$193  = 9'h007;
      5'h05:
          \$193  = 9'h008;
      5'h06:
          \$193  = 9'h009;
      5'h07:
          \$193  = 9'h00a;
      5'h08:
          \$193  = 9'h00b;
      5'h09:
          \$193  = 9'h00d;
      5'h0a:
          \$193  = 9'h00f;
      5'h0b:
          \$193  = 9'h011;
      5'h0c:
          \$193  = 9'h013;
      5'h0d:
          \$193  = 9'h017;
      5'h0e:
          \$193  = 9'h01b;
      5'h0f:
          \$193  = 9'h01f;
      5'h10:
          \$193  = 9'h023;
      5'h11:
          \$193  = 9'h02b;
      5'h12:
          \$193  = 9'h033;
      5'h13:
          \$193  = 9'h03b;
      5'h14:
          \$193  = 9'h043;
      5'h15:
          \$193  = 9'h053;
      5'h16:
          \$193  = 9'h063;
      5'h17:
          \$193  = 9'h073;
      5'h18:
          \$193  = 9'h083;
      5'h19:
          \$193  = 9'h0a3;
      5'h1a:
          \$193  = 9'h0c3;
      5'h1b:
          \$193  = 9'h0e3;
      5'h1c:
          \$193  = 9'h102;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$197  = 9'h000;
    casez (defl_len_idx)
      5'h00:
          \$197  = 9'h003;
      5'h01:
          \$197  = 9'h004;
      5'h02:
          \$197  = 9'h005;
      5'h03:
          \$197  = 9'h006;
      5'h04:
          \$197  = 9'h007;
      5'h05:
          \$197  = 9'h008;
      5'h06:
          \$197  = 9'h009;
      5'h07:
          \$197  = 9'h00a;
      5'h08:
          \$197  = 9'h00b;
      5'h09:
          \$197  = 9'h00d;
      5'h0a:
          \$197  = 9'h00f;
      5'h0b:
          \$197  = 9'h011;
      5'h0c:
          \$197  = 9'h013;
      5'h0d:
          \$197  = 9'h017;
      5'h0e:
          \$197  = 9'h01b;
      5'h0f:
          \$197  = 9'h01f;
      5'h10:
          \$197  = 9'h023;
      5'h11:
          \$197  = 9'h02b;
      5'h12:
          \$197  = 9'h033;
      5'h13:
          \$197  = 9'h03b;
      5'h14:
          \$197  = 9'h043;
      5'h15:
          \$197  = 9'h053;
      5'h16:
          \$197  = 9'h063;
      5'h17:
          \$197  = 9'h073;
      5'h18:
          \$197  = 9'h083;
      5'h19:
          \$197  = 9'h0a3;
      5'h1a:
          \$197  = 9'h0c3;
      5'h1b:
          \$197  = 9'h0e3;
      5'h1c:
          \$197  = 9'h102;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$220  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$220  = 15'h0001;
      5'h01:
          \$220  = 15'h0002;
      5'h02:
          \$220  = 15'h0003;
      5'h03:
          \$220  = 15'h0004;
      5'h04:
          \$220  = 15'h0005;
      5'h05:
          \$220  = 15'h0007;
      5'h06:
          \$220  = 15'h0009;
      5'h07:
          \$220  = 15'h000d;
      5'h08:
          \$220  = 15'h0011;
      5'h09:
          \$220  = 15'h0019;
      5'h0a:
          \$220  = 15'h0021;
      5'h0b:
          \$220  = 15'h0031;
      5'h0c:
          \$220  = 15'h0041;
      5'h0d:
          \$220  = 15'h0061;
      5'h0e:
          \$220  = 15'h0081;
      5'h0f:
          \$220  = 15'h00c1;
      5'h10:
          \$220  = 15'h0101;
      5'h11:
          \$220  = 15'h0181;
      5'h12:
          \$220  = 15'h0201;
      5'h13:
          \$220  = 15'h0301;
      5'h14:
          \$220  = 15'h0401;
      5'h15:
          \$220  = 15'h0601;
      5'h16:
          \$220  = 15'h0801;
      5'h17:
          \$220  = 15'h0c01;
      5'h18:
          \$220  = 15'h1001;
      5'h19:
          \$220  = 15'h1801;
      5'h1a:
          \$220  = 15'h2001;
      5'h1b:
          \$220  = 15'h3001;
      5'h1c:
          \$220  = 15'h4001;
      5'h1d:
          \$220  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$221  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$221  = 15'h0001;
      5'h01:
          \$221  = 15'h0002;
      5'h02:
          \$221  = 15'h0003;
      5'h03:
          \$221  = 15'h0004;
      5'h04:
          \$221  = 15'h0005;
      5'h05:
          \$221  = 15'h0007;
      5'h06:
          \$221  = 15'h0009;
      5'h07:
          \$221  = 15'h000d;
      5'h08:
          \$221  = 15'h0011;
      5'h09:
          \$221  = 15'h0019;
      5'h0a:
          \$221  = 15'h0021;
      5'h0b:
          \$221  = 15'h0031;
      5'h0c:
          \$221  = 15'h0041;
      5'h0d:
          \$221  = 15'h0061;
      5'h0e:
          \$221  = 15'h0081;
      5'h0f:
          \$221  = 15'h00c1;
      5'h10:
          \$221  = 15'h0101;
      5'h11:
          \$221  = 15'h0181;
      5'h12:
          \$221  = 15'h0201;
      5'h13:
          \$221  = 15'h0301;
      5'h14:
          \$221  = 15'h0401;
      5'h15:
          \$221  = 15'h0601;
      5'h16:
          \$221  = 15'h0801;
      5'h17:
          \$221  = 15'h0c01;
      5'h18:
          \$221  = 15'h1001;
      5'h19:
          \$221  = 15'h1801;
      5'h1a:
          \$221  = 15'h2001;
      5'h1b:
          \$221  = 15'h3001;
      5'h1c:
          \$221  = 15'h4001;
      5'h1d:
          \$221  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$225  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$225  = 15'h0001;
      5'h01:
          \$225  = 15'h0002;
      5'h02:
          \$225  = 15'h0003;
      5'h03:
          \$225  = 15'h0004;
      5'h04:
          \$225  = 15'h0005;
      5'h05:
          \$225  = 15'h0007;
      5'h06:
          \$225  = 15'h0009;
      5'h07:
          \$225  = 15'h000d;
      5'h08:
          \$225  = 15'h0011;
      5'h09:
          \$225  = 15'h0019;
      5'h0a:
          \$225  = 15'h0021;
      5'h0b:
          \$225  = 15'h0031;
      5'h0c:
          \$225  = 15'h0041;
      5'h0d:
          \$225  = 15'h0061;
      5'h0e:
          \$225  = 15'h0081;
      5'h0f:
          \$225  = 15'h00c1;
      5'h10:
          \$225  = 15'h0101;
      5'h11:
          \$225  = 15'h0181;
      5'h12:
          \$225  = 15'h0201;
      5'h13:
          \$225  = 15'h0301;
      5'h14:
          \$225  = 15'h0401;
      5'h15:
          \$225  = 15'h0601;
      5'h16:
          \$225  = 15'h0801;
      5'h17:
          \$225  = 15'h0c01;
      5'h18:
          \$225  = 15'h1001;
      5'h19:
          \$225  = 15'h1801;
      5'h1a:
          \$225  = 15'h2001;
      5'h1b:
          \$225  = 15'h3001;
      5'h1c:
          \$225  = 15'h4001;
      5'h1d:
          \$225  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$229  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$229  = 15'h0001;
      5'h01:
          \$229  = 15'h0002;
      5'h02:
          \$229  = 15'h0003;
      5'h03:
          \$229  = 15'h0004;
      5'h04:
          \$229  = 15'h0005;
      5'h05:
          \$229  = 15'h0007;
      5'h06:
          \$229  = 15'h0009;
      5'h07:
          \$229  = 15'h000d;
      5'h08:
          \$229  = 15'h0011;
      5'h09:
          \$229  = 15'h0019;
      5'h0a:
          \$229  = 15'h0021;
      5'h0b:
          \$229  = 15'h0031;
      5'h0c:
          \$229  = 15'h0041;
      5'h0d:
          \$229  = 15'h0061;
      5'h0e:
          \$229  = 15'h0081;
      5'h0f:
          \$229  = 15'h00c1;
      5'h10:
          \$229  = 15'h0101;
      5'h11:
          \$229  = 15'h0181;
      5'h12:
          \$229  = 15'h0201;
      5'h13:
          \$229  = 15'h0301;
      5'h14:
          \$229  = 15'h0401;
      5'h15:
          \$229  = 15'h0601;
      5'h16:
          \$229  = 15'h0801;
      5'h17:
          \$229  = 15'h0c01;
      5'h18:
          \$229  = 15'h1001;
      5'h19:
          \$229  = 15'h1801;
      5'h1a:
          \$229  = 15'h2001;
      5'h1b:
          \$229  = 15'h3001;
      5'h1c:
          \$229  = 15'h4001;
      5'h1d:
          \$229  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$233  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$233  = 15'h0001;
      5'h01:
          \$233  = 15'h0002;
      5'h02:
          \$233  = 15'h0003;
      5'h03:
          \$233  = 15'h0004;
      5'h04:
          \$233  = 15'h0005;
      5'h05:
          \$233  = 15'h0007;
      5'h06:
          \$233  = 15'h0009;
      5'h07:
          \$233  = 15'h000d;
      5'h08:
          \$233  = 15'h0011;
      5'h09:
          \$233  = 15'h0019;
      5'h0a:
          \$233  = 15'h0021;
      5'h0b:
          \$233  = 15'h0031;
      5'h0c:
          \$233  = 15'h0041;
      5'h0d:
          \$233  = 15'h0061;
      5'h0e:
          \$233  = 15'h0081;
      5'h0f:
          \$233  = 15'h00c1;
      5'h10:
          \$233  = 15'h0101;
      5'h11:
          \$233  = 15'h0181;
      5'h12:
          \$233  = 15'h0201;
      5'h13:
          \$233  = 15'h0301;
      5'h14:
          \$233  = 15'h0401;
      5'h15:
          \$233  = 15'h0601;
      5'h16:
          \$233  = 15'h0801;
      5'h17:
          \$233  = 15'h0c01;
      5'h18:
          \$233  = 15'h1001;
      5'h19:
          \$233  = 15'h1801;
      5'h1a:
          \$233  = 15'h2001;
      5'h1b:
          \$233  = 15'h3001;
      5'h1c:
          \$233  = 15'h4001;
      5'h1d:
          \$233  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$237  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$237  = 15'h0001;
      5'h01:
          \$237  = 15'h0002;
      5'h02:
          \$237  = 15'h0003;
      5'h03:
          \$237  = 15'h0004;
      5'h04:
          \$237  = 15'h0005;
      5'h05:
          \$237  = 15'h0007;
      5'h06:
          \$237  = 15'h0009;
      5'h07:
          \$237  = 15'h000d;
      5'h08:
          \$237  = 15'h0011;
      5'h09:
          \$237  = 15'h0019;
      5'h0a:
          \$237  = 15'h0021;
      5'h0b:
          \$237  = 15'h0031;
      5'h0c:
          \$237  = 15'h0041;
      5'h0d:
          \$237  = 15'h0061;
      5'h0e:
          \$237  = 15'h0081;
      5'h0f:
          \$237  = 15'h00c1;
      5'h10:
          \$237  = 15'h0101;
      5'h11:
          \$237  = 15'h0181;
      5'h12:
          \$237  = 15'h0201;
      5'h13:
          \$237  = 15'h0301;
      5'h14:
          \$237  = 15'h0401;
      5'h15:
          \$237  = 15'h0601;
      5'h16:
          \$237  = 15'h0801;
      5'h17:
          \$237  = 15'h0c01;
      5'h18:
          \$237  = 15'h1001;
      5'h19:
          \$237  = 15'h1801;
      5'h1a:
          \$237  = 15'h2001;
      5'h1b:
          \$237  = 15'h3001;
      5'h1c:
          \$237  = 15'h4001;
      5'h1d:
          \$237  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$241  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$241  = 15'h0001;
      5'h01:
          \$241  = 15'h0002;
      5'h02:
          \$241  = 15'h0003;
      5'h03:
          \$241  = 15'h0004;
      5'h04:
          \$241  = 15'h0005;
      5'h05:
          \$241  = 15'h0007;
      5'h06:
          \$241  = 15'h0009;
      5'h07:
          \$241  = 15'h000d;
      5'h08:
          \$241  = 15'h0011;
      5'h09:
          \$241  = 15'h0019;
      5'h0a:
          \$241  = 15'h0021;
      5'h0b:
          \$241  = 15'h0031;
      5'h0c:
          \$241  = 15'h0041;
      5'h0d:
          \$241  = 15'h0061;
      5'h0e:
          \$241  = 15'h0081;
      5'h0f:
          \$241  = 15'h00c1;
      5'h10:
          \$241  = 15'h0101;
      5'h11:
          \$241  = 15'h0181;
      5'h12:
          \$241  = 15'h0201;
      5'h13:
          \$241  = 15'h0301;
      5'h14:
          \$241  = 15'h0401;
      5'h15:
          \$241  = 15'h0601;
      5'h16:
          \$241  = 15'h0801;
      5'h17:
          \$241  = 15'h0c01;
      5'h18:
          \$241  = 15'h1001;
      5'h19:
          \$241  = 15'h1801;
      5'h1a:
          \$241  = 15'h2001;
      5'h1b:
          \$241  = 15'h3001;
      5'h1c:
          \$241  = 15'h4001;
      5'h1d:
          \$241  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$245  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$245  = 15'h0001;
      5'h01:
          \$245  = 15'h0002;
      5'h02:
          \$245  = 15'h0003;
      5'h03:
          \$245  = 15'h0004;
      5'h04:
          \$245  = 15'h0005;
      5'h05:
          \$245  = 15'h0007;
      5'h06:
          \$245  = 15'h0009;
      5'h07:
          \$245  = 15'h000d;
      5'h08:
          \$245  = 15'h0011;
      5'h09:
          \$245  = 15'h0019;
      5'h0a:
          \$245  = 15'h0021;
      5'h0b:
          \$245  = 15'h0031;
      5'h0c:
          \$245  = 15'h0041;
      5'h0d:
          \$245  = 15'h0061;
      5'h0e:
          \$245  = 15'h0081;
      5'h0f:
          \$245  = 15'h00c1;
      5'h10:
          \$245  = 15'h0101;
      5'h11:
          \$245  = 15'h0181;
      5'h12:
          \$245  = 15'h0201;
      5'h13:
          \$245  = 15'h0301;
      5'h14:
          \$245  = 15'h0401;
      5'h15:
          \$245  = 15'h0601;
      5'h16:
          \$245  = 15'h0801;
      5'h17:
          \$245  = 15'h0c01;
      5'h18:
          \$245  = 15'h1001;
      5'h19:
          \$245  = 15'h1801;
      5'h1a:
          \$245  = 15'h2001;
      5'h1b:
          \$245  = 15'h3001;
      5'h1c:
          \$245  = 15'h4001;
      5'h1d:
          \$245  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$249  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$249  = 15'h0001;
      5'h01:
          \$249  = 15'h0002;
      5'h02:
          \$249  = 15'h0003;
      5'h03:
          \$249  = 15'h0004;
      5'h04:
          \$249  = 15'h0005;
      5'h05:
          \$249  = 15'h0007;
      5'h06:
          \$249  = 15'h0009;
      5'h07:
          \$249  = 15'h000d;
      5'h08:
          \$249  = 15'h0011;
      5'h09:
          \$249  = 15'h0019;
      5'h0a:
          \$249  = 15'h0021;
      5'h0b:
          \$249  = 15'h0031;
      5'h0c:
          \$249  = 15'h0041;
      5'h0d:
          \$249  = 15'h0061;
      5'h0e:
          \$249  = 15'h0081;
      5'h0f:
          \$249  = 15'h00c1;
      5'h10:
          \$249  = 15'h0101;
      5'h11:
          \$249  = 15'h0181;
      5'h12:
          \$249  = 15'h0201;
      5'h13:
          \$249  = 15'h0301;
      5'h14:
          \$249  = 15'h0401;
      5'h15:
          \$249  = 15'h0601;
      5'h16:
          \$249  = 15'h0801;
      5'h17:
          \$249  = 15'h0c01;
      5'h18:
          \$249  = 15'h1001;
      5'h19:
          \$249  = 15'h1801;
      5'h1a:
          \$249  = 15'h2001;
      5'h1b:
          \$249  = 15'h3001;
      5'h1c:
          \$249  = 15'h4001;
      5'h1d:
          \$249  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$253  = 15'h0000;
    casez (defl_dist_code)
      5'h00:
          \$253  = 15'h0001;
      5'h01:
          \$253  = 15'h0002;
      5'h02:
          \$253  = 15'h0003;
      5'h03:
          \$253  = 15'h0004;
      5'h04:
          \$253  = 15'h0005;
      5'h05:
          \$253  = 15'h0007;
      5'h06:
          \$253  = 15'h0009;
      5'h07:
          \$253  = 15'h000d;
      5'h08:
          \$253  = 15'h0011;
      5'h09:
          \$253  = 15'h0019;
      5'h0a:
          \$253  = 15'h0021;
      5'h0b:
          \$253  = 15'h0031;
      5'h0c:
          \$253  = 15'h0041;
      5'h0d:
          \$253  = 15'h0061;
      5'h0e:
          \$253  = 15'h0081;
      5'h0f:
          \$253  = 15'h00c1;
      5'h10:
          \$253  = 15'h0101;
      5'h11:
          \$253  = 15'h0181;
      5'h12:
          \$253  = 15'h0201;
      5'h13:
          \$253  = 15'h0301;
      5'h14:
          \$253  = 15'h0401;
      5'h15:
          \$253  = 15'h0601;
      5'h16:
          \$253  = 15'h0801;
      5'h17:
          \$253  = 15'h0c01;
      5'h18:
          \$253  = 15'h1001;
      5'h19:
          \$253  = 15'h1801;
      5'h1a:
          \$253  = 15'h2001;
      5'h1b:
          \$253  = 15'h3001;
      5'h1c:
          \$253  = 15'h4001;
      5'h1d:
          \$253  = 15'h6001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    crc_byte_in = 8'h00;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          crc_byte_in = defl_symbol[7:0];
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          crc_byte_in = win_rd__data;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          crc_byte_in = rle_literal;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    win_wr__addr = 11'h000;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          win_wr__addr = defl_win_pos;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          win_wr__addr = defl_win_pos;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    win_wr__data = 8'h00;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          win_wr__data = defl_symbol[7:0];
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          win_wr__data = win_rd__data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    win_wr__en = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          win_wr__en = 1'h1;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          win_wr__en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    (* full_case = 32'd1 *)
    casez (tx_byte_cnt)
      3'h0:
          tx_byte = gt_raw[7:0];
      3'h1:
          tx_byte = gt_raw[15:8];
      3'h2:
          tx_byte = gt_raw[23:16];
      3'h3:
          tx_byte = gt_raw[31:24];
      3'h4:
          tx_byte = slot_id[7:0];
      3'h5:
          tx_byte = slot_id[15:8];
      default:
          tx_byte = 8'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    outform_busy = 1'h0;
    casez (outform_state)
      5'h00:
          outform_busy = 1'h0;
      5'h01:
          outform_busy = 1'h1;
      5'h02:
          outform_busy = 1'h1;
      5'h03:
          outform_busy = 1'h1;
      5'h05:
          outform_busy = 1'h1;
      5'h06:
          outform_busy = 1'h1;
      5'h07:
          outform_busy = 1'h1;
      5'h08:
          outform_busy = 1'h1;
      5'h09:
          outform_busy = 1'h1;
      5'h0a:
          outform_busy = 1'h1;
      5'h0b:
          outform_busy = 1'h1;
      5'h0d:
          outform_busy = 1'h1;
      5'h0f:
          outform_busy = 1'h1;
      5'h12:
          outform_busy = 1'h1;
      5'h11:
          outform_busy = 1'h1;
      5'h13:
          outform_busy = 1'h1;
      5'h14:
          outform_busy = 1'h1;
      5'h15:
          outform_busy = 1'h1;
      5'h16:
          outform_busy = 1'h1;
      5'h10:
          outform_busy = 1'h1;
      5'h0e:
          outform_busy = 1'h1;
      5'h17:
          outform_busy = 1'h1;
      5'h18:
          outform_busy = 1'h1;
      5'h19:
          outform_busy = 1'h1;
      5'h0c:
          outform_busy = 1'h1;
      5'h1a:
          outform_busy = 1'h1;
      5'h1b:
          outform_busy = 1'h1;
      5'h1c:
          outform_busy = 1'h0;
      5'h04:
          outform_busy = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    tx_valid = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          tx_valid = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    is_pow2 = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          is_pow2 = \$21 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    n_computed = 5'h00;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          (* full_case = 32'd1 *)
          casez (word_count_reg)
            32'd64:
                n_computed = 5'h06;
            32'd128:
                n_computed = 5'h07;
            32'd256:
                n_computed = 5'h08;
            32'd512:
                n_computed = 5'h09;
            32'd1024:
                n_computed = 5'h0a;
            32'd2048:
                n_computed = 5'h0b;
            32'd4096:
                n_computed = 5'h0c;
            32'd8192:
                n_computed = 5'h0d;
            32'd16384:
                n_computed = 5'h0e;
            default:
                n_computed = 5'h00;
          endcase
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    alloc_req = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          alloc_req = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    alloc_n = 5'h00;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          alloc_n = mint_n;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    mem_wr_addr = 32'd0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          if (\$32 ) begin
            mem_wr_addr = \$34 [31:0];
          end
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          if (\$46 ) begin
            mem_wr_addr = \$48 [31:0];
          end
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          if (\$49 ) begin
            mem_wr_addr = \$51 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    mem_wr_data = 32'd0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          if (\$32 ) begin
            mem_wr_data = { defl_symbol[7:0], byte_buf };
          end
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          if (\$46 ) begin
            mem_wr_data = { win_rd__data, byte_buf };
          end
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          if (\$49 ) begin
            mem_wr_data = { rle_literal, byte_buf };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    mem_wr_en = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          if (\$32 ) begin
            mem_wr_en = 1'h1;
          end
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          if (\$46 ) begin
            mem_wr_en = 1'h1;
          end
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          if (\$49 ) begin
            mem_wr_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    btype = 2'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          if (\$28 ) begin
            btype = defl_bits[2:1];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    len_extra_needed = 4'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          len_extra_needed = { 1'h0, \$35  };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    dist_extra_needed = 4'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          dist_extra_needed = \$36 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    defl_hist_depth = 32'd0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          defl_hist_depth = \$38 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    win_rd__addr = 11'h000;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          (* full_case = 32'd1 *)
          if (\$43 ) begin
          end else begin
            win_rd__addr = \$45 [10:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    crc_final = 32'd0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h19:
          /* empty */;
      5'h0c:
          crc_final = \$52 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    mint_call = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h19:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h1a:
          mint_call = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    outform_done = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h19:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h1a:
          /* empty */;
      5'h1b:
          /* empty */;
      5'h1c:
          outform_done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    outform_fault = 1'h0;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h19:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h1a:
          /* empty */;
      5'h1b:
          /* empty */;
      5'h1c:
          /* empty */;
      5'h04:
          outform_fault = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$299  = hdr_byte_cnt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$299  = 6'h00;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$300  = tx_byte_cnt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$300  = 3'h0;
          end
      5'h01:
          (* full_case = 32'd1 *)
          if (\$82 ) begin
            \$300  = 3'h0;
          end else begin
            \$300  = \$83 [2:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$301  = fname_cnt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$301  = 16'h0000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          if (alloc_fault) begin
          end else if (alloc_done) begin
            \$301  = fname_len_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$302  = extra_cnt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$302  = 16'h0000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          if (\$94 ) begin
            \$302  = extra_len_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$303  = sig_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$303  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$304  = flags_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$304  = 16'h0000;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$305  = method_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$305  = 16'h0000;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$306  = crc32_stored;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$306  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$307  = comp_size_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$307  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$308  = ucomp_size_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$308  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$309  = fname_len_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$309  = 16'h0000;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$310  = extra_len_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$310  = 16'h0000;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$311  = word_count_reg;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$311  = 32'd0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          (* full_case = 32'd1 *)
          if (\$87 ) begin
          end else begin
            \$311  = \$88 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$312  = mint_n;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$312  = 5'h00;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          (* full_case = 32'd1 *)
          if (\$93 ) begin
          end else begin
            \$312  = n_computed;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$313  = total_words;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$313  = 32'd0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          (* full_case = 32'd1 *)
          if (\$93 ) begin
          end else begin
            \$313  = word_count_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$314  = crc_acc;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$314  = 32'd4294967295;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          if (alloc_fault) begin
          end else if (alloc_done) begin
            \$314  = 32'd4294967295;
          end
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          \$314  = _cs7;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          \$314  = _cs7;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          \$314  = _cs7;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$315  = wr_word_cnt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$315  = 32'd0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          if (alloc_fault) begin
          end else if (alloc_done) begin
            \$315  = 32'd0;
          end
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          if (\$171 ) begin
            \$315  = \$172 [31:0];
          end
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          if (\$269 ) begin
            \$315  = \$270 [31:0];
          end
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          if (\$289 ) begin
            \$315  = \$290 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$316  = byte_buf;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$316  = 24'h000000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          if (alloc_fault) begin
          end else if (alloc_done) begin
            \$316  = 24'h000000;
          end
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          (* full_case = 32'd1 *)
          if (\$171 ) begin
            \$316  = 24'h000000;
          end else begin
            casez (byte_buf_cnt)
              2'h0:
                  \$316 [7:0] = defl_symbol[7:0];
              2'h1:
                  \$316 [15:8] = defl_symbol[7:0];
              2'h2:
                  \$316 [23:16] = defl_symbol[7:0];
            endcase
          end
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          (* full_case = 32'd1 *)
          if (\$269 ) begin
            \$316  = 24'h000000;
          end else begin
            casez (byte_buf_cnt)
              2'h0:
                  \$316 [7:0] = win_rd__data;
              2'h1:
                  \$316 [15:8] = win_rd__data;
              2'h2:
                  \$316 [23:16] = win_rd__data;
            endcase
          end
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          (* full_case = 32'd1 *)
          if (\$289 ) begin
            \$316  = 24'h000000;
          end else begin
            casez (byte_buf_cnt)
              2'h0:
                  \$316 [7:0] = rle_literal;
              2'h1:
                  \$316 [15:8] = rle_literal;
              2'h2:
                  \$316 [23:16] = rle_literal;
            endcase
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$317  = byte_buf_cnt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$317  = 2'h0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          if (alloc_fault) begin
          end else if (alloc_done) begin
            \$317  = 2'h0;
          end
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          (* full_case = 32'd1 *)
          if (\$171 ) begin
            \$317  = 2'h0;
          end else begin
            \$317  = \$175 [1:0];
          end
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          (* full_case = 32'd1 *)
          if (\$269 ) begin
            \$317  = 2'h0;
          end else begin
            \$317  = \$275 [1:0];
          end
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          (* full_case = 32'd1 *)
          if (\$289 ) begin
            \$317  = 2'h0;
          end else begin
            \$317  = \$294 [1:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$318  = result_gt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$318  = 32'd0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          /* empty */;
      5'h19:
          /* empty */;
      5'h0c:
          /* empty */;
      5'h1a:
          /* empty */;
      5'h1b:
          if (mint_fault) begin
          end else if (mint_done) begin
            \$318  = mint_result_gt;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$319  = defl_bits;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$319  = 32'd0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (\$98 ) begin
          end else if (\$99 ) begin
            \$319  = 32'd0;
          end
      5'h0d:
          if (\$106 ) begin
            \$319  = \$110 ;
          end else if (\$107 ) begin
          end else if (\$109 ) begin
            \$319  = \$114 [31:0];
          end
      5'h0f:
          if (\$119 ) begin
            \$319  = \$145 ;
          end else if (\$124 ) begin
            \$319  = \$153 ;
          end else if (\$129 ) begin
            \$319  = \$159 ;
          end else if (\$134 ) begin
          end else if (\$139 ) begin
            \$319  = \$163 ;
          end else if (\$140 ) begin
          end else if (\$141 ) begin
          end else if (\$143 ) begin
            \$319  = \$166 [31:0];
          end
      5'h12:
          /* empty */;
      5'h11:
          if (\$176 ) begin
            casez (len_extra_needed)
              4'h0:
                  /* empty */;
              4'h1:
                  \$319  = \$183 ;
              4'h2:
                  \$319  = \$187 ;
              4'h3:
                  \$319  = \$191 ;
              4'h4:
                  \$319  = \$195 ;
              4'h5:
                  \$319  = \$199 ;
            endcase
          end else if (\$177 ) begin
          end else if (\$179 ) begin
            \$319  = \$202 [31:0];
          end
      5'h13:
          if (\$205 ) begin
            \$319  = \$209 ;
          end else if (\$206 ) begin
          end else if (\$208 ) begin
            \$319  = \$213 [31:0];
          end
      5'h14:
          if (\$216 ) begin
            casez (dist_extra_needed)
              4'h0:
                  /* empty */;
              4'h1:
                  \$319  = \$223 ;
              4'h2:
                  \$319  = \$227 ;
              4'h3:
                  \$319  = \$231 ;
              4'h4:
                  \$319  = \$235 ;
              4'h5:
                  \$319  = \$239 ;
              4'h6:
                  \$319  = \$243 ;
              4'h7:
                  \$319  = \$247 ;
              4'h8:
                  \$319  = \$251 ;
              4'h9:
                  \$319  = \$255 ;
            endcase
          end else if (\$217 ) begin
          end else if (\$219 ) begin
            \$319  = \$258 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$320  = defl_bit_cnt;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$320  = 6'h00;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (\$98 ) begin
          end else if (\$99 ) begin
            \$320  = 6'h00;
          end
      5'h0d:
          if (\$106 ) begin
            \$320  = \$111 [5:0];
          end else if (\$107 ) begin
          end else if (\$109 ) begin
            \$320  = \$115 [5:0];
          end
      5'h0f:
          if (\$119 ) begin
            \$320  = \$146 [5:0];
          end else if (\$124 ) begin
            \$320  = \$154 [5:0];
          end else if (\$129 ) begin
            \$320  = \$160 [5:0];
          end else if (\$134 ) begin
          end else if (\$139 ) begin
            \$320  = \$164 [5:0];
          end else if (\$140 ) begin
          end else if (\$141 ) begin
          end else if (\$143 ) begin
            \$320  = \$167 [5:0];
          end
      5'h12:
          /* empty */;
      5'h11:
          if (\$176 ) begin
            casez (len_extra_needed)
              4'h0:
                  /* empty */;
              4'h1:
                  \$320  = \$184 [5:0];
              4'h2:
                  \$320  = \$188 [5:0];
              4'h3:
                  \$320  = \$192 [5:0];
              4'h4:
                  \$320  = \$196 [5:0];
              4'h5:
                  \$320  = \$200 [5:0];
            endcase
          end else if (\$177 ) begin
          end else if (\$179 ) begin
            \$320  = \$203 [5:0];
          end
      5'h13:
          if (\$205 ) begin
            \$320  = \$210 [5:0];
          end else if (\$206 ) begin
          end else if (\$208 ) begin
            \$320  = \$214 [5:0];
          end
      5'h14:
          if (\$216 ) begin
            casez (dist_extra_needed)
              4'h0:
                  /* empty */;
              4'h1:
                  \$320  = \$224 [5:0];
              4'h2:
                  \$320  = \$228 [5:0];
              4'h3:
                  \$320  = \$232 [5:0];
              4'h4:
                  \$320  = \$236 [5:0];
              4'h5:
                  \$320  = \$240 [5:0];
              4'h6:
                  \$320  = \$244 [5:0];
              4'h7:
                  \$320  = \$248 [5:0];
              4'h8:
                  \$320  = \$252 [5:0];
              4'h9:
                  \$320  = \$256 [5:0];
            endcase
          end else if (\$217 ) begin
          end else if (\$219 ) begin
            \$320  = \$259 [5:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$321  = defl_bfinal;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$321  = 1'h0;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          if (\$106 ) begin
            \$321  = defl_bits[0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$322  = defl_symbol;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$322  = 9'h000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          if (\$119 ) begin
            \$322  = \$144 [8:0];
          end else if (\$124 ) begin
            \$322  = \$152 ;
          end else if (\$129 ) begin
            \$322  = \$156 [8:0];
          end else if (\$134 ) begin
          end else if (\$139 ) begin
            \$322  = \$162 [8:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$323  = defl_copy_len;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$323  = 9'h000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          if (\$176 ) begin
            casez (len_extra_needed)
              4'h0:
                  \$323  = \$180 ;
              4'h1:
                  \$323  = \$182 [8:0];
              4'h2:
                  \$323  = \$186 [8:0];
              4'h3:
                  \$323  = \$190 [8:0];
              4'h4:
                  \$323  = \$194 [8:0];
              4'h5:
                  \$323  = \$198 [8:0];
            endcase
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$324  = defl_copy_dist;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$324  = 12'h000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          if (\$216 ) begin
            casez (dist_extra_needed)
              4'h0:
                  \$324  = \$220 [11:0];
              4'h1:
                  \$324  = \$222 [11:0];
              4'h2:
                  \$324  = \$226 [11:0];
              4'h3:
                  \$324  = \$230 [11:0];
              4'h4:
                  \$324  = \$234 [11:0];
              4'h5:
                  \$324  = \$238 [11:0];
              4'h6:
                  \$324  = \$242 [11:0];
              4'h7:
                  \$324  = \$246 [11:0];
              4'h8:
                  \$324  = \$250 [11:0];
              4'h9:
                  \$324  = \$254 [11:0];
            endcase
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$325  = defl_copy_idx;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$325  = 9'h000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          if (\$216 ) begin
            \$325  = 9'h000;
          end
      5'h15:
          /* empty */;
      5'h16:
          \$325  = \$268 [8:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$326  = defl_win_pos;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$326  = 11'h000;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (\$98 ) begin
          end else if (\$99 ) begin
            \$326  = 11'h000;
          end
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          \$326  = \$169 [10:0];
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          \$326  = \$266 [10:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$327  = defl_len_idx;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$327  = 5'h00;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          if (\$119 ) begin
            (* full_case = 32'd1 *)
            if (\$147 ) begin
            end else begin
              \$327  = \$151 [4:0];
            end
          end else if (\$124 ) begin
          end else if (\$129 ) begin
            \$327  = \$158 [4:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$328  = defl_dist_code;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$328  = 5'h00;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          if (\$205 ) begin
            \$328  = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$329  = rle_count;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$329  = 8'h00;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$330  = rle_literal;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$330  = 8'h00;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$331  = rle_remaining;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$331  = 8'h00;
          end
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          /* empty */;
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          /* empty */;
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          /* empty */;
      5'h10:
          /* empty */;
      5'h0e:
          /* empty */;
      5'h17:
          /* empty */;
      5'h18:
          \$331  = \$288 [7:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$332  = outform_state;
    casez (outform_state)
      5'h00:
          if (outform_start) begin
            \$332  = 5'h01;
          end
      5'h01:
          if (\$82 ) begin
            \$332  = 5'h02;
          end
      5'h02:
          /* empty */;
      5'h03:
          (* full_case = 32'd1 *)
          if (\$86 ) begin
            \$332  = 5'h04;
          end else begin
            \$332  = 5'h05;
          end
      5'h05:
          (* full_case = 32'd1 *)
          if (flags_reg[3]) begin
            \$332  = 5'h04;
          end else begin
            \$332  = 5'h06;
          end
      5'h06:
          (* full_case = 32'd1 *)
          if (\$87 ) begin
            \$332  = 5'h04;
          end else begin
            \$332  = 5'h07;
          end
      5'h07:
          (* full_case = 32'd1 *)
          if (\$93 ) begin
            \$332  = 5'h04;
          end else begin
            \$332  = 5'h08;
          end
      5'h08:
          if (alloc_fault) begin
            \$332  = 5'h04;
          end else if (alloc_done) begin
            \$332  = 5'h09;
          end
      5'h09:
          if (\$94 ) begin
            \$332  = 5'h0a;
          end
      5'h0a:
          if (\$96 ) begin
            \$332  = 5'h0b;
          end
      5'h0b:
          (* full_case = 32'd1 *)
          if (\$98 ) begin
          end else if (\$99 ) begin
            \$332  = 5'h0d;
          end else if (\$100 ) begin
            \$332  = 5'h0e;
          end else begin
            \$332  = 5'h04;
          end
      5'h0d:
          if (\$106 ) begin
            (* full_case = 32'd1 *)
            if (\$112 ) begin
              \$332  = 5'h0f;
            end else begin
              \$332  = 5'h04;
            end
          end else if (\$107 ) begin
            \$332  = 5'h04;
          end
      5'h0f:
          if (\$119 ) begin
            (* full_case = 32'd1 *)
            if (\$147 ) begin
              (* full_case = 32'd1 *)
              if (defl_bfinal) begin
                (* full_case = 32'd1 *)
                if (\$150 ) begin
                  \$332  = 5'h10;
                end else begin
                  \$332  = 5'h04;
                end
              end else begin
                \$332  = 5'h0d;
              end
            end else begin
              \$332  = 5'h11;
            end
          end else if (\$124 ) begin
            \$332  = 5'h12;
          end else if (\$129 ) begin
            \$332  = 5'h11;
          end else if (\$134 ) begin
            \$332  = 5'h04;
          end else if (\$139 ) begin
            \$332  = 5'h12;
          end else if (\$140 ) begin
            \$332  = 5'h04;
          end else if (\$141 ) begin
            \$332  = 5'h04;
          end
      5'h12:
          (* full_case = 32'd1 *)
          if (\$171 ) begin
            (* full_case = 32'd1 *)
            if (\$174 ) begin
              \$332  = 5'h10;
            end else begin
              \$332  = 5'h0f;
            end
          end else begin
            \$332  = 5'h0f;
          end
      5'h11:
          if (\$176 ) begin
            \$332  = 5'h13;
          end else if (\$177 ) begin
            \$332  = 5'h04;
          end
      5'h13:
          if (\$205 ) begin
            (* full_case = 32'd1 *)
            if (\$211 ) begin
              \$332  = 5'h04;
            end else begin
              \$332  = 5'h14;
            end
          end else if (\$206 ) begin
            \$332  = 5'h04;
          end
      5'h14:
          if (\$216 ) begin
            \$332  = 5'h15;
          end else if (\$217 ) begin
            \$332  = 5'h04;
          end
      5'h15:
          (* full_case = 32'd1 *)
          if (\$265 ) begin
            \$332  = 5'h04;
          end else begin
            \$332  = 5'h16;
          end
      5'h16:
          (* full_case = 32'd1 *)
          if (\$269 ) begin
            (* full_case = 32'd1 *)
            if (\$272 ) begin
              \$332  = 5'h10;
            end else if (\$274 ) begin
              \$332  = 5'h0f;
            end else begin
              \$332  = 5'h15;
            end
          end else begin
            (* full_case = 32'd1 *)
            if (\$277 ) begin
              \$332  = 5'h0f;
            end else begin
              \$332  = 5'h15;
            end
          end
      5'h10:
          if (\$278 ) begin
            \$332  = 5'h0c;
          end
      5'h0e:
          if (\$280 ) begin
            (* full_case = 32'd1 *)
            if (\$283 ) begin
              \$332  = 5'h0c;
            end else begin
              \$332  = 5'h04;
            end
          end
      5'h17:
          if (\$285 ) begin
            \$332  = 5'h04;
          end
      5'h18:
          (* full_case = 32'd1 *)
          if (\$289 ) begin
            if (\$292 ) begin
              \$332  = 5'h19;
            end else if (\$293 ) begin
              \$332  = 5'h0e;
            end
          end else begin
            if (\$295 ) begin
              \$332  = 5'h0e;
            end
          end
      5'h19:
          if (\$296 ) begin
            \$332  = 5'h0c;
          end
      5'h0c:
          (* full_case = 32'd1 *)
          if (\$298 ) begin
            \$332  = 5'h04;
          end else begin
            \$332  = 5'h1a;
          end
      5'h1a:
          \$332  = 5'h1b;
      5'h1b:
          if (mint_fault) begin
            \$332  = 5'h04;
          end else if (mint_done) begin
            \$332  = 5'h1c;
          end
      5'h1c:
          \$332  = 5'h00;
      5'h04:
          \$332  = 5'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$333  = outform_fault_type;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          if (\$86 ) begin
            \$333  = 5'h11;
          end
      5'h05:
          if (flags_reg[3]) begin
            \$333  = 5'h12;
          end
      5'h06:
          if (\$87 ) begin
            \$333  = 5'h14;
          end
      5'h07:
          if (\$93 ) begin
            \$333  = 5'h14;
          end
      5'h08:
          if (alloc_fault) begin
            \$333  = 5'h16;
          end
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          (* full_case = 32'd1 *)
          if (\$98 ) begin
          end else if (\$99 ) begin
          end else if (\$100 ) begin
          end else begin
            \$333  = 5'h13;
          end
      5'h0d:
          if (\$106 ) begin
            (* full_case = 32'd1 *)
            if (\$112 ) begin
            end else begin
              \$333  = 5'h18;
            end
          end else if (\$107 ) begin
            \$333  = 5'h18;
          end
      5'h0f:
          if (\$119 ) begin
            if (\$147 ) begin
              if (defl_bfinal) begin
                (* full_case = 32'd1 *)
                if (\$150 ) begin
                end else begin
                  \$333  = 5'h18;
                end
              end
            end
          end else if (\$124 ) begin
          end else if (\$129 ) begin
          end else if (\$134 ) begin
            \$333  = 5'h18;
          end else if (\$139 ) begin
          end else if (\$140 ) begin
            \$333  = 5'h18;
          end else if (\$141 ) begin
            \$333  = 5'h18;
          end
      5'h12:
          /* empty */;
      5'h11:
          if (\$176 ) begin
          end else if (\$177 ) begin
            \$333  = 5'h18;
          end
      5'h13:
          if (\$205 ) begin
            if (\$211 ) begin
              \$333  = 5'h19;
            end
          end else if (\$206 ) begin
            \$333  = 5'h18;
          end
      5'h14:
          if (\$216 ) begin
          end else if (\$217 ) begin
            \$333  = 5'h18;
          end
      5'h15:
          if (\$265 ) begin
            \$333  = 5'h19;
          end
      5'h16:
          /* empty */;
      5'h10:
          /* empty */;
      5'h0e:
          if (\$280 ) begin
            (* full_case = 32'd1 *)
            if (\$283 ) begin
            end else begin
              \$333  = 5'h1a;
            end
          end
      5'h17:
          if (\$285 ) begin
            \$333  = 5'h1a;
          end
      5'h18:
          /* empty */;
      5'h19:
          /* empty */;
      5'h0c:
          if (\$298 ) begin
            \$333  = 5'h15;
          end
      5'h1a:
          /* empty */;
      5'h1b:
          if (mint_fault) begin
            \$333  = 5'h17;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$334  = mint_base;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          if (alloc_fault) begin
          end else if (alloc_done) begin
            \$334  = alloc_base;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$335  = defl_bytes_out;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (\$98 ) begin
          end else if (\$99 ) begin
            \$335  = 32'd0;
          end
      5'h0d:
          /* empty */;
      5'h0f:
          /* empty */;
      5'h12:
          \$335  = \$170 [31:0];
      5'h11:
          /* empty */;
      5'h13:
          /* empty */;
      5'h14:
          /* empty */;
      5'h15:
          /* empty */;
      5'h16:
          \$335  = \$267 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$336  = defl_rx_count;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (\$98 ) begin
          end else if (\$99 ) begin
            \$336  = 32'd0;
          end
      5'h0d:
          if (\$106 ) begin
          end else if (\$107 ) begin
          end else if (\$109 ) begin
            \$336  = \$116 [31:0];
          end
      5'h0f:
          if (\$119 ) begin
          end else if (\$124 ) begin
          end else if (\$129 ) begin
          end else if (\$134 ) begin
          end else if (\$139 ) begin
          end else if (\$140 ) begin
          end else if (\$141 ) begin
          end else if (\$143 ) begin
            \$336  = \$168 [31:0];
          end
      5'h12:
          /* empty */;
      5'h11:
          if (\$176 ) begin
          end else if (\$177 ) begin
          end else if (\$179 ) begin
            \$336  = \$204 [31:0];
          end
      5'h13:
          if (\$205 ) begin
          end else if (\$206 ) begin
          end else if (\$208 ) begin
            \$336  = \$215 [31:0];
          end
      5'h14:
          if (\$216 ) begin
          end else if (\$217 ) begin
          end else if (\$219 ) begin
            \$336  = \$260 [31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$60 ) begin end
    \$337  = rle_rx_count;
    casez (outform_state)
      5'h00:
          /* empty */;
      5'h01:
          /* empty */;
      5'h02:
          /* empty */;
      5'h03:
          /* empty */;
      5'h05:
          /* empty */;
      5'h06:
          /* empty */;
      5'h07:
          /* empty */;
      5'h08:
          /* empty */;
      5'h09:
          /* empty */;
      5'h0a:
          /* empty */;
      5'h0b:
          if (\$98 ) begin
          end else if (\$99 ) begin
          end else if (\$100 ) begin
            \$337  = 32'd0;
          end
    endcase
  end
  assign rx_data = 8'h00;
  assign crc_next = _cs7;
  assign code7_rev = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6] };
  assign code8_rev = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7] };
  assign code9_rev = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4], defl_bits[5], defl_bits[6], defl_bits[7], defl_bits[8] };
  assign dist5_rev = { defl_bits[0], defl_bits[1], defl_bits[2], defl_bits[3], defl_bits[4] };
  assign inflate_word = { 8'h00, byte_buf };
  assign tx_data = tx_byte;
  assign base_reg = mint_base;
  assign n_reg = mint_n;
  assign result_gt_reg = result_gt;
  assign rx_valid = 1'h0;
  
  assign \$1  = { 1'h0, crc_acc[31:1] };
  assign \$3  = { 1'h0, _cs0[31:1] };
  assign \$5  = { 1'h0, _cs1[31:1] };
  assign \$7  = { 1'h0, _cs2[31:1] };
  assign \$9  = { 1'h0, _cs3[31:1] };
  assign \$11  = { 1'h0, _cs4[31:1] };
  assign \$13  = { 1'h0, _cs5[31:1] };
  assign \$15  = { 1'h0, _cs6[31:1] };
  assign \$26  = { 1'h0, wr_word_cnt, 2'h0 };
  assign \$31  = 1'h0;
  assign \$33  = { 1'h0, wr_word_cnt, 2'h0 };
  assign \$45 [12:11] = 2'h0;
  assign \$45 [10:0] = \$44 [10:0];
  assign \$47  = { 1'h0, wr_word_cnt, 2'h0 };
  assign \$50  = { 1'h0, wr_word_cnt, 2'h0 };
  assign \$52  = \$auto$rtlil.cc:2739:Not$18 ;
  assign \$88  = { 2'h0, ucomp_size_reg[31:2] };
  assign \$109  = 1'h0;
  assign \$110  = { 3'h0, defl_bits[31:3] };
  assign \$143  = 1'h0;
  assign \$145  = { 7'h00, defl_bits[31:7] };
  assign \$153  = { 8'h00, defl_bits[31:8] };
  assign \$159  = { 8'h00, defl_bits[31:8] };
  assign \$163  = { 9'h000, defl_bits[31:9] };
  assign \$179  = 1'h0;
  assign \$183  = { 1'h0, defl_bits[31:1] };
  assign \$187  = { 2'h0, defl_bits[31:2] };
  assign \$191  = { 3'h0, defl_bits[31:3] };
  assign \$195  = { 4'h0, defl_bits[31:4] };
  assign \$199  = { 5'h00, defl_bits[31:5] };
  assign \$208  = 1'h0;
  assign \$209  = { 5'h00, defl_bits[31:5] };
  assign \$219  = 1'h0;
  assign \$223  = { 1'h0, defl_bits[31:1] };
  assign \$227  = { 2'h0, defl_bits[31:2] };
  assign \$231  = { 3'h0, defl_bits[31:3] };
  assign \$235  = { 4'h0, defl_bits[31:4] };
  assign \$239  = { 5'h00, defl_bits[31:5] };
  assign \$243  = { 6'h00, defl_bits[31:6] };
  assign \$247  = { 7'h00, defl_bits[31:7] };
  assign \$251  = { 8'h00, defl_bits[31:8] };
  assign \$255  = { 9'h000, defl_bits[31:9] };
endmodule

(* src = "/home/runner/workspace/hardware/church_outform.py:61" *)
(* generator = "Amaranth" *)
module \top.core.u_outform_fsm (clk, outform_done_in, outform_fault_in, result_gt_in, src_cr_data, outform_fault_type_in, outform_start_out, outform_gt_raw_out, outform_slot_id_out, cr_wr_en, cr_wr_addr, cr_wr_data, busy, fault, fault_type, src_cr, intercept_start);
  reg \$auto$verilog_backend.cc:2355:dump_module$61  = 0;
  wire \$1 ;
  reg [15:0] \$10 ;
  reg [2:0] \$11 ;
  reg [4:0] \$12 ;
  wire \$2 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  reg [3:0] \$7 ;
  reg [95:0] \$8 ;
  reg [31:0] \$9 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:55" *)
  output busy;
  reg busy;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] church_outform_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/church_outform.py:40" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:41" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:39" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/church_outform.py:56" *)
  reg done;
  (* src = "/home/runner/workspace/hardware/church_outform.py:57" *)
  output fault;
  reg fault;
  (* src = "/home/runner/workspace/hardware/church_outform.py:58" *)
  output [4:0] fault_type;
  reg [4:0] fault_type;
  (* src = "/home/runner/workspace/hardware/church_outform.py:68" *)
  reg [4:0] fault_type_lat = 5'h00;
  (* src = "/home/runner/workspace/hardware/church_outform.py:66" *)
  reg [31:0] gt_raw_lat = 32'd0;
  (* src = "/home/runner/workspace/hardware/church_outform.py:34" *)
  input intercept_start;
  wire intercept_start;
  (* src = "/home/runner/workspace/hardware/church_outform.py:47" *)
  wire [31:0] outform_clist_addr_out;
  (* src = "/home/runner/workspace/hardware/church_outform.py:49" *)
  input outform_done_in;
  wire outform_done_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:50" *)
  input outform_fault_in;
  wire outform_fault_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:51" *)
  input [4:0] outform_fault_type_in;
  wire [4:0] outform_fault_type_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:45" *)
  output [31:0] outform_gt_raw_out;
  reg [31:0] outform_gt_raw_out;
  (* src = "/home/runner/workspace/hardware/church_outform.py:46" *)
  output [15:0] outform_slot_id_out;
  reg [15:0] outform_slot_id_out;
  (* src = "/home/runner/workspace/hardware/church_outform.py:44" *)
  output outform_start_out;
  reg outform_start_out;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [95:0] promoted_cap;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [31:0] \promoted_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire \promoted_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire \promoted_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [8:0] \promoted_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [1:0] \promoted_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [2:0] \promoted_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [15:0] \promoted_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [31:0] \promoted_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:95" *)
  wire [31:0] \promoted_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:82" *)
  wire [31:0] promoted_gt;
  (* src = "/home/runner/workspace/hardware/church_outform.py:52" *)
  input [31:0] result_gt_in;
  wire [31:0] result_gt_in;
  (* src = "/home/runner/workspace/hardware/church_outform.py:67" *)
  reg [15:0] slot_id_lat = 16'h0000;
  (* src = "/home/runner/workspace/hardware/church_outform.py:35" *)
  input [3:0] src_cr;
  wire [3:0] src_cr;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  input [95:0] src_cr_data;
  wire [95:0] src_cr_data;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [31:0] \src_cr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire \src_cr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire \src_cr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [8:0] \src_cr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [1:0] \src_cr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [2:0] \src_cr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [15:0] \src_cr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [31:0] \src_cr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:36" *)
  wire [31:0] \src_cr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  reg [95:0] src_cr_data_lat = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire [31:0] \src_cr_data_lat.word0_gt ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire \src_cr_data_lat.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire \src_cr_data_lat.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire [8:0] \src_cr_data_lat.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire [1:0] \src_cr_data_lat.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire [2:0] \src_cr_data_lat.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire [15:0] \src_cr_data_lat.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire [31:0] \src_cr_data_lat.word1_location ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  wire [31:0] \src_cr_data_lat.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:64" *)
  reg [3:0] src_cr_lat = 4'h0;
  assign \$1  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) church_outform_state;
  assign \$2  = church_outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$3  = church_outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$4  = church_outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$5  = church_outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$6  = church_outform_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  (* src = "/home/runner/workspace/hardware/church_outform.py:64" *)
  always @(posedge clk)
    src_cr_lat <= \$7 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:65" *)
  always @(posedge clk)
    src_cr_data_lat <= \$8 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:66" *)
  always @(posedge clk)
    gt_raw_lat <= \$9 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:67" *)
  always @(posedge clk)
    slot_id_lat <= \$10 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    church_outform_state <= \$11 ;
  (* src = "/home/runner/workspace/hardware/church_outform.py:68" *)
  always @(posedge clk)
    fault_type_lat <= \$12 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    outform_start_out = 1'h0;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          outform_start_out = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    outform_gt_raw_out = gt_raw_lat;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          outform_gt_raw_out = gt_raw_lat;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    outform_slot_id_out = slot_id_lat;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          outform_slot_id_out = slot_id_lat;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    cr_wr_en = 1'h0;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    cr_wr_addr = src_cr_lat;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          cr_wr_addr = src_cr_lat;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    cr_wr_data = promoted_cap;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          cr_wr_data = promoted_cap;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    busy = 1'h0;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          busy = 1'h1;
      3'h2:
          busy = 1'h1;
      3'h4:
          busy = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    done = 1'h0;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
          done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    fault = 1'h0;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
          /* empty */;
      3'h3:
          fault = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    fault_type = 5'h00;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h4:
          /* empty */;
      3'h5:
          /* empty */;
      3'h3:
          fault_type = fault_type_lat;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    \$7  = src_cr_lat;
    casez (church_outform_state)
      3'h0:
          if (intercept_start) begin
            \$7  = src_cr;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    \$8  = src_cr_data_lat;
    casez (church_outform_state)
      3'h0:
          if (intercept_start) begin
            \$8  = src_cr_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    \$9  = gt_raw_lat;
    casez (church_outform_state)
      3'h0:
          if (intercept_start) begin
            \$9  = src_cr_data[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    \$10  = slot_id_lat;
    casez (church_outform_state)
      3'h0:
          if (intercept_start) begin
            \$10  = src_cr_data[15:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    \$11  = church_outform_state;
    casez (church_outform_state)
      3'h0:
          if (intercept_start) begin
            \$11  = 3'h1;
          end
      3'h1:
          \$11  = 3'h2;
      3'h2:
          if (outform_fault_in) begin
            \$11  = 3'h3;
          end else if (outform_done_in) begin
            \$11  = 3'h4;
          end
      3'h4:
          \$11  = 3'h5;
      3'h5:
          \$11  = 3'h0;
      3'h3:
          \$11  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$61 ) begin end
    \$12  = fault_type_lat;
    casez (church_outform_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          if (outform_fault_in) begin
            \$12  = outform_fault_type_in;
          end
    endcase
  end
  assign outform_clist_addr_out = 32'd0;
  
  assign \src_cr_data_lat.word0_gt  = src_cr_data_lat[31:0];
  assign \src_cr_data_lat.word0_gt.slot_id  = src_cr_data_lat[15:0];
  assign \src_cr_data_lat.word0_gt.gt_seq  = src_cr_data_lat[24:16];
  assign \src_cr_data_lat.word0_gt.gt_type  = src_cr_data_lat[26:25];
  assign \src_cr_data_lat.word0_gt.dom  = src_cr_data_lat[27];
  assign \src_cr_data_lat.word0_gt.perm  = src_cr_data_lat[30:28];
  assign \src_cr_data_lat.word0_gt.b_flag  = src_cr_data_lat[31];
  assign \src_cr_data_lat.word1_location  = src_cr_data_lat[63:32];
  assign \src_cr_data_lat.word2_w2  = src_cr_data_lat[95:64];
  assign \promoted_cap.word0_gt  = promoted_cap[31:0];
  assign \promoted_cap.word0_gt.slot_id  = promoted_cap[15:0];
  assign \promoted_cap.word0_gt.gt_seq  = promoted_cap[24:16];
  assign \promoted_cap.word0_gt.gt_type  = promoted_cap[26:25];
  assign \promoted_cap.word0_gt.dom  = promoted_cap[27];
  assign \promoted_cap.word0_gt.perm  = promoted_cap[30:28];
  assign \promoted_cap.word0_gt.b_flag  = promoted_cap[31];
  assign \promoted_cap.word1_location  = promoted_cap[63:32];
  assign \promoted_cap.word2_w2  = promoted_cap[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \src_cr_data.word0_gt  = src_cr_data[31:0];
  assign \src_cr_data.word0_gt.slot_id  = src_cr_data[15:0];
  assign \src_cr_data.word0_gt.gt_seq  = src_cr_data[24:16];
  assign \src_cr_data.word0_gt.gt_type  = src_cr_data[26:25];
  assign \src_cr_data.word0_gt.dom  = src_cr_data[27];
  assign \src_cr_data.word0_gt.perm  = src_cr_data[30:28];
  assign \src_cr_data.word0_gt.b_flag  = src_cr_data[31];
  assign \src_cr_data.word1_location  = src_cr_data[63:32];
  assign \src_cr_data.word2_w2  = src_cr_data[95:64];
  assign promoted_cap[95:64] = src_cr_data_lat[95:64];
  assign promoted_cap[63:32] = src_cr_data_lat[63:32];
  assign promoted_cap[31:0] = promoted_gt;
  assign promoted_gt[31] = src_cr_data_lat[31];
  assign promoted_gt[30:28] = src_cr_data_lat[30:28];
  assign promoted_gt[27] = src_cr_data_lat[27];
  assign promoted_gt[26:25] = 2'h1;
  assign promoted_gt[24:16] = result_gt_in[24:16];
  assign promoted_gt[15:0] = src_cr_data_lat[15:0];
endmodule

(* src = "/home/runner/workspace/hardware/perm_check.py:62" *)
(* generator = "Amaranth" *)
module \top.core.u_perm_check (gt_in, required_perms, fault_valid, fault_type, check_valid);
  reg \$auto$verilog_backend.cc:2355:dump_module$62  = 0;
  wire [5:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire [5:0] \$18 ;
  wire [5:0] \$19 ;
  wire \$2 ;
  wire [5:0] \$20 ;
  wire [5:0] \$21 ;
  wire \$22 ;
  wire [5:0] \$23 ;
  wire [5:0] \$24 ;
  wire [5:0] \$25 ;
  wire [5:0] \$26 ;
  wire \$27 ;
  wire [5:0] \$28 ;
  wire [5:0] \$29 ;
  wire \$3 ;
  wire [5:0] \$30 ;
  wire [5:0] \$31 ;
  wire \$32 ;
  wire [5:0] \$33 ;
  wire [5:0] \$34 ;
  wire [5:0] \$35 ;
  wire [5:0] \$36 ;
  wire \$37 ;
  wire [5:0] \$38 ;
  wire [5:0] \$39 ;
  wire \$4 ;
  wire [5:0] \$40 ;
  wire [5:0] \$41 ;
  wire \$42 ;
  wire [5:0] \$43 ;
  wire [5:0] \$44 ;
  wire [5:0] \$45 ;
  wire [5:0] \$46 ;
  wire \$47 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:38" *)
  wire [15:0] access_index;
  (* src = "/home/runner/workspace/hardware/perm_check.py:54" *)
  wire all_checks_pass;
  (* src = "/home/runner/workspace/hardware/perm_check.py:51" *)
  wire bounds_ok;
  (* src = "/home/runner/workspace/hardware/perm_check.py:46" *)
  wire [15:0] calculated_seal;
  (* src = "/home/runner/workspace/hardware/perm_check.py:40" *)
  wire check_bounds;
  (* src = "/home/runner/workspace/hardware/perm_check.py:48" *)
  wire check_seal;
  (* src = "/home/runner/workspace/hardware/perm_check.py:36" *)
  input check_valid;
  wire check_valid;
  (* src = "/home/runner/workspace/hardware/perm_check.py:44" *)
  wire check_version;
  (* src = "/home/runner/workspace/hardware/perm_check.py:59" *)
  wire domain_purity_ok;
  (* src = "/home/runner/workspace/hardware/perm_check.py:55" *)
  output [3:0] fault_type;
  reg [3:0] fault_type;
  (* src = "/home/runner/workspace/hardware/perm_check.py:56" *)
  output fault_valid;
  reg fault_valid;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  input [31:0] gt_in;
  wire [31:0] gt_in;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire \gt_in.b_flag ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire \gt_in.dom ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [8:0] \gt_in.gt_seq ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [1:0] \gt_in.gt_type ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [2:0] \gt_in.perm ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:34" *)
  wire [15:0] \gt_in.slot_id ;
  (* src = "/home/runner/workspace/hardware/perm_check.py:72" *)
  wire [5:0] gt_perms;
  (* src = "/home/runner/workspace/hardware/perm_check.py:43" *)
  wire [6:0] gt_seq;
  (* src = "/home/runner/workspace/hardware/perm_check.py:80" *)
  wire is_null_gt;
  (* src = "/home/runner/workspace/hardware/perm_check.py:39" *)
  wire [31:0] limit;
  (* src = "/home/runner/workspace/hardware/perm_check.py:50" *)
  wire perm_granted;
  (* src = "/home/runner/workspace/hardware/perm_check.py:81" *)
  wire perms_match;
  (* src = "/home/runner/workspace/hardware/perm_check.py:35" *)
  input [5:0] required_perms;
  wire [5:0] required_perms;
  (* src = "/home/runner/workspace/hardware/perm_check.py:53" *)
  wire seal_valid;
  (* src = "/home/runner/workspace/hardware/perm_check.py:42" *)
  wire [6:0] stored_gt_seq;
  (* src = "/home/runner/workspace/hardware/perm_check.py:47" *)
  wire [15:0] stored_seal;
  (* src = "/home/runner/workspace/hardware/perm_check.py:52" *)
  wire version_ok;
  assign \$45  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:124" *) \$44 ;
  assign \$46  = \$43  & (* src = "/home/runner/workspace/hardware/perm_check.py:124" *) \$45 ;
  assign \$47  = | (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:551" *) \$46 ;
  assign gt_perms = gt_in[27] ? (* src = "/home/runner/workspace/hardware/perm_check.py:74" *) { gt_in[30:28], 3'h0 } : { 3'h0, gt_in[30:28] };
  assign is_null_gt = ! (* src = "/home/runner/workspace/hardware/perm_check.py:84" *) gt_in[26:25];
  assign \$1  = gt_perms & (* src = "/home/runner/workspace/hardware/perm_check.py:85" *) required_perms;
  assign perms_match = \$1  == (* src = "/home/runner/workspace/hardware/perm_check.py:85" *) required_perms;
  assign \$2  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:86" *) is_null_gt;
  assign perm_granted = \$2  & (* src = "/home/runner/workspace/hardware/perm_check.py:86" *) perms_match;
  assign \$11  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:112" *) perms_match;
  assign \$20  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:114" *) \$19 ;
  assign \$21  = \$18  & (* src = "/home/runner/workspace/hardware/perm_check.py:114" *) \$20 ;
  assign \$22  = | (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:551" *) \$21 ;
  assign \$25  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:116" *) \$24 ;
  assign \$26  = \$23  & (* src = "/home/runner/workspace/hardware/perm_check.py:116" *) \$25 ;
  assign \$27  = | (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:551" *) \$26 ;
  assign \$30  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:118" *) \$29 ;
  assign \$31  = \$28  & (* src = "/home/runner/workspace/hardware/perm_check.py:118" *) \$30 ;
  assign \$32  = | (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:551" *) \$31 ;
  assign \$35  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:120" *) \$34 ;
  assign \$36  = \$33  & (* src = "/home/runner/workspace/hardware/perm_check.py:120" *) \$35 ;
  assign \$37  = | (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:551" *) \$36 ;
  assign \$40  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:122" *) \$39 ;
  assign \$41  = \$38  & (* src = "/home/runner/workspace/hardware/perm_check.py:122" *) \$40 ;
  assign \$42  = | (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:551" *) \$41 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$62 ) begin end
    fault_valid = 1'h0;
    if (check_valid) begin
      if (is_null_gt) begin
        fault_valid = 1'h1;
      end else if (\$11 ) begin
        fault_valid = 1'h1;
      end else if (\$13 ) begin
        fault_valid = 1'h1;
      end else if (\$15 ) begin
        fault_valid = 1'h1;
      end else if (\$17 ) begin
        fault_valid = 1'h1;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$62 ) begin end
    fault_type = 4'h0;
    if (check_valid) begin
      if (is_null_gt) begin
        fault_type = 4'h7;
      end else if (\$11 ) begin
        (* full_case = 32'd1 *)
        if (\$22 ) begin
          fault_type = 4'h1;
        end else if (\$27 ) begin
          fault_type = 4'h2;
        end else if (\$32 ) begin
          fault_type = 4'h3;
        end else if (\$37 ) begin
          fault_type = 4'h4;
        end else if (\$42 ) begin
          fault_type = 4'h5;
        end else if (\$47 ) begin
          fault_type = 4'h6;
        end else begin
          fault_type = 4'h1;
        end
      end else if (\$13 ) begin
        fault_type = 4'h8;
      end else if (\$15 ) begin
        fault_type = 4'h9;
      end else if (\$17 ) begin
        fault_type = 4'ha;
      end
    end
  end
  assign domain_purity_ok = 1'h1;
  assign check_bounds = 1'h0;
  assign access_index = 16'h0000;
  assign limit = 32'd0;
  assign check_version = 1'h0;
  assign gt_seq = 7'h00;
  assign stored_gt_seq = 7'h00;
  assign check_seal = 1'h0;
  assign calculated_seal = 16'h0000;
  assign stored_seal = 16'h0000;
  assign \gt_in.slot_id  = gt_in[15:0];
  assign \gt_in.gt_seq  = gt_in[24:16];
  assign \gt_in.gt_type  = gt_in[26:25];
  assign \gt_in.dom  = gt_in[27];
  assign \gt_in.perm  = gt_in[30:28];
  assign \gt_in.b_flag  = gt_in[31];
  assign \$3  = 1'h1;
  assign \$4  = 1'h0;
  assign bounds_ok = 1'h1;
  assign \$5  = 1'h1;
  assign \$6  = 1'h1;
  assign version_ok = 1'h1;
  assign \$7  = 1'h1;
  assign \$8  = 1'h1;
  assign seal_valid = 1'h1;
  assign \$9  = perm_granted;
  assign \$10  = perm_granted;
  assign all_checks_pass = perm_granted;
  assign \$12  = 1'h0;
  assign \$13  = 1'h0;
  assign \$14  = 1'h0;
  assign \$15  = 1'h0;
  assign \$16  = 1'h0;
  assign \$17  = 1'h0;
  assign \$18 [5:1] = 5'h00;
  assign \$18 [0] = required_perms[0];
  assign \$19 [5:1] = 5'h00;
  assign \$19 [0] = gt_perms[0];
  assign { \$23 [5:2], \$23 [0] } = 5'h00;
  assign \$23 [1] = required_perms[1];
  assign { \$24 [5:2], \$24 [0] } = 5'h00;
  assign \$24 [1] = gt_perms[1];
  assign { \$28 [5:3], \$28 [1:0] } = 5'h00;
  assign \$28 [2] = required_perms[2];
  assign { \$29 [5:3], \$29 [1:0] } = 5'h00;
  assign \$29 [2] = gt_perms[2];
  assign { \$33 [5:4], \$33 [2:0] } = 5'h00;
  assign \$33 [3] = required_perms[3];
  assign { \$34 [5:4], \$34 [2:0] } = 5'h00;
  assign \$34 [3] = gt_perms[3];
  assign { \$38 [5], \$38 [3:0] } = 5'h00;
  assign \$38 [4] = required_perms[4];
  assign { \$39 [5], \$39 [3:0] } = 5'h00;
  assign \$39 [4] = gt_perms[4];
  assign \$43 [4:0] = 5'h00;
  assign \$43 [5] = required_perms[5];
  assign \$44 [4:0] = 5'h00;
  assign \$44 [5] = gt_perms[5];
endmodule

(* src = "/home/runner/workspace/hardware/pet_name_mem.py:79" *)
(* generator = "Amaranth" *)
module \top.core.u_pet_name_mem (clk, rd_data, wr_en, wr_addr, wr_data, rd_addr);
  reg \$auto$verilog_backend.cc:2355:dump_module$63  = 0;
  reg \$1 ;
  reg \$10 ;
  reg \$11 ;
  reg \$12 ;
  reg \$13 ;
  reg \$14 ;
  reg \$15 ;
  reg \$16 ;
  reg \$17 ;
  reg \$18 ;
  reg \$19 ;
  wire \$2 ;
  reg \$20 ;
  reg \$21 ;
  reg \$22 ;
  reg \$23 ;
  reg \$24 ;
  reg \$25 ;
  reg \$26 ;
  reg \$27 ;
  reg \$28 ;
  reg \$29 ;
  wire \$3 ;
  reg \$30 ;
  reg \$31 ;
  reg \$32 ;
  reg \$33 ;
  reg \$34 ;
  reg \$35 ;
  reg \$36 ;
  reg \$37 ;
  reg \$38 ;
  reg \$39 ;
  reg \$4 ;
  reg \$40 ;
  reg \$41 ;
  reg \$42 ;
  reg \$43 ;
  reg \$44 ;
  reg \$45 ;
  reg \$46 ;
  reg \$47 ;
  reg \$48 ;
  reg \$49 ;
  reg \$5 ;
  reg \$50 ;
  reg \$51 ;
  reg \$52 ;
  reg \$53 ;
  reg \$54 ;
  reg \$55 ;
  reg \$56 ;
  reg \$57 ;
  reg \$58 ;
  reg \$59 ;
  reg \$6 ;
  reg \$60 ;
  reg \$61 ;
  reg \$62 ;
  reg \$63 ;
  reg \$64 ;
  reg \$65 ;
  reg \$66 ;
  reg \$67 ;
  reg \$7 ;
  reg \$8 ;
  reg \$9 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:86" *)
  wire in_range;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_0 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_1 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_10 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_11 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_12 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_13 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_14 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_15 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_16 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_17 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_18 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_19 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_2 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_20 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_21 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_22 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_23 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_24 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_25 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_26 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_27 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_28 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_29 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_3 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_30 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_31 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_32 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_33 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_34 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_35 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_36 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_37 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_38 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_39 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_4 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_40 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_41 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_42 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_43 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_44 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_45 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_46 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_47 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_48 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_49 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_5 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_50 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_51 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_52 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_53 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_54 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_55 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_56 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_57 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_58 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_59 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_6 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_60 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_61 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_62 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_63 = 1'h0;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_7 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_8 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  reg pn_9 = 1'h1;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:71" *)
  input [15:0] rd_addr;
  wire [15:0] rd_addr;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:72" *)
  output rd_data;
  wire rd_data;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:75" *)
  input [5:0] wr_addr;
  wire [5:0] wr_addr;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:76" *)
  input wr_data;
  wire wr_data;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:74" *)
  input wr_en;
  wire wr_en;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_13 <= \$17 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_14 <= \$18 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_15 <= \$19 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_16 <= \$20 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_17 <= \$21 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_18 <= \$22 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_19 <= \$23 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_20 <= \$24 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_21 <= \$25 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_22 <= \$26 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_23 <= \$27 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_24 <= \$28 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_25 <= \$29 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_26 <= \$30 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_27 <= \$31 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_28 <= \$32 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_29 <= \$33 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_30 <= \$34 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_31 <= \$35 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_32 <= \$36 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_33 <= \$37 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_34 <= \$38 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_35 <= \$39 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_36 <= \$40 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_37 <= \$41 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_38 <= \$42 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_39 <= \$43 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_40 <= \$44 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_41 <= \$45 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_42 <= \$46 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_43 <= \$47 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_44 <= \$48 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_45 <= \$49 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_46 <= \$50 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_47 <= \$51 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_48 <= \$52 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_49 <= \$53 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_50 <= \$54 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_51 <= \$55 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_52 <= \$56 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_53 <= \$57 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_54 <= \$58 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_55 <= \$59 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_56 <= \$60 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_57 <= \$61 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_58 <= \$62 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_59 <= \$63 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_60 <= \$64 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_61 <= \$65 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_62 <= \$66 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_63 <= \$67 ;
  assign in_range = rd_addr < (* src = "/home/runner/workspace/hardware/pet_name_mem.py:87" *) 7'h40;
  assign rd_data = in_range ? (* src = "/home/runner/workspace/hardware/pet_name_mem.py:90" *) \$1  : 1'h0;
  assign \$2  = wr_addr < (* src = "/home/runner/workspace/hardware/pet_name_mem.py:93" *) 7'h40;
  assign \$3  = wr_en & (* src = "/home/runner/workspace/hardware/pet_name_mem.py:93" *) \$2 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_0 <= \$4 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_1 <= \$5 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_2 <= \$6 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_3 <= \$7 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_4 <= \$8 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_5 <= \$9 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_6 <= \$10 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_7 <= \$11 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_8 <= \$12 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_9 <= \$13 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_10 <= \$14 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_11 <= \$15 ;
  (* src = "/home/runner/workspace/hardware/pet_name_mem.py:82" *)
  always @(posedge clk)
    pn_12 <= \$16 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$18  = pn_14;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            \$18  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$19  = pn_15;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            \$19  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$20  = pn_16;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            \$20  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$21  = pn_17;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            \$21  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$22  = pn_18;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            \$22  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$23  = pn_19;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            \$23  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$24  = pn_20;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            \$24  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$25  = pn_21;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            \$25  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$26  = pn_22;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            \$26  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$27  = pn_23;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            \$27  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$28  = pn_24;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            \$28  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$29  = pn_25;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            \$29  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$30  = pn_26;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            \$30  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$31  = pn_27;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            \$31  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$32  = pn_28;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            \$32  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$33  = pn_29;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            \$33  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$34  = pn_30;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            \$34  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$35  = pn_31;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            \$35  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$36  = pn_32;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            \$36  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$37  = pn_33;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            \$37  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$38  = pn_34;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            \$38  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$39  = pn_35;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            \$39  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$40  = pn_36;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            \$40  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$41  = pn_37;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            \$41  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$42  = pn_38;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            \$42  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$43  = pn_39;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            \$43  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$44  = pn_40;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            \$44  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$45  = pn_41;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            \$45  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$46  = pn_42;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            \$46  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$47  = pn_43;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            \$47  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$48  = pn_44;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            \$48  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$49  = pn_45;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            \$49  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$50  = pn_46;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            \$50  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$51  = pn_47;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            \$51  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$52  = pn_48;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            \$52  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$53  = pn_49;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            \$53  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$54  = pn_50;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            \$54  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$55  = pn_51;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            \$55  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$56  = pn_52;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            \$56  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$57  = pn_53;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            \$57  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$58  = pn_54;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            \$58  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$59  = pn_55;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            \$59  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$60  = pn_56;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            \$60  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$61  = pn_57;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            /* empty */;
        6'h39:
            \$61  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$62  = pn_58;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            /* empty */;
        6'h39:
            /* empty */;
        6'h3a:
            \$62  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$63  = pn_59;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            /* empty */;
        6'h39:
            /* empty */;
        6'h3a:
            /* empty */;
        6'h3b:
            \$63  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$64  = pn_60;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            /* empty */;
        6'h39:
            /* empty */;
        6'h3a:
            /* empty */;
        6'h3b:
            /* empty */;
        6'h3c:
            \$64  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$65  = pn_61;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            /* empty */;
        6'h39:
            /* empty */;
        6'h3a:
            /* empty */;
        6'h3b:
            /* empty */;
        6'h3c:
            /* empty */;
        6'h3d:
            \$65  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$66  = pn_62;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            /* empty */;
        6'h39:
            /* empty */;
        6'h3a:
            /* empty */;
        6'h3b:
            /* empty */;
        6'h3c:
            /* empty */;
        6'h3d:
            /* empty */;
        6'h3e:
            \$66  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$67  = pn_63;
    if (\$3 ) begin
      (* full_case = 32'd1 *)
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            /* empty */;
        6'h0e:
            /* empty */;
        6'h0f:
            /* empty */;
        6'h10:
            /* empty */;
        6'h11:
            /* empty */;
        6'h12:
            /* empty */;
        6'h13:
            /* empty */;
        6'h14:
            /* empty */;
        6'h15:
            /* empty */;
        6'h16:
            /* empty */;
        6'h17:
            /* empty */;
        6'h18:
            /* empty */;
        6'h19:
            /* empty */;
        6'h1a:
            /* empty */;
        6'h1b:
            /* empty */;
        6'h1c:
            /* empty */;
        6'h1d:
            /* empty */;
        6'h1e:
            /* empty */;
        6'h1f:
            /* empty */;
        6'h20:
            /* empty */;
        6'h21:
            /* empty */;
        6'h22:
            /* empty */;
        6'h23:
            /* empty */;
        6'h24:
            /* empty */;
        6'h25:
            /* empty */;
        6'h26:
            /* empty */;
        6'h27:
            /* empty */;
        6'h28:
            /* empty */;
        6'h29:
            /* empty */;
        6'h2a:
            /* empty */;
        6'h2b:
            /* empty */;
        6'h2c:
            /* empty */;
        6'h2d:
            /* empty */;
        6'h2e:
            /* empty */;
        6'h2f:
            /* empty */;
        6'h30:
            /* empty */;
        6'h31:
            /* empty */;
        6'h32:
            /* empty */;
        6'h33:
            /* empty */;
        6'h34:
            /* empty */;
        6'h35:
            /* empty */;
        6'h36:
            /* empty */;
        6'h37:
            /* empty */;
        6'h38:
            /* empty */;
        6'h39:
            /* empty */;
        6'h3a:
            /* empty */;
        6'h3b:
            /* empty */;
        6'h3c:
            /* empty */;
        6'h3d:
            /* empty */;
        6'h3e:
            /* empty */;
        6'h3f:
            \$67  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    (* full_case = 32'd1 *)
    casez (rd_addr[5:0])
      6'h00:
          \$1  = pn_0;
      6'h01:
          \$1  = pn_1;
      6'h02:
          \$1  = pn_2;
      6'h03:
          \$1  = pn_3;
      6'h04:
          \$1  = pn_4;
      6'h05:
          \$1  = pn_5;
      6'h06:
          \$1  = pn_6;
      6'h07:
          \$1  = pn_7;
      6'h08:
          \$1  = pn_8;
      6'h09:
          \$1  = pn_9;
      6'h0a:
          \$1  = pn_10;
      6'h0b:
          \$1  = pn_11;
      6'h0c:
          \$1  = pn_12;
      6'h0d:
          \$1  = pn_13;
      6'h0e:
          \$1  = pn_14;
      6'h0f:
          \$1  = pn_15;
      6'h10:
          \$1  = pn_16;
      6'h11:
          \$1  = pn_17;
      6'h12:
          \$1  = pn_18;
      6'h13:
          \$1  = pn_19;
      6'h14:
          \$1  = pn_20;
      6'h15:
          \$1  = pn_21;
      6'h16:
          \$1  = pn_22;
      6'h17:
          \$1  = pn_23;
      6'h18:
          \$1  = pn_24;
      6'h19:
          \$1  = pn_25;
      6'h1a:
          \$1  = pn_26;
      6'h1b:
          \$1  = pn_27;
      6'h1c:
          \$1  = pn_28;
      6'h1d:
          \$1  = pn_29;
      6'h1e:
          \$1  = pn_30;
      6'h1f:
          \$1  = pn_31;
      6'h20:
          \$1  = pn_32;
      6'h21:
          \$1  = pn_33;
      6'h22:
          \$1  = pn_34;
      6'h23:
          \$1  = pn_35;
      6'h24:
          \$1  = pn_36;
      6'h25:
          \$1  = pn_37;
      6'h26:
          \$1  = pn_38;
      6'h27:
          \$1  = pn_39;
      6'h28:
          \$1  = pn_40;
      6'h29:
          \$1  = pn_41;
      6'h2a:
          \$1  = pn_42;
      6'h2b:
          \$1  = pn_43;
      6'h2c:
          \$1  = pn_44;
      6'h2d:
          \$1  = pn_45;
      6'h2e:
          \$1  = pn_46;
      6'h2f:
          \$1  = pn_47;
      6'h30:
          \$1  = pn_48;
      6'h31:
          \$1  = pn_49;
      6'h32:
          \$1  = pn_50;
      6'h33:
          \$1  = pn_51;
      6'h34:
          \$1  = pn_52;
      6'h35:
          \$1  = pn_53;
      6'h36:
          \$1  = pn_54;
      6'h37:
          \$1  = pn_55;
      6'h38:
          \$1  = pn_56;
      6'h39:
          \$1  = pn_57;
      6'h3a:
          \$1  = pn_58;
      6'h3b:
          \$1  = pn_59;
      6'h3c:
          \$1  = pn_60;
      6'h3d:
          \$1  = pn_61;
      6'h3e:
          \$1  = pn_62;
      6'h3f:
          \$1  = pn_63;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$4  = pn_0;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            \$4  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$5  = pn_1;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            \$5  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$6  = pn_2;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            \$6  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$7  = pn_3;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            \$7  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$8  = pn_4;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            \$8  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$9  = pn_5;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            \$9  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$10  = pn_6;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            \$10  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$11  = pn_7;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            \$11  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$12  = pn_8;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            \$12  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$13  = pn_9;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            \$13  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$14  = pn_10;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            \$14  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$15  = pn_11;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            \$15  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$16  = pn_12;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            \$16  = wr_data;
      endcase
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$63 ) begin end
    \$17  = pn_13;
    if (\$3 ) begin
      casez (wr_addr)
        6'h00:
            /* empty */;
        6'h01:
            /* empty */;
        6'h02:
            /* empty */;
        6'h03:
            /* empty */;
        6'h04:
            /* empty */;
        6'h05:
            /* empty */;
        6'h06:
            /* empty */;
        6'h07:
            /* empty */;
        6'h08:
            /* empty */;
        6'h09:
            /* empty */;
        6'h0a:
            /* empty */;
        6'h0b:
            /* empty */;
        6'h0c:
            /* empty */;
        6'h0d:
            \$17  = wr_data;
      endcase
    end
  end
  
endmodule

(* src = "/home/runner/workspace/hardware/registers.py:99" *)
(* generator = "Amaranth" *)
module \top.core.u_registers (clk, cr_rd_addr, cr_wr_addr, cr_wr_data, cr_wr_en, m_set_dr11, m_set_dr12, m_set_dr13, m_set_dr14, m_set_dr15, cr0_gt_wr_en, cr0_gt_wr_data, cr1_gt_wr_en, cr1_gt_wr_data, cr2_gt_wr_en, cr2_gt_wr_data, cr3_gt_wr_en, cr3_gt_wr_data, cr4_gt_wr_en, cr4_gt_wr_data, cr5_gt_wr_en, cr5_gt_wr_data
, cr6_gt_wr_en, cr6_gt_wr_data, cr7_gt_wr_en, cr7_gt_wr_data, cr8_gt_wr_en, cr8_gt_wr_data, cr9_gt_wr_en, cr9_gt_wr_data, cr10_gt_wr_en, cr10_gt_wr_data, cr11_gt_wr_en, cr11_gt_wr_data, cr12_gt_wr_en, cr12_gt_wr_data, cr13_gt_wr_en, cr13_gt_wr_data, cr14_gt_wr_en, cr14_gt_wr_data, cr15_gt_wr_en, cr15_gt_wr_data, dr_rd_addr2
, dr_rd_addr1, cr_rd_data, dr_rd_data1, dr_rd_data2, flags_in, flags_wr_en, dr_wr_addr, dr_wr_data, dr_wr_en, m_set_en, m_clear_en, cr5, cr12, cr14, cr15, m_dr11, m_dr12, m_dr13, m_dr14, m_dr15, flags
, cr15_m_flag, cr_null_mask, cr_b_clear_mask, m_flag_restore_en, m_flag_restore_val, clear_all);
  reg \$auto$verilog_backend.cc:2355:dump_module$64  = 0;
  wire [95:0] \$1 ;
  reg [95:0] \$10 ;
  reg [95:0] \$11 ;
  reg [95:0] \$12 ;
  reg [95:0] \$13 ;
  reg [95:0] \$14 ;
  reg [95:0] \$15 ;
  reg [95:0] \$16 ;
  reg [95:0] \$17 ;
  reg [95:0] \$18 ;
  reg [95:0] \$19 ;
  wire [95:0] \$2 ;
  reg [95:0] \$20 ;
  reg [95:0] \$21 ;
  reg [95:0] \$22 ;
  reg [95:0] \$23 ;
  reg [95:0] \$24 ;
  reg [95:0] \$25 ;
  reg [31:0] \$26 ;
  reg [31:0] \$27 ;
  reg [31:0] \$28 ;
  reg [31:0] \$29 ;
  wire [95:0] \$3 ;
  reg [31:0] \$30 ;
  reg [31:0] \$31 ;
  reg [31:0] \$32 ;
  reg [31:0] \$33 ;
  reg [31:0] \$34 ;
  reg [31:0] \$35 ;
  reg [31:0] \$36 ;
  reg [31:0] \$37 ;
  reg [31:0] \$38 ;
  reg [31:0] \$39 ;
  wire \$4 ;
  reg [31:0] \$40 ;
  reg [31:0] \$41 ;
  reg [3:0] \$42 ;
  reg \$43 ;
  reg [31:0] \$5 ;
  wire \$6 ;
  reg [31:0] \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/registers.py:58" *)
  input clear_all;
  wire clear_all;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr0 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr0.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr0.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr0.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr0.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr0.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr0.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr0.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr0.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr0.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr0_gt_wr_data;
  wire [31:0] cr0_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr0_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr0_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr0_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr0_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr0_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr0_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr0_gt_wr_en;
  wire cr0_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr1 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr1.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr1.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr1.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr1.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr1.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr1.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr1.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr1.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr1.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr10 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr10.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr10.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr10.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr10.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr10.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr10.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr10.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr10.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr10.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr10_gt_wr_data;
  wire [31:0] cr10_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr10_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr10_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr10_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr10_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr10_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr10_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr10_gt_wr_en;
  wire cr10_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr11 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr11.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr11.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr11.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr11.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr11.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr11.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr11.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr11.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr11.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr11_gt_wr_data;
  wire [31:0] cr11_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr11_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr11_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr11_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr11_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr11_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr11_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr11_gt_wr_en;
  wire cr11_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  output [95:0] cr12;
  reg [95:0] cr12 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr12.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr12.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr12.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr12.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr12.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr12.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr12.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr12.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr12.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr12_gt_wr_data;
  wire [31:0] cr12_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr12_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr12_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr12_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr12_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr12_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr12_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr12_gt_wr_en;
  wire cr12_gt_wr_en;
  (* init = 96'h000000000000000000000000 *)
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [95:0] cr12_thread;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [31:0] \cr12_thread.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire \cr12_thread.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire \cr12_thread.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [8:0] \cr12_thread.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [1:0] \cr12_thread.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [2:0] \cr12_thread.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [15:0] \cr12_thread.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [31:0] \cr12_thread.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:38" *)
  wire [31:0] \cr12_thread.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr13 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr13.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr13.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr13.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr13.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr13.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr13.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr13.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr13.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr13.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr13_gt_wr_data;
  wire [31:0] cr13_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr13_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr13_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr13_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr13_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr13_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr13_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr13_gt_wr_en;
  wire cr13_gt_wr_en;
  (* init = 96'h000000000000000000000000 *)
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [95:0] cr13_interrupt;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [31:0] \cr13_interrupt.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire \cr13_interrupt.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire \cr13_interrupt.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [8:0] \cr13_interrupt.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [1:0] \cr13_interrupt.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [2:0] \cr13_interrupt.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [15:0] \cr13_interrupt.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [31:0] \cr13_interrupt.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:39" *)
  wire [31:0] \cr13_interrupt.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  output [95:0] cr14;
  reg [95:0] cr14 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr14.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr14.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr14.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr14.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr14.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr14.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr14.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr14.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr14.word2_w2 ;
  (* init = 96'h000000000000000000000000 *)
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [95:0] cr14_code;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [31:0] \cr14_code.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire \cr14_code.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire \cr14_code.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [8:0] \cr14_code.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [1:0] \cr14_code.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [2:0] \cr14_code.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [15:0] \cr14_code.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [31:0] \cr14_code.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:40" *)
  wire [31:0] \cr14_code.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr14_gt_wr_data;
  wire [31:0] cr14_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr14_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr14_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr14_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr14_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr14_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr14_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr14_gt_wr_en;
  wire cr14_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  output [95:0] cr15;
  reg [95:0] cr15 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr15.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr15.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr15.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr15.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr15.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr15.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr15.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr15.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr15.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr15_gt_wr_data;
  wire [31:0] cr15_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr15_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr15_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr15_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr15_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr15_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr15_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr15_gt_wr_en;
  wire cr15_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:106" *)
  output cr15_m_flag;
  reg cr15_m_flag = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/registers.py:106" *)
  wire cr15_m_reg;
  (* init = 96'h000000000000000000000000 *)
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:41" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr1_gt_wr_data;
  wire [31:0] cr1_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr1_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr1_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr1_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr1_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr1_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr1_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr1_gt_wr_en;
  wire cr1_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr2 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr2.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr2.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr2.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr2.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr2.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr2.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr2.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr2.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr2.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr2_gt_wr_data;
  wire [31:0] cr2_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr2_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr2_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr2_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr2_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr2_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr2_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr2_gt_wr_en;
  wire cr2_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr3 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr3.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr3.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr3.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr3.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr3.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr3.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr3.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr3.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr3.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr3_gt_wr_data;
  wire [31:0] cr3_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr3_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr3_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr3_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr3_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr3_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr3_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr3_gt_wr_en;
  wire cr3_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr4 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr4.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr4.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr4.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr4.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr4.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr4.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr4.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr4.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr4.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr4_gt_wr_data;
  wire [31:0] cr4_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr4_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr4_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr4_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr4_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr4_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr4_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr4_gt_wr_en;
  wire cr4_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  output [95:0] cr5;
  reg [95:0] cr5 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr5.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr5.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr5.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr5.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr5.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr5.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr5.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr5.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr5.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr5_gt_wr_data;
  wire [31:0] cr5_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr5_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr5_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr5_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr5_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr5_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr5_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr5_gt_wr_en;
  wire cr5_gt_wr_en;
  (* init = 96'h000000000000000000000000 *)
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [95:0] cr5_heap;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [31:0] \cr5_heap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire \cr5_heap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire \cr5_heap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [8:0] \cr5_heap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [1:0] \cr5_heap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [2:0] \cr5_heap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [15:0] \cr5_heap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [31:0] \cr5_heap.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:36" *)
  wire [31:0] \cr5_heap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr6 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr6.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr6.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr6.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr6.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr6.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr6.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr6.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr6.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr6.word2_w2 ;
  (* init = 96'h000000000000000000000000 *)
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [95:0] cr6_clist;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [31:0] \cr6_clist.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire \cr6_clist.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire \cr6_clist.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [8:0] \cr6_clist.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [1:0] \cr6_clist.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [2:0] \cr6_clist.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [15:0] \cr6_clist.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [31:0] \cr6_clist.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:37" *)
  wire [31:0] \cr6_clist.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr6_gt_wr_data;
  wire [31:0] cr6_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr6_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr6_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr6_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr6_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr6_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr6_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr6_gt_wr_en;
  wire cr6_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr7 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr7.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr7.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr7.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr7.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr7.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr7.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr7.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr7.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr7.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr7_gt_wr_data;
  wire [31:0] cr7_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr7_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr7_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr7_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr7_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr7_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr7_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr7_gt_wr_en;
  wire cr7_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr8 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr8.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr8.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr8.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr8.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr8.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr8.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr8.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr8.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr8.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr8_gt_wr_data;
  wire [31:0] cr8_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr8_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr8_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr8_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr8_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr8_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr8_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr8_gt_wr_en;
  wire cr8_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  reg [95:0] cr9 = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr9.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr9.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire \cr9.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [8:0] \cr9.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [1:0] \cr9.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [2:0] \cr9.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [15:0] \cr9.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr9.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  wire [31:0] \cr9.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  input [31:0] cr9_gt_wr_data;
  wire [31:0] cr9_gt_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr9_gt_wr_data.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire \cr9_gt_wr_data.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [8:0] \cr9_gt_wr_data.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [1:0] \cr9_gt_wr_data.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [2:0] \cr9_gt_wr_data.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:43" *)
  wire [15:0] \cr9_gt_wr_data.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:44" *)
  input cr9_gt_wr_en;
  wire cr9_gt_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:64" *)
  input [11:0] cr_b_clear_mask;
  wire [11:0] cr_b_clear_mask;
  (* src = "/home/runner/workspace/hardware/registers.py:65" *)
  input [11:0] cr_null_mask;
  wire [11:0] cr_null_mask;
  (* src = "/home/runner/workspace/hardware/registers.py:20" *)
  input [3:0] cr_rd_addr;
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  output [95:0] cr_rd_data;
  reg [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:21" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:32" *)
  wire [3:0] cr_word_rd_addr;
  (* src = "/home/runner/workspace/hardware/registers.py:34" *)
  wire [31:0] cr_word_rd_data;
  (* src = "/home/runner/workspace/hardware/registers.py:33" *)
  wire [1:0] cr_word_rd_sel;
  (* src = "/home/runner/workspace/hardware/registers.py:28" *)
  wire [1:0] cr_word_sel;
  (* src = "/home/runner/workspace/hardware/registers.py:27" *)
  wire [3:0] cr_word_wr_addr;
  (* src = "/home/runner/workspace/hardware/registers.py:29" *)
  wire [31:0] cr_word_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:30" *)
  wire cr_word_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:23" *)
  input [3:0] cr_wr_addr;
  wire [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  input [95:0] cr_wr_data;
  wire [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/registers.py:24" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/registers.py:25" *)
  input cr_wr_en;
  wire cr_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr0 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr1 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr10 = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  wire [31:0] dr11;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  wire [31:0] dr12;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  wire [31:0] dr13;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  wire [31:0] dr14;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  wire [31:0] dr15;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr2 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr3 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr4 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr5 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr6 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr7 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr8 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  reg [31:0] dr9 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:46" *)
  input [3:0] dr_rd_addr1;
  wire [3:0] dr_rd_addr1;
  (* src = "/home/runner/workspace/hardware/registers.py:48" *)
  input [3:0] dr_rd_addr2;
  wire [3:0] dr_rd_addr2;
  (* src = "/home/runner/workspace/hardware/registers.py:47" *)
  output [31:0] dr_rd_data1;
  wire [31:0] dr_rd_data1;
  (* src = "/home/runner/workspace/hardware/registers.py:49" *)
  output [31:0] dr_rd_data2;
  wire [31:0] dr_rd_data2;
  (* src = "/home/runner/workspace/hardware/registers.py:50" *)
  input [3:0] dr_wr_addr;
  wire [3:0] dr_wr_addr;
  (* src = "/home/runner/workspace/hardware/registers.py:51" *)
  input [31:0] dr_wr_data;
  wire [31:0] dr_wr_data;
  (* src = "/home/runner/workspace/hardware/registers.py:52" *)
  input dr_wr_en;
  wire dr_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:103" *)
  output [3:0] flags;
  reg [3:0] flags = 4'h0;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags.C ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags.N ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags.V ;
  (* src = "/home/runner/workspace/hardware/registers.py:54" *)
  wire \flags.Z ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  input [3:0] flags_in;
  wire [3:0] flags_in;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.C ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.N ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.V ;
  (* src = "/home/runner/workspace/hardware/registers.py:55" *)
  wire \flags_in.Z ;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/registers.py:103" *)
  wire [3:0] flags_reg;
  (* src = "/home/runner/workspace/hardware/registers.py:103" *)
  wire \flags_reg.C ;
  (* src = "/home/runner/workspace/hardware/registers.py:103" *)
  wire \flags_reg.N ;
  (* src = "/home/runner/workspace/hardware/registers.py:103" *)
  wire \flags_reg.V ;
  (* src = "/home/runner/workspace/hardware/registers.py:103" *)
  wire \flags_reg.Z ;
  (* src = "/home/runner/workspace/hardware/registers.py:56" *)
  input flags_wr_en;
  wire flags_wr_en;
  (* src = "/home/runner/workspace/hardware/registers.py:72" *)
  input m_clear_en;
  wire m_clear_en;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  output [31:0] m_dr11;
  reg [31:0] m_dr11 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  output [31:0] m_dr12;
  reg [31:0] m_dr12 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  output [31:0] m_dr13;
  reg [31:0] m_dr13 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  output [31:0] m_dr14;
  reg [31:0] m_dr14 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  output [31:0] m_dr15;
  reg [31:0] m_dr15 = 32'd0;
  (* src = "/home/runner/workspace/hardware/registers.py:73" *)
  input m_flag_restore_en;
  wire m_flag_restore_en;
  (* src = "/home/runner/workspace/hardware/registers.py:74" *)
  input m_flag_restore_val;
  wire m_flag_restore_val;
  (* src = "/home/runner/workspace/hardware/registers.py:80" *)
  input [31:0] m_set_dr11;
  wire [31:0] m_set_dr11;
  (* src = "/home/runner/workspace/hardware/registers.py:81" *)
  input [31:0] m_set_dr12;
  wire [31:0] m_set_dr12;
  (* src = "/home/runner/workspace/hardware/registers.py:82" *)
  input [31:0] m_set_dr13;
  wire [31:0] m_set_dr13;
  (* src = "/home/runner/workspace/hardware/registers.py:83" *)
  input [31:0] m_set_dr14;
  wire [31:0] m_set_dr14;
  (* src = "/home/runner/workspace/hardware/registers.py:84" *)
  input [31:0] m_set_dr15;
  wire [31:0] m_set_dr15;
  (* src = "/home/runner/workspace/hardware/registers.py:71" *)
  input m_set_en;
  wire m_set_en;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr5 <= \$31 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr6 <= \$32 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr7 <= \$33 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr8 <= \$34 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr9 <= \$35 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr10 <= \$36 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    m_dr11 <= \$37 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    m_dr12 <= \$38 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    m_dr13 <= \$39 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    m_dr14 <= \$40 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    m_dr15 <= \$41 ;
  (* src = "/home/runner/workspace/hardware/registers.py:103" *)
  always @(posedge clk)
    flags <= \$42 ;
  (* src = "/home/runner/workspace/hardware/registers.py:106" *)
  always @(posedge clk)
    cr15_m_flag <= \$43 ;
  assign \$4  = ! (* src = "/home/runner/workspace/hardware/registers.py:197" *) dr_rd_addr1;
  assign dr_rd_data1 = \$4  ? (* src = "/home/runner/workspace/hardware/registers.py:197" *) 32'd0 : \$5 ;
  assign \$6  = ! (* src = "/home/runner/workspace/hardware/registers.py:198" *) dr_rd_addr2;
  assign dr_rd_data2 = \$6  ? (* src = "/home/runner/workspace/hardware/registers.py:198" *) 32'd0 : \$7 ;
  assign \$8  = | (* src = "/home/runner/workspace/hardware/registers.py:174" *) dr_wr_addr;
  assign \$9  = dr_wr_en & (* src = "/home/runner/workspace/hardware/registers.py:174" *) \$8 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr0 <= \$10 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr1 <= \$11 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr2 <= \$12 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr3 <= \$13 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr4 <= \$14 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr5 <= \$15 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr6 <= \$16 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr7 <= \$17 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr8 <= \$18 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr9 <= \$19 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr10 <= \$20 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr11 <= \$21 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr12 <= \$22 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr13 <= \$23 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr14 <= \$24 ;
  (* src = "/home/runner/workspace/hardware/registers.py:101" *)
  always @(posedge clk)
    cr15 <= \$25 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr0 <= \$26 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr1 <= \$27 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr2 <= \$28 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr3 <= \$29 ;
  (* src = "/home/runner/workspace/hardware/registers.py:102" *)
  always @(posedge clk)
    dr4 <= \$30 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$32  = dr6;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$32  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              \$32  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$33  = dr7;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$33  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              \$33  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$34  = dr8;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$34  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              \$34  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$35  = dr9;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$35  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              \$35  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$36  = dr10;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$36  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              \$36  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$37  = m_dr11;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$37  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              \$37  = dr_wr_data;
        endcase
      end
      if (m_set_en) begin
        \$37  = m_set_dr11;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$38  = m_dr12;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$38  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              \$38  = dr_wr_data;
        endcase
      end
      if (m_set_en) begin
        \$38  = m_set_dr12;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$39  = m_dr13;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$39  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              /* empty */;
          4'hd:
              \$39  = dr_wr_data;
        endcase
      end
      if (m_set_en) begin
        \$39  = m_set_dr13;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$40  = m_dr14;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$40  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              /* empty */;
          4'hd:
              /* empty */;
          4'he:
              \$40  = dr_wr_data;
        endcase
      end
      if (m_set_en) begin
        \$40  = m_set_dr14;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$41  = m_dr15;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$41  = 32'd0;
    end else begin
      if (\$9 ) begin
        (* full_case = 32'd1 *)
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              /* empty */;
          4'hd:
              /* empty */;
          4'he:
              /* empty */;
          4'hf:
              \$41  = dr_wr_data;
        endcase
      end
      if (m_set_en) begin
        \$41  = m_set_dr15;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$42  = flags;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$42  = 4'h0;
    end else begin
      if (flags_wr_en) begin
        \$42  = flags_in;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$43  = cr15_m_flag;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$43  = 1'h0;
    end else begin
      if (m_set_en) begin
        \$43  = 1'h1;
      end else if (m_clear_en) begin
        \$43  = 1'h0;
      end else if (m_flag_restore_en) begin
        \$43  = m_flag_restore_val;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    (* full_case = 32'd1 *)
    casez (cr_rd_addr)
      4'h0:
          cr_rd_data = cr0;
      4'h1:
          cr_rd_data = cr1;
      4'h2:
          cr_rd_data = cr2;
      4'h3:
          cr_rd_data = cr3;
      4'h4:
          cr_rd_data = cr4;
      4'h5:
          cr_rd_data = cr5;
      4'h6:
          cr_rd_data = cr6;
      4'h7:
          cr_rd_data = cr7;
      4'h8:
          cr_rd_data = cr8;
      4'h9:
          cr_rd_data = cr9;
      4'ha:
          cr_rd_data = cr10;
      4'hb:
          cr_rd_data = cr11;
      4'hc:
          cr_rd_data = cr12;
      4'hd:
          cr_rd_data = cr13;
      4'he:
          cr_rd_data = cr14;
      4'hf:
          cr_rd_data = cr15;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    (* full_case = 32'd1 *)
    casez (dr_rd_addr1)
      4'h0:
          \$5  = dr0;
      4'h1:
          \$5  = dr1;
      4'h2:
          \$5  = dr2;
      4'h3:
          \$5  = dr3;
      4'h4:
          \$5  = dr4;
      4'h5:
          \$5  = dr5;
      4'h6:
          \$5  = dr6;
      4'h7:
          \$5  = dr7;
      4'h8:
          \$5  = dr8;
      4'h9:
          \$5  = dr9;
      4'ha:
          \$5  = dr10;
      4'hb:
          \$5  = m_dr11;
      4'hc:
          \$5  = m_dr12;
      4'hd:
          \$5  = m_dr13;
      4'he:
          \$5  = m_dr14;
      4'hf:
          \$5  = m_dr15;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    (* full_case = 32'd1 *)
    casez (dr_rd_addr2)
      4'h0:
          \$7  = dr0;
      4'h1:
          \$7  = dr1;
      4'h2:
          \$7  = dr2;
      4'h3:
          \$7  = dr3;
      4'h4:
          \$7  = dr4;
      4'h5:
          \$7  = dr5;
      4'h6:
          \$7  = dr6;
      4'h7:
          \$7  = dr7;
      4'h8:
          \$7  = dr8;
      4'h9:
          \$7  = dr9;
      4'ha:
          \$7  = dr10;
      4'hb:
          \$7  = m_dr11;
      4'hc:
          \$7  = m_dr12;
      4'hd:
          \$7  = m_dr13;
      4'he:
          \$7  = m_dr14;
      4'hf:
          \$7  = m_dr15;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$10  = cr0;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$10  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              \$10  = cr_wr_data;
        endcase
      end
      if (cr0_gt_wr_en) begin
        \$10 [31:0] = cr0_gt_wr_data;
      end
      if (cr_null_mask[0]) begin
        \$10  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[0]) begin
        \$10 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$11  = cr1;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$11  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              \$11  = cr_wr_data;
        endcase
      end
      if (cr1_gt_wr_en) begin
        \$11 [31:0] = cr1_gt_wr_data;
      end
      if (cr_null_mask[1]) begin
        \$11  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[1]) begin
        \$11 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$12  = cr2;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$12  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              \$12  = cr_wr_data;
        endcase
      end
      if (cr2_gt_wr_en) begin
        \$12 [31:0] = cr2_gt_wr_data;
      end
      if (cr_null_mask[2]) begin
        \$12  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[2]) begin
        \$12 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$13  = cr3;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$13  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              \$13  = cr_wr_data;
        endcase
      end
      if (cr3_gt_wr_en) begin
        \$13 [31:0] = cr3_gt_wr_data;
      end
      if (cr_null_mask[3]) begin
        \$13  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[3]) begin
        \$13 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$14  = cr4;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$14  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              \$14  = cr_wr_data;
        endcase
      end
      if (cr4_gt_wr_en) begin
        \$14 [31:0] = cr4_gt_wr_data;
      end
      if (cr_null_mask[4]) begin
        \$14  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[4]) begin
        \$14 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$15  = cr5;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$15  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              \$15  = cr_wr_data;
        endcase
      end
      if (cr5_gt_wr_en) begin
        \$15 [31:0] = cr5_gt_wr_data;
      end
      if (cr_null_mask[5]) begin
        \$15  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[5]) begin
        \$15 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$16  = cr6;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$16  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              \$16  = cr_wr_data;
        endcase
      end
      if (cr6_gt_wr_en) begin
        \$16 [31:0] = cr6_gt_wr_data;
      end
      if (cr_null_mask[6]) begin
        \$16  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[6]) begin
        \$16 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$17  = cr7;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$17  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              \$17  = cr_wr_data;
        endcase
      end
      if (cr7_gt_wr_en) begin
        \$17 [31:0] = cr7_gt_wr_data;
      end
      if (cr_null_mask[7]) begin
        \$17  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[7]) begin
        \$17 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$18  = cr8;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$18  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              \$18  = cr_wr_data;
        endcase
      end
      if (cr8_gt_wr_en) begin
        \$18 [31:0] = cr8_gt_wr_data;
      end
      if (cr_null_mask[8]) begin
        \$18  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[8]) begin
        \$18 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$19  = cr9;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$19  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              \$19  = cr_wr_data;
        endcase
      end
      if (cr9_gt_wr_en) begin
        \$19 [31:0] = cr9_gt_wr_data;
      end
      if (cr_null_mask[9]) begin
        \$19  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[9]) begin
        \$19 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$20  = cr10;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$20  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              \$20  = cr_wr_data;
        endcase
      end
      if (cr10_gt_wr_en) begin
        \$20 [31:0] = cr10_gt_wr_data;
      end
      if (cr_null_mask[10]) begin
        \$20  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[10]) begin
        \$20 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$21  = cr11;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$21  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              \$21  = cr_wr_data;
        endcase
      end
      if (cr11_gt_wr_en) begin
        \$21 [31:0] = cr11_gt_wr_data;
      end
      if (cr_null_mask[11]) begin
        \$21  = 96'h000000000000000000000000;
      end else if (cr_b_clear_mask[11]) begin
        \$21 [31] = 1'h0;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$22  = cr12;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$22  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              \$22  = cr_wr_data;
        endcase
      end
      if (cr12_gt_wr_en) begin
        \$22 [31:0] = cr12_gt_wr_data;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$23  = cr13;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$23  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              /* empty */;
          4'hd:
              \$23  = cr_wr_data;
        endcase
      end
      if (cr13_gt_wr_en) begin
        \$23 [31:0] = cr13_gt_wr_data;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$24  = cr14;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$24  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              /* empty */;
          4'hd:
              /* empty */;
          4'he:
              \$24  = cr_wr_data;
        endcase
      end
      if (cr14_gt_wr_en) begin
        \$24 [31:0] = cr14_gt_wr_data;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$25  = cr15;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$25  = 96'h000000000000000000000000;
    end else begin
      if (cr_wr_en) begin
        (* full_case = 32'd1 *)
        casez (cr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              /* empty */;
          4'h6:
              /* empty */;
          4'h7:
              /* empty */;
          4'h8:
              /* empty */;
          4'h9:
              /* empty */;
          4'ha:
              /* empty */;
          4'hb:
              /* empty */;
          4'hc:
              /* empty */;
          4'hd:
              /* empty */;
          4'he:
              /* empty */;
          4'hf:
              \$25  = cr_wr_data;
        endcase
      end
      if (cr15_gt_wr_en) begin
        \$25 [31:0] = cr15_gt_wr_data;
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$26  = dr0;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$26  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              \$26  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$27  = dr1;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$27  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              \$27  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$28  = dr2;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$28  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              \$28  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$29  = dr3;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$29  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              \$29  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$30  = dr4;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$30  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              \$30  = dr_wr_data;
        endcase
      end
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$64 ) begin end
    \$31  = dr5;
    (* full_case = 32'd1 *)
    if (clear_all) begin
      \$31  = 32'd0;
    end else begin
      if (\$9 ) begin
        casez (dr_wr_addr)
          4'h0:
              /* empty */;
          4'h1:
              /* empty */;
          4'h2:
              /* empty */;
          4'h3:
              /* empty */;
          4'h4:
              /* empty */;
          4'h5:
              \$31  = dr_wr_data;
        endcase
      end
    end
  end
  assign cr_word_rd_sel = 2'h0;
  assign cr_word_rd_addr = 4'h0;
  assign cr5_heap = cr5;
  assign cr6_clist = cr6;
  assign cr12_thread = cr12;
  assign cr13_interrupt = cr13;
  assign cr14_code = cr14;
  assign cr15_namespace = cr15;
  assign dr11 = m_dr11;
  assign dr12 = m_dr12;
  assign dr13 = m_dr13;
  assign dr14 = m_dr14;
  assign dr15 = m_dr15;
  assign cr15_m_reg = cr15_m_flag;
  assign flags_reg = flags;
  
  assign cr_word_wr_en = 1'h0;
  assign cr_word_sel = 2'h0;
  assign cr_word_wr_addr = 4'h0;
  assign cr_word_wr_data = 32'd0;
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \cr0.word0_gt  = cr0[31:0];
  assign \cr0.word0_gt.slot_id  = cr0[15:0];
  assign \cr0.word0_gt.gt_seq  = cr0[24:16];
  assign \cr0.word0_gt.gt_type  = cr0[26:25];
  assign \cr0.word0_gt.dom  = cr0[27];
  assign \cr0.word0_gt.perm  = cr0[30:28];
  assign \cr0.word0_gt.b_flag  = cr0[31];
  assign \cr0.word1_location  = cr0[63:32];
  assign \cr0.word2_w2  = cr0[95:64];
  assign \cr1.word0_gt  = cr1[31:0];
  assign \cr1.word0_gt.slot_id  = cr1[15:0];
  assign \cr1.word0_gt.gt_seq  = cr1[24:16];
  assign \cr1.word0_gt.gt_type  = cr1[26:25];
  assign \cr1.word0_gt.dom  = cr1[27];
  assign \cr1.word0_gt.perm  = cr1[30:28];
  assign \cr1.word0_gt.b_flag  = cr1[31];
  assign \cr1.word1_location  = cr1[63:32];
  assign \cr1.word2_w2  = cr1[95:64];
  assign \cr2.word0_gt  = cr2[31:0];
  assign \cr2.word0_gt.slot_id  = cr2[15:0];
  assign \cr2.word0_gt.gt_seq  = cr2[24:16];
  assign \cr2.word0_gt.gt_type  = cr2[26:25];
  assign \cr2.word0_gt.dom  = cr2[27];
  assign \cr2.word0_gt.perm  = cr2[30:28];
  assign \cr2.word0_gt.b_flag  = cr2[31];
  assign \cr2.word1_location  = cr2[63:32];
  assign \cr2.word2_w2  = cr2[95:64];
  assign \cr3.word0_gt  = cr3[31:0];
  assign \cr3.word0_gt.slot_id  = cr3[15:0];
  assign \cr3.word0_gt.gt_seq  = cr3[24:16];
  assign \cr3.word0_gt.gt_type  = cr3[26:25];
  assign \cr3.word0_gt.dom  = cr3[27];
  assign \cr3.word0_gt.perm  = cr3[30:28];
  assign \cr3.word0_gt.b_flag  = cr3[31];
  assign \cr3.word1_location  = cr3[63:32];
  assign \cr3.word2_w2  = cr3[95:64];
  assign \cr4.word0_gt  = cr4[31:0];
  assign \cr4.word0_gt.slot_id  = cr4[15:0];
  assign \cr4.word0_gt.gt_seq  = cr4[24:16];
  assign \cr4.word0_gt.gt_type  = cr4[26:25];
  assign \cr4.word0_gt.dom  = cr4[27];
  assign \cr4.word0_gt.perm  = cr4[30:28];
  assign \cr4.word0_gt.b_flag  = cr4[31];
  assign \cr4.word1_location  = cr4[63:32];
  assign \cr4.word2_w2  = cr4[95:64];
  assign \cr5.word0_gt  = cr5[31:0];
  assign \cr5.word0_gt.slot_id  = cr5[15:0];
  assign \cr5.word0_gt.gt_seq  = cr5[24:16];
  assign \cr5.word0_gt.gt_type  = cr5[26:25];
  assign \cr5.word0_gt.dom  = cr5[27];
  assign \cr5.word0_gt.perm  = cr5[30:28];
  assign \cr5.word0_gt.b_flag  = cr5[31];
  assign \cr5.word1_location  = cr5[63:32];
  assign \cr5.word2_w2  = cr5[95:64];
  assign \cr6.word0_gt  = cr6[31:0];
  assign \cr6.word0_gt.slot_id  = cr6[15:0];
  assign \cr6.word0_gt.gt_seq  = cr6[24:16];
  assign \cr6.word0_gt.gt_type  = cr6[26:25];
  assign \cr6.word0_gt.dom  = cr6[27];
  assign \cr6.word0_gt.perm  = cr6[30:28];
  assign \cr6.word0_gt.b_flag  = cr6[31];
  assign \cr6.word1_location  = cr6[63:32];
  assign \cr6.word2_w2  = cr6[95:64];
  assign \cr7.word0_gt  = cr7[31:0];
  assign \cr7.word0_gt.slot_id  = cr7[15:0];
  assign \cr7.word0_gt.gt_seq  = cr7[24:16];
  assign \cr7.word0_gt.gt_type  = cr7[26:25];
  assign \cr7.word0_gt.dom  = cr7[27];
  assign \cr7.word0_gt.perm  = cr7[30:28];
  assign \cr7.word0_gt.b_flag  = cr7[31];
  assign \cr7.word1_location  = cr7[63:32];
  assign \cr7.word2_w2  = cr7[95:64];
  assign \cr8.word0_gt  = cr8[31:0];
  assign \cr8.word0_gt.slot_id  = cr8[15:0];
  assign \cr8.word0_gt.gt_seq  = cr8[24:16];
  assign \cr8.word0_gt.gt_type  = cr8[26:25];
  assign \cr8.word0_gt.dom  = cr8[27];
  assign \cr8.word0_gt.perm  = cr8[30:28];
  assign \cr8.word0_gt.b_flag  = cr8[31];
  assign \cr8.word1_location  = cr8[63:32];
  assign \cr8.word2_w2  = cr8[95:64];
  assign \cr9.word0_gt  = cr9[31:0];
  assign \cr9.word0_gt.slot_id  = cr9[15:0];
  assign \cr9.word0_gt.gt_seq  = cr9[24:16];
  assign \cr9.word0_gt.gt_type  = cr9[26:25];
  assign \cr9.word0_gt.dom  = cr9[27];
  assign \cr9.word0_gt.perm  = cr9[30:28];
  assign \cr9.word0_gt.b_flag  = cr9[31];
  assign \cr9.word1_location  = cr9[63:32];
  assign \cr9.word2_w2  = cr9[95:64];
  assign \cr10.word0_gt  = cr10[31:0];
  assign \cr10.word0_gt.slot_id  = cr10[15:0];
  assign \cr10.word0_gt.gt_seq  = cr10[24:16];
  assign \cr10.word0_gt.gt_type  = cr10[26:25];
  assign \cr10.word0_gt.dom  = cr10[27];
  assign \cr10.word0_gt.perm  = cr10[30:28];
  assign \cr10.word0_gt.b_flag  = cr10[31];
  assign \cr10.word1_location  = cr10[63:32];
  assign \cr10.word2_w2  = cr10[95:64];
  assign \cr11.word0_gt  = cr11[31:0];
  assign \cr11.word0_gt.slot_id  = cr11[15:0];
  assign \cr11.word0_gt.gt_seq  = cr11[24:16];
  assign \cr11.word0_gt.gt_type  = cr11[26:25];
  assign \cr11.word0_gt.dom  = cr11[27];
  assign \cr11.word0_gt.perm  = cr11[30:28];
  assign \cr11.word0_gt.b_flag  = cr11[31];
  assign \cr11.word1_location  = cr11[63:32];
  assign \cr11.word2_w2  = cr11[95:64];
  assign \cr12.word0_gt  = cr12[31:0];
  assign \cr12.word0_gt.slot_id  = cr12[15:0];
  assign \cr12.word0_gt.gt_seq  = cr12[24:16];
  assign \cr12.word0_gt.gt_type  = cr12[26:25];
  assign \cr12.word0_gt.dom  = cr12[27];
  assign \cr12.word0_gt.perm  = cr12[30:28];
  assign \cr12.word0_gt.b_flag  = cr12[31];
  assign \cr12.word1_location  = cr12[63:32];
  assign \cr12.word2_w2  = cr12[95:64];
  assign \cr13.word0_gt  = cr13[31:0];
  assign \cr13.word0_gt.slot_id  = cr13[15:0];
  assign \cr13.word0_gt.gt_seq  = cr13[24:16];
  assign \cr13.word0_gt.gt_type  = cr13[26:25];
  assign \cr13.word0_gt.dom  = cr13[27];
  assign \cr13.word0_gt.perm  = cr13[30:28];
  assign \cr13.word0_gt.b_flag  = cr13[31];
  assign \cr13.word1_location  = cr13[63:32];
  assign \cr13.word2_w2  = cr13[95:64];
  assign \cr14.word0_gt  = cr14[31:0];
  assign \cr14.word0_gt.slot_id  = cr14[15:0];
  assign \cr14.word0_gt.gt_seq  = cr14[24:16];
  assign \cr14.word0_gt.gt_type  = cr14[26:25];
  assign \cr14.word0_gt.dom  = cr14[27];
  assign \cr14.word0_gt.perm  = cr14[30:28];
  assign \cr14.word0_gt.b_flag  = cr14[31];
  assign \cr14.word1_location  = cr14[63:32];
  assign \cr14.word2_w2  = cr14[95:64];
  assign \cr15.word0_gt  = cr15[31:0];
  assign \cr15.word0_gt.slot_id  = cr15[15:0];
  assign \cr15.word0_gt.gt_seq  = cr15[24:16];
  assign \cr15.word0_gt.gt_type  = cr15[26:25];
  assign \cr15.word0_gt.dom  = cr15[27];
  assign \cr15.word0_gt.perm  = cr15[30:28];
  assign \cr15.word0_gt.b_flag  = cr15[31];
  assign \cr15.word1_location  = cr15[63:32];
  assign \cr15.word2_w2  = cr15[95:64];
  assign \cr5_heap.word0_gt  = cr5[31:0];
  assign \cr5_heap.word0_gt.slot_id  = cr5[15:0];
  assign \cr5_heap.word0_gt.gt_seq  = cr5[24:16];
  assign \cr5_heap.word0_gt.gt_type  = cr5[26:25];
  assign \cr5_heap.word0_gt.dom  = cr5[27];
  assign \cr5_heap.word0_gt.perm  = cr5[30:28];
  assign \cr5_heap.word0_gt.b_flag  = cr5[31];
  assign \cr5_heap.word1_location  = cr5[63:32];
  assign \cr5_heap.word2_w2  = cr5[95:64];
  assign \cr6_clist.word0_gt  = cr6[31:0];
  assign \cr6_clist.word0_gt.slot_id  = cr6[15:0];
  assign \cr6_clist.word0_gt.gt_seq  = cr6[24:16];
  assign \cr6_clist.word0_gt.gt_type  = cr6[26:25];
  assign \cr6_clist.word0_gt.dom  = cr6[27];
  assign \cr6_clist.word0_gt.perm  = cr6[30:28];
  assign \cr6_clist.word0_gt.b_flag  = cr6[31];
  assign \cr6_clist.word1_location  = cr6[63:32];
  assign \cr6_clist.word2_w2  = cr6[95:64];
  assign \cr12_thread.word0_gt  = cr12[31:0];
  assign \cr12_thread.word0_gt.slot_id  = cr12[15:0];
  assign \cr12_thread.word0_gt.gt_seq  = cr12[24:16];
  assign \cr12_thread.word0_gt.gt_type  = cr12[26:25];
  assign \cr12_thread.word0_gt.dom  = cr12[27];
  assign \cr12_thread.word0_gt.perm  = cr12[30:28];
  assign \cr12_thread.word0_gt.b_flag  = cr12[31];
  assign \cr12_thread.word1_location  = cr12[63:32];
  assign \cr12_thread.word2_w2  = cr12[95:64];
  assign \cr13_interrupt.word0_gt  = cr13[31:0];
  assign \cr13_interrupt.word0_gt.slot_id  = cr13[15:0];
  assign \cr13_interrupt.word0_gt.gt_seq  = cr13[24:16];
  assign \cr13_interrupt.word0_gt.gt_type  = cr13[26:25];
  assign \cr13_interrupt.word0_gt.dom  = cr13[27];
  assign \cr13_interrupt.word0_gt.perm  = cr13[30:28];
  assign \cr13_interrupt.word0_gt.b_flag  = cr13[31];
  assign \cr13_interrupt.word1_location  = cr13[63:32];
  assign \cr13_interrupt.word2_w2  = cr13[95:64];
  assign \cr14_code.word0_gt  = cr14[31:0];
  assign \cr14_code.word0_gt.slot_id  = cr14[15:0];
  assign \cr14_code.word0_gt.gt_seq  = cr14[24:16];
  assign \cr14_code.word0_gt.gt_type  = cr14[26:25];
  assign \cr14_code.word0_gt.dom  = cr14[27];
  assign \cr14_code.word0_gt.perm  = cr14[30:28];
  assign \cr14_code.word0_gt.b_flag  = cr14[31];
  assign \cr14_code.word1_location  = cr14[63:32];
  assign \cr14_code.word2_w2  = cr14[95:64];
  assign \cr15_namespace.word0_gt  = cr15[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15[27];
  assign \cr15_namespace.word0_gt.perm  = cr15[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15[31];
  assign \cr15_namespace.word1_location  = cr15[63:32];
  assign \cr15_namespace.word2_w2  = cr15[95:64];
  assign \flags.N  = flags[0];
  assign \flags.Z  = flags[1];
  assign \flags.C  = flags[2];
  assign \flags.V  = flags[3];
  assign \flags_reg.N  = flags[0];
  assign \flags_reg.Z  = flags[1];
  assign \flags_reg.C  = flags[2];
  assign \flags_reg.V  = flags[3];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr0_gt_wr_data.slot_id  = cr0_gt_wr_data[15:0];
  assign \cr0_gt_wr_data.gt_seq  = cr0_gt_wr_data[24:16];
  assign \cr0_gt_wr_data.gt_type  = cr0_gt_wr_data[26:25];
  assign \cr0_gt_wr_data.dom  = cr0_gt_wr_data[27];
  assign \cr0_gt_wr_data.perm  = cr0_gt_wr_data[30:28];
  assign \cr0_gt_wr_data.b_flag  = cr0_gt_wr_data[31];
  assign \cr1_gt_wr_data.slot_id  = cr1_gt_wr_data[15:0];
  assign \cr1_gt_wr_data.gt_seq  = cr1_gt_wr_data[24:16];
  assign \cr1_gt_wr_data.gt_type  = cr1_gt_wr_data[26:25];
  assign \cr1_gt_wr_data.dom  = cr1_gt_wr_data[27];
  assign \cr1_gt_wr_data.perm  = cr1_gt_wr_data[30:28];
  assign \cr1_gt_wr_data.b_flag  = cr1_gt_wr_data[31];
  assign \cr2_gt_wr_data.slot_id  = cr2_gt_wr_data[15:0];
  assign \cr2_gt_wr_data.gt_seq  = cr2_gt_wr_data[24:16];
  assign \cr2_gt_wr_data.gt_type  = cr2_gt_wr_data[26:25];
  assign \cr2_gt_wr_data.dom  = cr2_gt_wr_data[27];
  assign \cr2_gt_wr_data.perm  = cr2_gt_wr_data[30:28];
  assign \cr2_gt_wr_data.b_flag  = cr2_gt_wr_data[31];
  assign \cr3_gt_wr_data.slot_id  = cr3_gt_wr_data[15:0];
  assign \cr3_gt_wr_data.gt_seq  = cr3_gt_wr_data[24:16];
  assign \cr3_gt_wr_data.gt_type  = cr3_gt_wr_data[26:25];
  assign \cr3_gt_wr_data.dom  = cr3_gt_wr_data[27];
  assign \cr3_gt_wr_data.perm  = cr3_gt_wr_data[30:28];
  assign \cr3_gt_wr_data.b_flag  = cr3_gt_wr_data[31];
  assign \cr4_gt_wr_data.slot_id  = cr4_gt_wr_data[15:0];
  assign \cr4_gt_wr_data.gt_seq  = cr4_gt_wr_data[24:16];
  assign \cr4_gt_wr_data.gt_type  = cr4_gt_wr_data[26:25];
  assign \cr4_gt_wr_data.dom  = cr4_gt_wr_data[27];
  assign \cr4_gt_wr_data.perm  = cr4_gt_wr_data[30:28];
  assign \cr4_gt_wr_data.b_flag  = cr4_gt_wr_data[31];
  assign \cr5_gt_wr_data.slot_id  = cr5_gt_wr_data[15:0];
  assign \cr5_gt_wr_data.gt_seq  = cr5_gt_wr_data[24:16];
  assign \cr5_gt_wr_data.gt_type  = cr5_gt_wr_data[26:25];
  assign \cr5_gt_wr_data.dom  = cr5_gt_wr_data[27];
  assign \cr5_gt_wr_data.perm  = cr5_gt_wr_data[30:28];
  assign \cr5_gt_wr_data.b_flag  = cr5_gt_wr_data[31];
  assign \cr6_gt_wr_data.slot_id  = cr6_gt_wr_data[15:0];
  assign \cr6_gt_wr_data.gt_seq  = cr6_gt_wr_data[24:16];
  assign \cr6_gt_wr_data.gt_type  = cr6_gt_wr_data[26:25];
  assign \cr6_gt_wr_data.dom  = cr6_gt_wr_data[27];
  assign \cr6_gt_wr_data.perm  = cr6_gt_wr_data[30:28];
  assign \cr6_gt_wr_data.b_flag  = cr6_gt_wr_data[31];
  assign \cr7_gt_wr_data.slot_id  = cr7_gt_wr_data[15:0];
  assign \cr7_gt_wr_data.gt_seq  = cr7_gt_wr_data[24:16];
  assign \cr7_gt_wr_data.gt_type  = cr7_gt_wr_data[26:25];
  assign \cr7_gt_wr_data.dom  = cr7_gt_wr_data[27];
  assign \cr7_gt_wr_data.perm  = cr7_gt_wr_data[30:28];
  assign \cr7_gt_wr_data.b_flag  = cr7_gt_wr_data[31];
  assign \cr8_gt_wr_data.slot_id  = cr8_gt_wr_data[15:0];
  assign \cr8_gt_wr_data.gt_seq  = cr8_gt_wr_data[24:16];
  assign \cr8_gt_wr_data.gt_type  = cr8_gt_wr_data[26:25];
  assign \cr8_gt_wr_data.dom  = cr8_gt_wr_data[27];
  assign \cr8_gt_wr_data.perm  = cr8_gt_wr_data[30:28];
  assign \cr8_gt_wr_data.b_flag  = cr8_gt_wr_data[31];
  assign \cr9_gt_wr_data.slot_id  = cr9_gt_wr_data[15:0];
  assign \cr9_gt_wr_data.gt_seq  = cr9_gt_wr_data[24:16];
  assign \cr9_gt_wr_data.gt_type  = cr9_gt_wr_data[26:25];
  assign \cr9_gt_wr_data.dom  = cr9_gt_wr_data[27];
  assign \cr9_gt_wr_data.perm  = cr9_gt_wr_data[30:28];
  assign \cr9_gt_wr_data.b_flag  = cr9_gt_wr_data[31];
  assign \cr10_gt_wr_data.slot_id  = cr10_gt_wr_data[15:0];
  assign \cr10_gt_wr_data.gt_seq  = cr10_gt_wr_data[24:16];
  assign \cr10_gt_wr_data.gt_type  = cr10_gt_wr_data[26:25];
  assign \cr10_gt_wr_data.dom  = cr10_gt_wr_data[27];
  assign \cr10_gt_wr_data.perm  = cr10_gt_wr_data[30:28];
  assign \cr10_gt_wr_data.b_flag  = cr10_gt_wr_data[31];
  assign \cr11_gt_wr_data.slot_id  = cr11_gt_wr_data[15:0];
  assign \cr11_gt_wr_data.gt_seq  = cr11_gt_wr_data[24:16];
  assign \cr11_gt_wr_data.gt_type  = cr11_gt_wr_data[26:25];
  assign \cr11_gt_wr_data.dom  = cr11_gt_wr_data[27];
  assign \cr11_gt_wr_data.perm  = cr11_gt_wr_data[30:28];
  assign \cr11_gt_wr_data.b_flag  = cr11_gt_wr_data[31];
  assign \cr12_gt_wr_data.slot_id  = cr12_gt_wr_data[15:0];
  assign \cr12_gt_wr_data.gt_seq  = cr12_gt_wr_data[24:16];
  assign \cr12_gt_wr_data.gt_type  = cr12_gt_wr_data[26:25];
  assign \cr12_gt_wr_data.dom  = cr12_gt_wr_data[27];
  assign \cr12_gt_wr_data.perm  = cr12_gt_wr_data[30:28];
  assign \cr12_gt_wr_data.b_flag  = cr12_gt_wr_data[31];
  assign \cr13_gt_wr_data.slot_id  = cr13_gt_wr_data[15:0];
  assign \cr13_gt_wr_data.gt_seq  = cr13_gt_wr_data[24:16];
  assign \cr13_gt_wr_data.gt_type  = cr13_gt_wr_data[26:25];
  assign \cr13_gt_wr_data.dom  = cr13_gt_wr_data[27];
  assign \cr13_gt_wr_data.perm  = cr13_gt_wr_data[30:28];
  assign \cr13_gt_wr_data.b_flag  = cr13_gt_wr_data[31];
  assign \cr14_gt_wr_data.slot_id  = cr14_gt_wr_data[15:0];
  assign \cr14_gt_wr_data.gt_seq  = cr14_gt_wr_data[24:16];
  assign \cr14_gt_wr_data.gt_type  = cr14_gt_wr_data[26:25];
  assign \cr14_gt_wr_data.dom  = cr14_gt_wr_data[27];
  assign \cr14_gt_wr_data.perm  = cr14_gt_wr_data[30:28];
  assign \cr14_gt_wr_data.b_flag  = cr14_gt_wr_data[31];
  assign \cr15_gt_wr_data.slot_id  = cr15_gt_wr_data[15:0];
  assign \cr15_gt_wr_data.gt_seq  = cr15_gt_wr_data[24:16];
  assign \cr15_gt_wr_data.gt_type  = cr15_gt_wr_data[26:25];
  assign \cr15_gt_wr_data.dom  = cr15_gt_wr_data[27];
  assign \cr15_gt_wr_data.perm  = cr15_gt_wr_data[30:28];
  assign \cr15_gt_wr_data.b_flag  = cr15_gt_wr_data[31];
  assign \flags_in.N  = flags_in[0];
  assign \flags_in.Z  = flags_in[1];
  assign \flags_in.C  = flags_in[2];
  assign \flags_in.V  = flags_in[3];
  assign cr_word_rd_data = \$1 [31:0];
  assign \$3  = cr0;
  assign \$2  = cr0;
  assign \$1  = cr0;
endmodule

(* src = "/home/runner/workspace/hardware/ret.py:61" *)
(* generator = "Amaranth" *)
module \top.core.u_return (clk, mem_rd_valid, return_start, cr_rd_data, cr_rd_addr, busy, complete, reboot_request, lambda_active, lambda_pc, cr5_heap, cr12_thread, nia_set, nia_value, lambda_clear, mem_rd_addr, mem_rd_en, mem_wr_addr, mem_wr_data, mem_wr_en, fault_valid, fault_type
, cload_e_gt, cr_src, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$65  = 0;
  wire \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  wire \$25 ;
  reg \$26 ;
  reg [4:0] \$27 ;
  reg \$28 ;
  reg \$29 ;
  wire [32:0] \$3 ;
  reg [31:0] \$30 ;
  reg [3:0] \$31 ;
  reg [95:0] \$32 ;
  reg [31:0] \$33 ;
  reg [31:0] \$34 ;
  reg [31:0] \$35 ;
  reg [31:0] \$36 ;
  reg [14:0] \$37 ;
  reg [15:0] \$38 ;
  wire [35:0] \$4 ;
  wire [36:0] \$5 ;
  wire [32:0] \$6 ;
  wire [35:0] \$7 ;
  wire [36:0] \$8 ;
  wire [17:0] \$9 ;
  (* src = "/home/runner/workspace/hardware/ret.py:15" *)
  output busy;
  wire busy;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ret.py:93" *)
  wire [31:0] callee_egt_latched;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ret.py:93" *)
  output [31:0] cload_e_gt;
  reg [31:0] cload_e_gt = 32'd0;
  (* src = "/home/runner/workspace/hardware/ret.py:16" *)
  output complete;
  wire complete;
  (* src = "/home/runner/workspace/hardware/ret.py:86" *)
  wire cr12_null;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  input [95:0] cr12_thread;
  wire [95:0] cr12_thread;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [31:0] \cr12_thread.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire \cr12_thread.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire \cr12_thread.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [8:0] \cr12_thread.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [1:0] \cr12_thread.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [2:0] \cr12_thread.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [15:0] \cr12_thread.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [31:0] \cr12_thread.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:47" *)
  wire [31:0] \cr12_thread.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:76" *)
  wire cr5_has_r;
  (* src = "/home/runner/workspace/hardware/ret.py:77" *)
  wire cr5_has_w;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  input [95:0] cr5_heap;
  wire [95:0] cr5_heap;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [31:0] \cr5_heap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire \cr5_heap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire \cr5_heap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [8:0] \cr5_heap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [1:0] \cr5_heap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [2:0] \cr5_heap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [15:0] \cr5_heap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [31:0] \cr5_heap.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:46" *)
  wire [31:0] \cr5_heap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:75" *)
  wire cr5_null;
  (* src = "/home/runner/workspace/hardware/ret.py:21" *)
  output [3:0] cr_rd_addr;
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:22" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:14" *)
  input [2:0] cr_src;
  wire [2:0] cr_src;
  (* src = "/home/runner/workspace/hardware/ret.py:23" *)
  wire [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:24" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:25" *)
  wire cr_wr_en;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/ret.py:146" *)
  wire fault_flag;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/ret.py:147" *)
  wire [4:0] fault_latched;
  (* src = "/home/runner/workspace/hardware/ret.py:147" *)
  output [4:0] fault_type;
  reg [4:0] fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/ret.py:146" *)
  output fault_valid;
  reg fault_valid = 1'h0;
  (* src = "/home/runner/workspace/hardware/ret.py:100" *)
  wire [15:0] frame_prev_sto;
  (* src = "/home/runner/workspace/hardware/ret.py:99" *)
  wire [14:0] frame_ret_pc;
  (* src = "/home/runner/workspace/hardware/ret.py:98" *)
  wire frame_sz;
  (* src = "/home/runner/workspace/hardware/ret.py:97" *)
  reg [31:0] frame_word = 32'd0;
  (* src = "/home/runner/workspace/hardware/ret.py:89" *)
  reg [31:0] heap_base_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ret.py:70" *)
  wire is_null_cap;
  (* src = "/home/runner/workspace/hardware/ret.py:42" *)
  input lambda_active;
  wire lambda_active;
  (* src = "/home/runner/workspace/hardware/ret.py:44" *)
  output lambda_clear;
  reg lambda_clear;
  (* src = "/home/runner/workspace/hardware/ret.py:43" *)
  input [31:0] lambda_pc;
  wire [31:0] lambda_pc;
  (* src = "/home/runner/workspace/hardware/ret.py:107" *)
  reg local_cr_rd_en;
  (* src = "/home/runner/workspace/hardware/ret.py:112" *)
  wire [31:0] local_mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/ret.py:113" *)
  wire local_mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ret.py:114" *)
  wire [31:0] local_mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/ret.py:115" *)
  wire [31:0] local_mem_wr_data;
  (* src = "/home/runner/workspace/hardware/ret.py:116" *)
  wire local_mem_wr_en;
  (* src = "/home/runner/workspace/hardware/ret.py:112" *)
  output [31:0] mem_rd_addr;
  reg [31:0] mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/ret.py:51" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ret.py:113" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ret.py:52" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ret.py:114" *)
  output [31:0] mem_wr_addr;
  reg [31:0] mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/ret.py:115" *)
  output [31:0] mem_wr_data;
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/ret.py:116" *)
  output mem_wr_en;
  reg mem_wr_en;
  (* src = "/home/runner/workspace/hardware/ret.py:32" *)
  wire [3:0] mload_cr_dst;
  (* src = "/home/runner/workspace/hardware/ret.py:31" *)
  wire [3:0] mload_cr_src;
  (* src = "/home/runner/workspace/hardware/ret.py:34" *)
  wire mload_direct;
  (* src = "/home/runner/workspace/hardware/ret.py:35" *)
  wire [31:0] mload_direct_gt;
  (* src = "/home/runner/workspace/hardware/ret.py:33" *)
  wire [15:0] mload_index;
  (* src = "/home/runner/workspace/hardware/ret.py:36" *)
  wire mload_m_elevated;
  (* src = "/home/runner/workspace/hardware/ret.py:30" *)
  wire mload_start;
  (* src = "/home/runner/workspace/hardware/ret.py:27" *)
  output nia_set;
  reg nia_set;
  (* src = "/home/runner/workspace/hardware/ret.py:28" *)
  output [31:0] nia_value;
  reg [31:0] nia_value;
  (* src = "/home/runner/workspace/hardware/ret.py:95" *)
  reg [15:0] prev_sto_latched = 16'h0000;
  (* src = "/home/runner/workspace/hardware/ret.py:19" *)
  output reboot_request;
  wire reboot_request;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] ret_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  reg [95:0] return_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire [31:0] \return_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire \return_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire \return_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire [8:0] \return_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire [1:0] \return_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire [2:0] \return_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire [15:0] \return_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire [31:0] \return_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  wire [31:0] \return_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/ret.py:94" *)
  reg [14:0] return_pc_latched = 15'h0000;
  (* src = "/home/runner/workspace/hardware/ret.py:13" *)
  input return_start;
  wire return_start;
  (* src = "/home/runner/workspace/hardware/ret.py:92" *)
  reg [31:0] sto_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ret.py:144" *)
  reg sub_done_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/ret.py:145" *)
  reg sub_fault_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/ret.py:90" *)
  reg [31:0] thread_base_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ret.py:92" *)
  always @(posedge clk)
    sto_latched <= \$35 ;
  (* src = "/home/runner/workspace/hardware/ret.py:97" *)
  always @(posedge clk)
    frame_word <= \$36 ;
  (* src = "/home/runner/workspace/hardware/ret.py:94" *)
  always @(posedge clk)
    return_pc_latched <= \$37 ;
  (* src = "/home/runner/workspace/hardware/ret.py:95" *)
  always @(posedge clk)
    prev_sto_latched <= \$38 ;
  assign is_null_cap = ! (* src = "/home/runner/workspace/hardware/ret.py:71" *) return_cap[26:25];
  assign cr5_null = ! (* src = "/home/runner/workspace/hardware/ret.py:79" *) cr5_heap[26:25];
  assign \$1  = ~ (* src = "/home/runner/workspace/hardware/ret.py:80" *) cr5_heap[27];
  assign cr5_has_r = \$1  & (* src = "/home/runner/workspace/hardware/ret.py:80" *) cr5_heap[28];
  assign \$2  = ~ (* src = "/home/runner/workspace/hardware/ret.py:81" *) cr5_heap[27];
  assign cr5_has_w = \$2  & (* src = "/home/runner/workspace/hardware/ret.py:81" *) cr5_heap[29];
  assign cr12_null = ! (* src = "/home/runner/workspace/hardware/ret.py:87" *) cr12_thread[26:25];
  assign cr_rd_addr = local_cr_rd_en ? (* src = "/home/runner/workspace/hardware/ret.py:109" *) { 1'h0, cr_src } : 4'h0;
  assign \$3  = sto_latched + (* src = "/home/runner/workspace/hardware/stack_frame.py:42" *) 2'h2;
  assign \$5  = thread_base_latched + (* src = "/home/runner/workspace/hardware/stack_frame.py:42" *) \$4 ;
  assign \$6  = sto_latched + (* src = "/home/runner/workspace/hardware/stack_frame.py:42" *) 1'h1;
  assign \$8  = thread_base_latched + (* src = "/home/runner/workspace/hardware/stack_frame.py:42" *) \$7 ;
  assign busy = ~ (* src = "/home/runner/workspace/hardware/ret.py:265" *) \$10 ;
  assign \$10  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) ret_state;
  assign \$11  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$12  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign complete = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$13  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign reboot_request = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$14  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$15  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$16  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$17  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$18  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$19  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign \$20  = ret_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$21  = return_cap[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) return_cap[30];
  assign \$22  = ~ (* src = "/home/runner/workspace/hardware/ret.py:183" *) \$21 ;
  assign \$23  = ~ (* src = "/home/runner/workspace/hardware/ret.py:193" *) cr5_has_r;
  assign \$24  = ~ (* src = "/home/runner/workspace/hardware/ret.py:196" *) cr5_has_w;
  assign \$25  = ~ (* src = "/home/runner/workspace/hardware/ret.py:221" *) mem_rd_data[31];
  (* src = "/home/runner/workspace/hardware/ret.py:146" *)
  always @(posedge clk)
    fault_valid <= \$26 ;
  (* src = "/home/runner/workspace/hardware/ret.py:147" *)
  always @(posedge clk)
    fault_type <= \$27 ;
  (* src = "/home/runner/workspace/hardware/ret.py:144" *)
  always @(posedge clk)
    sub_done_latched <= \$28 ;
  (* src = "/home/runner/workspace/hardware/ret.py:145" *)
  always @(posedge clk)
    sub_fault_latched <= \$29 ;
  (* src = "/home/runner/workspace/hardware/ret.py:93" *)
  always @(posedge clk)
    cload_e_gt <= \$30 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    ret_state <= \$31 ;
  (* src = "/home/runner/workspace/hardware/ret.py:65" *)
  always @(posedge clk)
    return_cap <= \$32 ;
  (* src = "/home/runner/workspace/hardware/ret.py:89" *)
  always @(posedge clk)
    heap_base_latched <= \$33 ;
  (* src = "/home/runner/workspace/hardware/ret.py:90" *)
  always @(posedge clk)
    thread_base_latched <= \$34 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$35  = sto_latched;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          if (mem_rd_valid) begin
            \$35  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$36  = frame_word;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (mem_rd_valid) begin
            \$36  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$37  = return_pc_latched;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (mem_rd_valid) begin
            (* full_case = 32'd1 *)
            if (\$25 ) begin
            end else begin
              \$37  = mem_rd_data[30:16];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$38  = prev_sto_latched;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (mem_rd_valid) begin
            (* full_case = 32'd1 *)
            if (\$25 ) begin
            end else begin
              \$38  = mem_rd_data[15:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    nia_set = 1'h0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          nia_set = 1'h1;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          nia_set = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    nia_value = 32'd0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          nia_value = lambda_pc;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          nia_value = { 14'h0000, \$9  };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    lambda_clear = 1'h0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          lambda_clear = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    local_cr_rd_en = 1'h0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          local_cr_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    mem_rd_addr = 32'd0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          mem_rd_addr = heap_base_latched;
      4'h9:
          mem_rd_addr = \$5 [31:0];
      4'ha:
          mem_rd_addr = \$8 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    mem_rd_en = 1'h0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          mem_rd_en = 1'h1;
      4'h9:
          mem_rd_en = 1'h1;
      4'ha:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    mem_wr_addr = 32'd0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          mem_wr_addr = heap_base_latched;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    mem_wr_data = 32'd0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          mem_wr_data = { 16'h0000, prev_sto_latched };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    mem_wr_en = 1'h0;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$26  = fault_valid;
    casez (ret_state)
      4'h0:
          \$26  = 1'h0;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          if (is_null_cap) begin
          end else if (\$22 ) begin
            \$26  = 1'h1;
          end
      4'h7:
          if (cr5_null) begin
            \$26  = 1'h1;
          end else if (\$23 ) begin
            \$26  = 1'h1;
          end else if (\$24 ) begin
            \$26  = 1'h1;
          end else if (cr12_null) begin
            \$26  = 1'h1;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (mem_rd_valid) begin
            if (\$25 ) begin
              \$26  = 1'h1;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$27  = fault_type;
    casez (ret_state)
      4'h0:
          \$27  = 5'h00;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          if (is_null_cap) begin
          end else if (\$22 ) begin
            \$27  = 5'h06;
          end
      4'h7:
          if (cr5_null) begin
            \$27  = 5'h07;
          end else if (\$23 ) begin
            \$27  = 5'h01;
          end else if (\$24 ) begin
            \$27  = 5'h02;
          end else if (cr12_null) begin
            \$27  = 5'h07;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (mem_rd_valid) begin
            if (\$25 ) begin
              \$27  = 5'h12;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$28  = sub_done_latched;
    casez (ret_state)
      4'h0:
          \$28  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$29  = sub_fault_latched;
    casez (ret_state)
      4'h0:
          \$29  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$30  = cload_e_gt;
    casez (ret_state)
      4'h0:
          \$30  = 32'd0;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          if (mem_rd_valid) begin
            \$30  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$31  = ret_state;
    casez (ret_state)
      4'h0:
          if (return_start) begin
            (* full_case = 32'd1 *)
            if (lambda_active) begin
              \$31  = 4'h1;
            end else begin
              \$31  = 4'h2;
            end
          end
      4'h1:
          \$31  = 4'h3;
      4'h2:
          \$31  = 4'h4;
      4'h4:
          (* full_case = 32'd1 *)
          if (is_null_cap) begin
            \$31  = 4'h5;
          end else if (\$22 ) begin
            \$31  = 4'h6;
          end else begin
            \$31  = 4'h7;
          end
      4'h7:
          (* full_case = 32'd1 *)
          if (cr5_null) begin
            \$31  = 4'h6;
          end else if (\$23 ) begin
            \$31  = 4'h6;
          end else if (\$24 ) begin
            \$31  = 4'h6;
          end else if (cr12_null) begin
            \$31  = 4'h6;
          end else begin
            \$31  = 4'h8;
          end
      4'h8:
          if (mem_rd_valid) begin
            \$31  = 4'h9;
          end
      4'h9:
          if (mem_rd_valid) begin
            (* full_case = 32'd1 *)
            if (\$25 ) begin
              \$31  = 4'h6;
            end else begin
              \$31  = 4'ha;
            end
          end
      4'ha:
          if (mem_rd_valid) begin
            \$31  = 4'hb;
          end
      4'hb:
          \$31  = 4'hc;
      4'hc:
          \$31  = 4'h3;
      4'h3:
          \$31  = 4'h0;
      4'h5:
          \$31  = 4'h0;
      4'h6:
          \$31  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$32  = return_cap;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          \$32  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$33  = heap_base_latched;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          \$33  = cr5_heap[63:32];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$65 ) begin end
    \$34  = thread_base_latched;
    casez (ret_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          \$34  = cr12_thread[63:32];
    endcase
  end
  assign frame_sz = frame_word[31];
  assign frame_ret_pc = frame_word[30:16];
  assign frame_prev_sto = frame_word[15:0];
  assign local_mem_rd_addr = mem_rd_addr;
  assign local_mem_rd_en = mem_rd_en;
  assign local_mem_wr_addr = mem_wr_addr;
  assign local_mem_wr_data = mem_wr_data;
  assign local_mem_wr_en = mem_wr_en;
  assign mload_start = 1'h0;
  assign mload_cr_src = 4'h0;
  assign mload_cr_dst = 4'h0;
  assign mload_index = 16'h0000;
  assign mload_direct = 1'h0;
  assign mload_direct_gt = 32'd0;
  assign mload_m_elevated = 1'h0;
  assign cr_wr_addr = 4'h0;
  assign cr_wr_data = 96'h000000000000000000000000;
  assign cr_wr_en = 1'h0;
  assign callee_egt_latched = cload_e_gt;
  assign fault_flag = fault_valid;
  assign fault_latched = fault_type;
  
  assign \return_cap.word0_gt  = return_cap[31:0];
  assign \return_cap.word0_gt.slot_id  = return_cap[15:0];
  assign \return_cap.word0_gt.gt_seq  = return_cap[24:16];
  assign \return_cap.word0_gt.gt_type  = return_cap[26:25];
  assign \return_cap.word0_gt.dom  = return_cap[27];
  assign \return_cap.word0_gt.perm  = return_cap[30:28];
  assign \return_cap.word0_gt.b_flag  = return_cap[31];
  assign \return_cap.word1_location  = return_cap[63:32];
  assign \return_cap.word2_w2  = return_cap[95:64];
  assign \cr5_heap.word0_gt  = cr5_heap[31:0];
  assign \cr5_heap.word0_gt.slot_id  = cr5_heap[15:0];
  assign \cr5_heap.word0_gt.gt_seq  = cr5_heap[24:16];
  assign \cr5_heap.word0_gt.gt_type  = cr5_heap[26:25];
  assign \cr5_heap.word0_gt.dom  = cr5_heap[27];
  assign \cr5_heap.word0_gt.perm  = cr5_heap[30:28];
  assign \cr5_heap.word0_gt.b_flag  = cr5_heap[31];
  assign \cr5_heap.word1_location  = cr5_heap[63:32];
  assign \cr5_heap.word2_w2  = cr5_heap[95:64];
  assign \cr12_thread.word0_gt  = cr12_thread[31:0];
  assign \cr12_thread.word0_gt.slot_id  = cr12_thread[15:0];
  assign \cr12_thread.word0_gt.gt_seq  = cr12_thread[24:16];
  assign \cr12_thread.word0_gt.gt_type  = cr12_thread[26:25];
  assign \cr12_thread.word0_gt.dom  = cr12_thread[27];
  assign \cr12_thread.word0_gt.perm  = cr12_thread[30:28];
  assign \cr12_thread.word0_gt.b_flag  = cr12_thread[31];
  assign \cr12_thread.word1_location  = cr12_thread[63:32];
  assign \cr12_thread.word2_w2  = cr12_thread[95:64];
  assign \cr_wr_data.word0_gt  = 32'd0;
  assign \cr_wr_data.word0_gt.slot_id  = 16'h0000;
  assign \cr_wr_data.word0_gt.gt_seq  = 9'h000;
  assign \cr_wr_data.word0_gt.gt_type  = 2'h0;
  assign \cr_wr_data.word0_gt.dom  = 1'h0;
  assign \cr_wr_data.word0_gt.perm  = 3'h0;
  assign \cr_wr_data.word0_gt.b_flag  = 1'h0;
  assign \cr_wr_data.word1_location  = 32'd0;
  assign \cr_wr_data.word2_w2  = 32'd0;
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \$4  = { 1'h0, \$3 , 2'h0 };
  assign \$7  = { 1'h0, \$6 , 2'h0 };
  assign \$9  = { 1'h0, return_pc_latched, 2'h0 };
endmodule

(* src = "/home/runner/workspace/hardware/save.py:36" *)
(* generator = "Amaranth" *)
module \top.core.u_save (clk, mem_rd_valid, save_start, cr_rd_data, save_busy, cr15_namespace, cr_rd_addr, save_fault, fault_type, mem_rd_addr, mem_rd_en, mem_wr_en, mem_wr_addr, mem_wr_data, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$66  = 0;
  wire \$1 ;
  reg \$10 ;
  reg [2:0] \$11 ;
  reg [95:0] \$12 ;
  reg [95:0] \$13 ;
  reg \$14 ;
  wire \$2 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  reg \$7 ;
  reg [3:0] \$8 ;
  reg \$9 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [95:0] \cr15_namespace$13 ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [31:0] \cr15_namespace$13.word0_gt ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire \cr15_namespace$13.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire \cr15_namespace$13.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [8:0] \cr15_namespace$13.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [1:0] \cr15_namespace$13.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [2:0] \cr15_namespace$13.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [15:0] \cr15_namespace$13.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [31:0] \cr15_namespace$13.word1_location ;
  (* src = "/home/runner/workspace/hardware/save.py:33" *)
  wire [31:0] \cr15_namespace$13.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/save.py:13" *)
  wire [3:0] cr_dst;
  (* src = "/home/runner/workspace/hardware/save.py:20" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/save.py:21" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/save.py:12" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/save.py:52" *)
  wire dst_in_range;
  (* init = 96'h000000000000000000000000 *)
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [95:0] dst_reg_latched;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [31:0] \dst_reg_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire \dst_reg_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire \dst_reg_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [8:0] \dst_reg_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [1:0] \dst_reg_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [2:0] \dst_reg_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [15:0] \dst_reg_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [31:0] \dst_reg_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  wire [31:0] \dst_reg_latched.word2_w2 ;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/save.py:45" *)
  wire fault_latched;
  (* src = "/home/runner/workspace/hardware/save.py:46" *)
  output [3:0] fault_type;
  reg [3:0] fault_type = 4'h0;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/save.py:46" *)
  wire [3:0] fault_type_latched;
  (* src = "/home/runner/workspace/hardware/save.py:14" *)
  wire [15:0] index;
  (* src = "/home/runner/workspace/hardware/msave.py:27" *)
  output [31:0] mem_rd_addr;
  wire [31:0] mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/msave.py:27" *)
  wire [31:0] \mem_rd_addr$25 ;
  (* src = "/home/runner/workspace/hardware/save.py:30" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/save.py:30" *)
  wire [31:0] \mem_rd_data$15 ;
  (* src = "/home/runner/workspace/hardware/msave.py:28" *)
  output mem_rd_en;
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/msave.py:28" *)
  wire \mem_rd_en$27 ;
  (* src = "/home/runner/workspace/hardware/save.py:31" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/save.py:31" *)
  wire \mem_rd_valid$17 ;
  (* src = "/home/runner/workspace/hardware/msave.py:22" *)
  output [31:0] mem_wr_addr;
  wire [31:0] mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/msave.py:22" *)
  wire [31:0] \mem_wr_addr$19 ;
  (* src = "/home/runner/workspace/hardware/msave.py:23" *)
  output [31:0] mem_wr_data;
  wire [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/msave.py:23" *)
  wire [31:0] \mem_wr_data$21 ;
  (* src = "/home/runner/workspace/hardware/msave.py:25" *)
  wire mem_wr_done;
  (* src = "/home/runner/workspace/hardware/save.py:26" *)
  wire \mem_wr_done$11 ;
  (* src = "/home/runner/workspace/hardware/msave.py:24" *)
  output mem_wr_en;
  wire mem_wr_en;
  (* src = "/home/runner/workspace/hardware/msave.py:24" *)
  wire \mem_wr_en$23 ;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/save.py:15" *)
  output save_busy;
  wire save_busy;
  (* src = "/home/runner/workspace/hardware/save.py:16" *)
  wire save_complete;
  (* src = "/home/runner/workspace/hardware/save.py:45" *)
  output save_fault;
  reg save_fault = 1'h0;
  (* src = "/home/runner/workspace/hardware/save.py:11" *)
  input save_start;
  wire save_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] save_wrapper_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  reg [95:0] src_reg_latched = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire [31:0] \src_reg_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire \src_reg_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire \src_reg_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire [8:0] \src_reg_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire [1:0] \src_reg_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire [2:0] \src_reg_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire [15:0] \src_reg_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire [31:0] \src_reg_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  wire [31:0] \src_reg_latched.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/msave.py:18" *)
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/save.py:49" *)
  reg sub_done_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  reg [95:0] sub_dst_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [31:0] \sub_dst_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire \sub_dst_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire \sub_dst_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [8:0] \sub_dst_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [1:0] \sub_dst_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [2:0] \sub_dst_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [15:0] \sub_dst_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [31:0] \sub_dst_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [31:0] \sub_dst_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/msave.py:19" *)
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/save.py:50" *)
  reg sub_fault_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/msave.py:20" *)
  wire [3:0] sub_fault_type;
  (* src = "/home/runner/workspace/hardware/msave.py:16" *)
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/msave.py:15" *)
  wire [31:0] sub_src_gt;
  (* src = "/home/runner/workspace/hardware/msave.py:13" *)
  reg sub_start = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/save.py:47" *)
  wire \sub_start$3 ;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/save.py:48" *)
  wire sub_start_reg;
  assign dst_in_range = \port$5930$0 [22:19] <= (* src = "/home/runner/workspace/hardware/save.py:53" *) 3'h6;
  assign save_busy = ~ (* src = "/home/runner/workspace/hardware/save.py:115" *) \$1 ;
  assign save_complete = \$5  & (* src = "/home/runner/workspace/hardware/save.py:116" *) sub_done_latched;
  assign \$1  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) save_wrapper_state;
  assign \$2  = save_wrapper_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$3  = save_wrapper_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$4  = save_wrapper_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$5  = save_wrapper_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$6  = ~ (* src = "/home/runner/workspace/hardware/save.py:85" *) dst_in_range;
  (* src = "/home/runner/workspace/hardware/save.py:45" *)
  always @(posedge clk)
    save_fault <= \$7 ;
  (* src = "/home/runner/workspace/hardware/save.py:46" *)
  always @(posedge clk)
    fault_type <= \$8 ;
  (* src = "/home/runner/workspace/hardware/save.py:49" *)
  always @(posedge clk)
    sub_done_latched <= \$9 ;
  (* src = "/home/runner/workspace/hardware/save.py:50" *)
  always @(posedge clk)
    sub_fault_latched <= \$10 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    save_wrapper_state <= \$11 ;
  (* src = "/home/runner/workspace/hardware/save.py:43" *)
  always @(posedge clk)
    sub_dst_cap <= \$12 ;
  (* src = "/home/runner/workspace/hardware/save.py:44" *)
  always @(posedge clk)
    src_reg_latched <= \$13 ;
  (* src = "/home/runner/workspace/hardware/save.py:48" *)
  always @(posedge clk)
    sub_start <= \$14 ;
  (* src = "/home/runner/workspace/hardware/save.py:41" *)
  \top.core.u_save.u_msave  u_msave (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .mem_rd_addr(mem_rd_addr),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(mem_rd_en),
    .mem_rd_valid(mem_rd_valid),
    .mem_wr_addr(mem_wr_addr),
    .mem_wr_data(mem_wr_data),
    .mem_wr_en(mem_wr_en),
    .\port$5930$0 (\port$5930$0 [14:0]),
    .sub_done(sub_done),
    .sub_dst_cap(sub_dst_cap),
    .sub_fault(sub_fault),
    .sub_fault_type(sub_fault_type),
    .sub_src_gt(src_reg_latched[31:0]),
    .sub_start(sub_start)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    cr_rd_addr = 4'h0;
    casez (save_wrapper_state)
      3'h0:
          /* empty */;
      3'h1:
          cr_rd_addr = \port$5930$0 [22:19];
      3'h2:
          cr_rd_addr = \port$5930$0 [18:15];
      3'h3:
          cr_rd_addr = \port$5930$0 [18:15];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$7  = save_fault;
    casez (save_wrapper_state)
      3'h0:
          \$7  = 1'h0;
      3'h1:
          if (\$6 ) begin
            \$7  = 1'h1;
          end
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (sub_fault) begin
            \$7  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$8  = fault_type;
    casez (save_wrapper_state)
      3'h0:
          \$8  = 4'h0;
      3'h1:
          if (\$6 ) begin
            \$8  = 4'h5;
          end
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (sub_fault) begin
            \$8  = sub_fault_type;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$9  = sub_done_latched;
    casez (save_wrapper_state)
      3'h0:
          \$9  = 1'h0;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (sub_done) begin
            \$9  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$10  = sub_fault_latched;
    casez (save_wrapper_state)
      3'h0:
          \$10  = 1'h0;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (sub_fault) begin
            \$10  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$11  = save_wrapper_state;
    casez (save_wrapper_state)
      3'h0:
          if (save_start) begin
            \$11  = 3'h1;
          end
      3'h1:
          (* full_case = 32'd1 *)
          if (\$6 ) begin
            \$11  = 3'h0;
          end else begin
            \$11  = 3'h2;
          end
      3'h2:
          \$11  = 3'h3;
      3'h3:
          \$11  = 3'h4;
      3'h4:
          if (sub_done_latched) begin
            \$11  = 3'h0;
          end else if (sub_fault_latched) begin
            \$11  = 3'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$12  = sub_dst_cap;
    casez (save_wrapper_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          \$12  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$13  = src_reg_latched;
    casez (save_wrapper_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          \$13  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$66 ) begin end
    \$14  = sub_start;
    casez (save_wrapper_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          \$14  = 1'h1;
      3'h4:
          \$14  = 1'h0;
    endcase
  end
  assign cr_dst = \port$5930$0 [22:19];
  assign \sub_start$3  = sub_start;
  assign dst_reg_latched = sub_dst_cap;
  assign sub_src_gt = src_reg_latched[31:0];
  assign sub_index = { 1'h0, \port$5930$0 [14:0] };
  assign index = { 1'h0, \port$5930$0 [14:0] };
  assign mem_wr_done = 1'h1;
  assign \mem_wr_done$11  = 1'h1;
  assign \cr15_namespace$13  = cr15_namespace;
  assign \mem_rd_data$15  = mem_rd_data;
  assign \mem_rd_valid$17  = mem_rd_valid;
  assign \mem_wr_addr$19  = mem_wr_addr;
  assign \mem_wr_data$21  = mem_wr_data;
  assign \mem_wr_en$23  = mem_wr_en;
  assign \mem_rd_addr$25  = mem_rd_addr;
  assign \mem_rd_en$27  = mem_rd_en;
  assign sub_start_reg = sub_start;
  assign cr_src = \port$5930$0 [18:15];
  assign fault_latched = save_fault;
  assign fault_type_latched = fault_type;
  
  assign \sub_dst_cap.word0_gt  = sub_dst_cap[31:0];
  assign \sub_dst_cap.word0_gt.slot_id  = sub_dst_cap[15:0];
  assign \sub_dst_cap.word0_gt.gt_seq  = sub_dst_cap[24:16];
  assign \sub_dst_cap.word0_gt.gt_type  = sub_dst_cap[26:25];
  assign \sub_dst_cap.word0_gt.dom  = sub_dst_cap[27];
  assign \sub_dst_cap.word0_gt.perm  = sub_dst_cap[30:28];
  assign \sub_dst_cap.word0_gt.b_flag  = sub_dst_cap[31];
  assign \sub_dst_cap.word1_location  = sub_dst_cap[63:32];
  assign \sub_dst_cap.word2_w2  = sub_dst_cap[95:64];
  assign \dst_reg_latched.word0_gt  = sub_dst_cap[31:0];
  assign \dst_reg_latched.word0_gt.slot_id  = sub_dst_cap[15:0];
  assign \dst_reg_latched.word0_gt.gt_seq  = sub_dst_cap[24:16];
  assign \dst_reg_latched.word0_gt.gt_type  = sub_dst_cap[26:25];
  assign \dst_reg_latched.word0_gt.dom  = sub_dst_cap[27];
  assign \dst_reg_latched.word0_gt.perm  = sub_dst_cap[30:28];
  assign \dst_reg_latched.word0_gt.b_flag  = sub_dst_cap[31];
  assign \dst_reg_latched.word1_location  = sub_dst_cap[63:32];
  assign \dst_reg_latched.word2_w2  = sub_dst_cap[95:64];
  assign \src_reg_latched.word0_gt  = src_reg_latched[31:0];
  assign \src_reg_latched.word0_gt.slot_id  = src_reg_latched[15:0];
  assign \src_reg_latched.word0_gt.gt_seq  = src_reg_latched[24:16];
  assign \src_reg_latched.word0_gt.gt_type  = src_reg_latched[26:25];
  assign \src_reg_latched.word0_gt.dom  = src_reg_latched[27];
  assign \src_reg_latched.word0_gt.perm  = src_reg_latched[30:28];
  assign \src_reg_latched.word0_gt.b_flag  = src_reg_latched[31];
  assign \src_reg_latched.word1_location  = src_reg_latched[63:32];
  assign \src_reg_latched.word2_w2  = src_reg_latched[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$13.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$13.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$13.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$13.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$13.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$13.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$13.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$13.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$13.word2_w2  = cr15_namespace[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
endmodule

(* src = "/home/runner/workspace/hardware/msave.py:35" *)
(* generator = "Amaranth" *)
module \top.core.u_save.u_msave (clk, mem_rd_valid, sub_fault, sub_done, cr15_namespace, sub_dst_cap, sub_src_gt, sub_start, mem_rd_addr, mem_rd_en, mem_wr_en, mem_wr_addr, mem_wr_data, sub_fault_type, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$67  = 0;
  wire [18:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [32:0] \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  reg [95:0] \$25 ;
  reg [31:0] \$26 ;
  reg [15:0] \$27 ;
  reg [3:0] \$28 ;
  reg [3:0] \$29 ;
  wire [22:0] \$3 ;
  reg [31:0] \$30 ;
  reg [31:0] \$31 ;
  reg [31:0] \$32 ;
  wire [32:0] \$4 ;
  wire [31:0] \$5 ;
  wire [32:0] \$6 ;
  wire [32:0] \$7 ;
  wire \$8 ;
  wire \$9 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$32 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/msave.py:71" *)
  wire [31:0] computed_integrity;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/msave.py:32" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  reg [95:0] dst_cap_reg = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire [31:0] \dst_cap_reg.word0_gt ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire \dst_cap_reg.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire \dst_cap_reg.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire [8:0] \dst_cap_reg.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire [1:0] \dst_cap_reg.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire [2:0] \dst_cap_reg.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire [15:0] \dst_cap_reg.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire [31:0] \dst_cap_reg.word1_location ;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  wire [31:0] \dst_cap_reg.word2_w2 ;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/msave.py:40" *)
  wire [3:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/msave.py:68" *)
  wire gt_seq_match;
  (* src = "/home/runner/workspace/hardware/msave.py:51" *)
  wire index_in_bounds;
  (* src = "/home/runner/workspace/hardware/msave.py:39" *)
  reg [15:0] index_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/msave.py:27" *)
  output [31:0] mem_rd_addr;
  reg [31:0] mem_rd_addr;
  (* src = "/home/runner/workspace/hardware/msave.py:29" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/msave.py:28" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/msave.py:30" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/msave.py:22" *)
  output [31:0] mem_wr_addr;
  reg [31:0] mem_wr_addr;
  (* src = "/home/runner/workspace/hardware/msave.py:23" *)
  output [31:0] mem_wr_data;
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/msave.py:25" *)
  wire mem_wr_done;
  (* src = "/home/runner/workspace/hardware/msave.py:24" *)
  output mem_wr_en;
  reg mem_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] msave_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/msave.py:58" *)
  wire [31:0] ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/msave.py:66" *)
  reg [31:0] ns_integrity_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/msave.py:61" *)
  reg [31:0] ns_location_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/msave.py:62" *)
  reg [31:0] ns_w1_reg = 32'd0;
  input [14:0] \port$5930$0 ;
  wire [14:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/msave.py:74" *)
  wire seal_ok;
  (* src = "/home/runner/workspace/hardware/msave.py:38" *)
  reg [31:0] src_gt_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/msave.py:17" *)
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/msave.py:18" *)
  output sub_done;
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  input [95:0] sub_dst_cap;
  wire [95:0] sub_dst_cap;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [31:0] \sub_dst_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire \sub_dst_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire \sub_dst_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [8:0] \sub_dst_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [1:0] \sub_dst_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [2:0] \sub_dst_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [15:0] \sub_dst_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [31:0] \sub_dst_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/msave.py:14" *)
  wire [31:0] \sub_dst_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/msave.py:19" *)
  output sub_fault;
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/msave.py:40" *)
  output [3:0] sub_fault_type;
  reg [3:0] sub_fault_type = 4'h0;
  (* src = "/home/runner/workspace/hardware/msave.py:16" *)
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/msave.py:15" *)
  input [31:0] sub_src_gt;
  wire [31:0] sub_src_gt;
  (* src = "/home/runner/workspace/hardware/msave.py:13" *)
  input sub_start;
  wire sub_start;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  (* src = "/home/runner/workspace/hardware/msave.py:54" *)
  wire [31:0] write_addr;
  assign index_in_bounds = index_reg < (* src = "/home/runner/workspace/hardware/msave.py:52" *) dst_cap_reg[79:64];
  assign \$2  = dst_cap_reg[63:32] + (* src = "/home/runner/workspace/hardware/msave.py:55" *) \$1 ;
  assign \$4  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/msave.py:59" *) \$3 ;
  assign gt_seq_match = src_gt_reg[24:16] == (* src = "/home/runner/workspace/hardware/msave.py:69" *) ns_w1_reg[29:21];
  assign \$5  = { ns_location_reg[24:0], ns_location_reg[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign seal_ok = computed_integrity == (* src = "/home/runner/workspace/hardware/msave.py:75" *) ns_integrity_reg;
  assign \$6  = \$4 [31:0] + (* src = "/home/runner/workspace/hardware/msave.py:127" *) 3'h4;
  assign \$7  = \$4 [31:0] + (* src = "/home/runner/workspace/hardware/msave.py:140" *) 4'h8;
  assign sub_busy = ~ (* src = "/home/runner/workspace/hardware/msave.py:173" *) \$8 ;
  assign \$8  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) msave_state;
  assign \$9  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign sub_fault = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$12  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$13  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$14  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$15  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$16  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$17  = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign sub_done = msave_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/msave.py:89" *) dst_cap_reg[31];
  assign \$19  = dst_cap_reg[27] & (* src = "/home/runner/workspace/hardware/msave.py:49" *) dst_cap_reg[29];
  assign \$20  = ~ (* src = "/home/runner/workspace/hardware/msave.py:96" *) \$19 ;
  assign \$21  = ~ (* src = "/home/runner/workspace/hardware/msave.py:103" *) index_in_bounds;
  assign \$22  = ~ (* src = "/home/runner/workspace/hardware/msave.py:110" *) src_gt_reg[31];
  assign \$23  = ~ (* src = "/home/runner/workspace/hardware/msave.py:148" *) gt_seq_match;
  assign \$24  = ~ (* src = "/home/runner/workspace/hardware/msave.py:151" *) seal_ok;
  (* src = "/home/runner/workspace/hardware/msave.py:37" *)
  always @(posedge clk)
    dst_cap_reg <= \$25 ;
  (* src = "/home/runner/workspace/hardware/msave.py:38" *)
  always @(posedge clk)
    src_gt_reg <= \$26 ;
  (* src = "/home/runner/workspace/hardware/msave.py:39" *)
  always @(posedge clk)
    index_reg <= \$27 ;
  (* src = "/home/runner/workspace/hardware/msave.py:40" *)
  always @(posedge clk)
    sub_fault_type <= \$28 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    msave_state <= \$29 ;
  (* src = "/home/runner/workspace/hardware/msave.py:61" *)
  always @(posedge clk)
    ns_location_reg <= \$30 ;
  (* src = "/home/runner/workspace/hardware/msave.py:62" *)
  always @(posedge clk)
    ns_w1_reg <= \$31 ;
  (* src = "/home/runner/workspace/hardware/msave.py:66" *)
  always @(posedge clk)
    ns_integrity_reg <= \$32 ;
  assign \$auto$rtlil.cc:2739:Not$32  = ~ { \$5 [31:30], \$5 [28:25], \$5 [23], \$5 [21], \$5 [19:18], \$5 [16:15], \$5 [13:9], \$5 [7:5], \$5 [3:0] };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    mem_rd_addr = 32'd0;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          mem_rd_addr = \$4 [31:0];
      4'h7:
          mem_rd_addr = \$6 [31:0];
      4'h8:
          mem_rd_addr = \$7 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    mem_rd_en = 1'h0;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          mem_rd_en = 1'h1;
      4'h7:
          mem_rd_en = 1'h1;
      4'h8:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    mem_wr_en = 1'h0;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    mem_wr_addr = 32'd0;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_addr = \$2 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    mem_wr_data = 32'd0;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_data = src_gt_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$25  = dst_cap_reg;
    casez (msave_state)
      4'h0:
          if (sub_start) begin
            \$25  = sub_dst_cap;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$26  = src_gt_reg;
    casez (msave_state)
      4'h0:
          if (sub_start) begin
            \$26  = sub_src_gt;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$27  = index_reg;
    casez (msave_state)
      4'h0:
          if (sub_start) begin
            \$27  = { 1'h0, \port$5930$0  };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$28  = sub_fault_type;
    casez (msave_state)
      4'h0:
          if (sub_start) begin
            \$28  = 4'h0;
          end
      4'h1:
          if (\$18 ) begin
            \$28  = 4'he;
          end
      4'h3:
          if (\$20 ) begin
            \$28  = 4'h5;
          end
      4'h4:
          if (\$21 ) begin
            \$28  = 4'h8;
          end
      4'h5:
          if (\$22 ) begin
            \$28  = 4'h7;
          end
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (\$23 ) begin
            \$28  = 4'h9;
          end else if (\$24 ) begin
            \$28  = 4'ha;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$29  = msave_state;
    casez (msave_state)
      4'h0:
          if (sub_start) begin
            \$29  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (\$18 ) begin
            \$29  = 4'h2;
          end else begin
            \$29  = 4'h3;
          end
      4'h3:
          (* full_case = 32'd1 *)
          if (\$20 ) begin
            \$29  = 4'h2;
          end else begin
            \$29  = 4'h4;
          end
      4'h4:
          (* full_case = 32'd1 *)
          if (\$21 ) begin
            \$29  = 4'h2;
          end else begin
            \$29  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$22 ) begin
            \$29  = 4'h2;
          end else begin
            \$29  = 4'h6;
          end
      4'h6:
          if (mem_rd_valid) begin
            \$29  = 4'h7;
          end
      4'h7:
          if (mem_rd_valid) begin
            \$29  = 4'h8;
          end
      4'h8:
          if (mem_rd_valid) begin
            \$29  = 4'h9;
          end
      4'h9:
          (* full_case = 32'd1 *)
          if (\$23 ) begin
            \$29  = 4'h2;
          end else if (\$24 ) begin
            \$29  = 4'h2;
          end else begin
            \$29  = 4'ha;
          end
      4'ha:
          \$29  = 4'hb;
      4'hb:
          \$29  = 4'h0;
      4'h2:
          \$29  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$30  = ns_location_reg;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (mem_rd_valid) begin
            \$30  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$31  = ns_w1_reg;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          if (mem_rd_valid) begin
            \$31  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$67 ) begin end
    \$32  = ns_integrity_reg;
    casez (msave_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          if (mem_rd_valid) begin
            \$32  = mem_rd_data;
          end
    endcase
  end
  assign write_addr = \$2 [31:0];
  assign ns_entry_addr = \$4 [31:0];
  assign w0_rot = { ns_location_reg[24:0], ns_location_reg[31:25] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign fault_type_reg = sub_fault_type;
  
  assign sub_index = { 1'h0, \port$5930$0  };
  assign mem_wr_done = 1'h1;
  assign \dst_cap_reg.word0_gt  = dst_cap_reg[31:0];
  assign \dst_cap_reg.word0_gt.slot_id  = dst_cap_reg[15:0];
  assign \dst_cap_reg.word0_gt.gt_seq  = dst_cap_reg[24:16];
  assign \dst_cap_reg.word0_gt.gt_type  = dst_cap_reg[26:25];
  assign \dst_cap_reg.word0_gt.dom  = dst_cap_reg[27];
  assign \dst_cap_reg.word0_gt.perm  = dst_cap_reg[30:28];
  assign \dst_cap_reg.word0_gt.b_flag  = dst_cap_reg[31];
  assign \dst_cap_reg.word1_location  = dst_cap_reg[63:32];
  assign \dst_cap_reg.word2_w2  = dst_cap_reg[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \sub_dst_cap.word0_gt  = sub_dst_cap[31:0];
  assign \sub_dst_cap.word0_gt.slot_id  = sub_dst_cap[15:0];
  assign \sub_dst_cap.word0_gt.gt_seq  = sub_dst_cap[24:16];
  assign \sub_dst_cap.word0_gt.gt_type  = sub_dst_cap[26:25];
  assign \sub_dst_cap.word0_gt.dom  = sub_dst_cap[27];
  assign \sub_dst_cap.word0_gt.perm  = sub_dst_cap[30:28];
  assign \sub_dst_cap.word0_gt.b_flag  = sub_dst_cap[31];
  assign \sub_dst_cap.word1_location  = sub_dst_cap[63:32];
  assign \sub_dst_cap.word2_w2  = sub_dst_cap[95:64];
  assign \$1  = { 1'h0, index_reg, 2'h0 };
  assign \$3  = { 3'h0, src_gt_reg[15:0], 4'h0 };
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = ns_w1_reg[29:0];
  assign { computed_integrity[29], computed_integrity[24], computed_integrity[22], computed_integrity[20], computed_integrity[17], computed_integrity[14], computed_integrity[8], computed_integrity[4] } = { \$5 [29], \$5 [24], \$5 [22], \$5 [20], \$5 [17], \$5 [14], \$5 [8], \$5 [4] };
  assign { computed_integrity[31:30], computed_integrity[28:25], computed_integrity[23], computed_integrity[21], computed_integrity[19:18], computed_integrity[16:15], computed_integrity[13:9], computed_integrity[7:5], computed_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$32 ;
endmodule

(* src = "/home/runner/workspace/hardware/mload.py:88" *)
(* generator = "Amaranth" *)
module \top.core.u_shared_mload (clk, \mem_rd_valid$23 , outform_done_in, outform_fault_in, cr_rd_data, mem_addr, mem_rd_en, sub_busy, sub_fault, outform_start_out, sub_done, sub_start, sub_cr_src, sub_cr_dst, sub_index, sub_direct, sub_direct_gt, sub_m_elevated, cr15_namespace, cr_rd_addr, mem_wr_en, mem_wr_data
, gbit_reset_done, cr_wr_addr, cr_wr_data, cr_wr_en, sub_fault_type, outform_clist_addr, outform_gt_raw, outform_slot_id, outform_fault_type_in, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$68  = 0;
  wire [18:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [32:0] \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  reg [3:0] \$25 ;
  reg [3:0] \$26 ;
  reg [15:0] \$27 ;
  reg \$28 ;
  reg [31:0] \$29 ;
  wire [32:0] \$3 ;
  reg \$30 ;
  reg [95:0] \$31 ;
  reg [4:0] \$32 ;
  reg [3:0] \$33 ;
  reg [95:0] \$34 ;
  reg [31:0] \$35 ;
  reg [31:0] \$36 ;
  reg [15:0] \$37 ;
  reg [31:0] \$38 ;
  wire [32:0] \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/mload.py:115" *)
  wire bounds_ok;
  (* src = "/home/runner/workspace/hardware/mload.py:119" *)
  wire [31:0] clist_gt_addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [95:0] \cr15_namespace$8 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace$8.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace$8.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace$8.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace$8.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  reg [3:0] cr_dst_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  reg [3:0] cr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  reg [31:0] direct_gt_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  reg direct_mode = 1'h0;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:253" *)
  reg [31:0] gbit_cleared_w1;
  (* src = "/home/runner/workspace/hardware/mload.py:66" *)
  output gbit_reset_done;
  reg gbit_reset_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  reg [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  reg [15:0] index_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/mload.py:135" *)
  reg [31:0] local_mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:136" *)
  reg local_mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:138" *)
  wire [31:0] local_mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:137" *)
  wire local_mem_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  reg m_elevated_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  output [31:0] mem_addr;
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  wire [31:0] \mem_addr$12 ;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  wire [31:0] \mem_rd_data$21 ;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  output mem_rd_en;
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  wire \mem_rd_en$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/mload.py:61" *)
  input \mem_rd_valid$23 ;
  wire \mem_rd_valid$23 ;
  (* src = "/home/runner/workspace/hardware/mload.py:138" *)
  output [31:0] mem_wr_data;
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:137" *)
  output mem_wr_en;
  reg mem_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] mload_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:85" *)
  wire [31:0] ns_abstract_gt;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:71" *)
  wire [31:0] \ns_abstract_gt$56 ;
  (* src = "/home/runner/workspace/hardware/mload.py:65" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] \ns_entry_addr_out$25 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:64" *)
  wire [4:0] ns_gate_fault_type;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  reg ns_gate_start;
  (* src = "/home/runner/workspace/hardware/mload.py:125" *)
  wire ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  reg [31:0] ns_w1_saved = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  output [31:0] outform_clist_addr;
  reg [31:0] outform_clist_addr = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  wire [31:0] outform_clist_addr_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:81" *)
  input outform_done_in;
  wire outform_done_in;
  (* src = "/home/runner/workspace/hardware/mload.py:82" *)
  input outform_fault_in;
  wire outform_fault_in;
  (* src = "/home/runner/workspace/hardware/mload.py:83" *)
  input [4:0] outform_fault_type_in;
  wire [4:0] outform_fault_type_in;
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  output [31:0] outform_gt_raw;
  reg [31:0] outform_gt_raw = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  wire [31:0] outform_gt_raw_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  output [15:0] outform_slot_id;
  reg [15:0] outform_slot_id = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  wire [15:0] outform_slot_id_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:76" *)
  output outform_start_out;
  wire outform_start_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  reg [95:0] result_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [8:0] \result_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [1:0] \result_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [2:0] \result_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [15:0] \result_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  reg [95:0] src_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [8:0] \src_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [1:0] \src_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [2:0] \src_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [15:0] \src_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:112" *)
  wire src_is_null;
  (* src = "/home/runner/workspace/hardware/mload.py:44" *)
  output sub_busy;
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  input [3:0] sub_cr_dst;
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  input [3:0] sub_cr_src;
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  input sub_direct;
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  input [31:0] sub_direct_gt;
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  output sub_done;
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  output sub_fault;
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  output [4:0] sub_fault_type;
  reg [4:0] sub_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  input [15:0] sub_index;
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  input sub_m_elevated;
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  input sub_start;
  wire sub_start;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  reg [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  reg thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  reg [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  always @(posedge clk)
    m_elevated_reg <= \$30 ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  always @(posedge clk)
    result_cap <= \$31 ;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  always @(posedge clk)
    sub_fault_type <= \$32 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    mload_state <= \$33 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  always @(posedge clk)
    src_cap <= \$34 ;
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  always @(posedge clk)
    outform_clist_addr <= \$35 ;
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  always @(posedge clk)
    outform_gt_raw <= \$36 ;
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  always @(posedge clk)
    outform_slot_id <= \$37 ;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  always @(posedge clk)
    ns_w1_saved <= \$38 ;
  assign src_is_null = ! (* src = "/home/runner/workspace/hardware/mload.py:113" *) src_cap[26:25];
  assign bounds_ok = index_reg < (* src = "/home/runner/workspace/hardware/mload.py:117" *) src_cap[79:64];
  assign \$2  = src_cap[63:32] + (* src = "/home/runner/workspace/hardware/mload.py:120" *) \$1 ;
  assign ns_index_in_bounds = result_cap[15:0] < (* src = "/home/runner/workspace/hardware/mload.py:126" *) cr15_namespace[79:64];
  assign mem_addr = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:144" *) \mem_addr$12  : local_mem_addr;
  assign mem_rd_en = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:147" *) \mem_rd_en$15  : local_mem_rd_en;
  assign mem_rd_valid = ns_gate_busy & (* src = "/home/runner/workspace/hardware/mload.py:152" *) \mem_rd_valid$23 ;
  assign \$4  = ns_entry_addr_out + (* src = "/home/runner/workspace/hardware/mload.py:256" *) 3'h4;
  assign \$5  = cr_dst_reg <= (* src = "/home/runner/workspace/hardware/mload.py:264" *) 3'h7;
  assign sub_busy = ~ (* src = "/home/runner/workspace/hardware/mload.py:302" *) \$6 ;
  assign ns_abstract_gt = m_elevated_reg ? (* src = "/home/runner/workspace/hardware/mload.py:310" *) \ns_abstract_gt$56  : 32'd0;
  assign \$6  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) mload_state;
  assign \$7  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$8  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$9  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign sub_fault = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$10  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$11  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign outform_start_out = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$12  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$13  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$14  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$15  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign sub_done = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$16  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$17  = src_cap[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) src_cap[28];
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$17 ;
  assign \$19  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) sub_m_elevated;
  assign \$20  = \$18  & (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$19 ;
  assign \$21  = ~ (* src = "/home/runner/workspace/hardware/mload.py:192" *) bounds_ok;
  assign \$22  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:205" *) 2'h3;
  assign \$23  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:212" *) 2'h2;
  assign \$24  = ~ (* src = "/home/runner/workspace/hardware/mload.py:223" *) ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  always @(posedge clk)
    cr_src_reg <= \$25 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  always @(posedge clk)
    cr_dst_reg <= \$26 ;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  always @(posedge clk)
    index_reg <= \$27 ;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  always @(posedge clk)
    direct_mode <= \$28 ;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  always @(posedge clk)
    direct_gt_reg <= \$29 ;
  (* src = "/home/runner/workspace/hardware/mload.py:90" *)
  \top.core.u_shared_mload.u_ns_gate  u_ns_gate (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .gt_word0(gt_word0),
    .mem_addr(\mem_addr$12 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$15 ),
    .mem_rd_valid(mem_rd_valid),
    .ns_abstract_gt(\ns_abstract_gt$56 ),
    .ns_entry_addr(ns_entry_addr_out),
    .ns_gate_busy(ns_gate_busy),
    .ns_gate_done(ns_gate_done),
    .ns_gate_fault(ns_gate_fault),
    .ns_gate_fault_type(ns_gate_fault_type),
    .ns_gate_start(ns_gate_start),
    .raw_base_reg(raw_base),
    .raw_w2_reg(raw_w2)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$31  = result_cap;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$31  = 96'h000000000000000000000000;
          end
      4'h1:
          if (direct_mode) begin
            \$31 [31:0] = direct_gt_reg;
          end
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            \$31 [31:0] = mem_rd_data;
          end
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$31 [63:32] = raw_base;
            \$31 [95:64] = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$32  = sub_fault_type;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$32  = 5'h00;
          end
      4'h1:
          /* empty */;
      4'h3:
          if (src_is_null) begin
            \$32  = 5'h07;
          end else if (\$20 ) begin
            \$32  = 5'h04;
          end
      4'h5:
          if (\$21 ) begin
            \$32  = 5'h08;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
              \$32  = 5'h0b;
            end
          end
      4'h2:
          if (\$24 ) begin
            \$32  = 5'h08;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
            \$32  = ns_gate_fault_type;
          end
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          /* empty */;
      4'h4:
          /* empty */;
      4'h7:
          /* empty */;
      4'hd:
          if (outform_fault_in) begin
            \$32  = outform_fault_type_in;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$33  = mload_state;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$33  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
            \$33  = 4'h2;
          end else begin
            \$33  = 4'h3;
          end
      4'h3:
          (* full_case = 32'd1 *)
          if (src_is_null) begin
            \$33  = 4'h4;
          end else if (\$20 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$21 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h6;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            (* full_case = 32'd1 *)
            if (\$22 ) begin
              \$33  = 4'h4;
            end else if (\$23 ) begin
              \$33  = 4'h7;
            end else begin
              \$33  = 4'h2;
            end
          end
      4'h2:
          (* full_case = 32'd1 *)
          if (\$24 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h8;
          end
      4'h8:
          \$33  = 4'h9;
      4'h9:
          if (ns_gate_fault) begin
            \$33  = 4'h4;
          end else if (ns_gate_done) begin
            \$33  = 4'ha;
          end
      4'ha:
          \$33  = 4'hb;
      4'hb:
          \$33  = 4'hc;
      4'hc:
          \$33  = 4'h0;
      4'h4:
          \$33  = 4'h0;
      4'h7:
          \$33  = 4'hd;
      4'hd:
          if (outform_fault_in) begin
            \$33  = 4'h4;
          end else if (outform_done_in) begin
            \$33  = 4'h6;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$34  = src_cap;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            \$34  = cr_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$35  = outform_clist_addr;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$35  = \$2 [31:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$36  = outform_gt_raw;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$36  = mem_rd_data;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$37  = outform_slot_id;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$37  = mem_rd_data[15:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$38  = ns_w1_saved;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$38  = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    cr_rd_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            cr_rd_addr = cr_src_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    local_mem_addr = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_addr = \$2 [31:0];
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          local_mem_addr = \$4 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    local_mem_rd_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    ns_gate_start = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          ns_gate_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    gt_word0 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          gt_word0 = result_cap[31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    gbit_cleared_w1 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_cleared_w1 = \$3 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    mem_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    mem_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_data = gbit_cleared_w1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    gbit_reset_done = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_reset_done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    thread_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    thread_wr_idx = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_idx = cr_dst_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    thread_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_data = result_cap[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    cr_wr_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_addr = cr_dst_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_data = result_cap;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    cr_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$25  = cr_src_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$25  = sub_cr_src;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$26  = cr_dst_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$26  = sub_cr_dst;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$27  = index_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$27  = sub_index;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$28  = direct_mode;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$28  = sub_direct;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$29  = direct_gt_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$29  = sub_direct_gt;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$68 ) begin end
    \$30  = m_elevated_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$30  = sub_m_elevated;
          end
    endcase
  end
  assign clist_gt_addr = \$2 [31:0];
  assign \cr15_namespace$8  = cr15_namespace;
  assign local_mem_wr_en = mem_wr_en;
  assign local_mem_wr_data = mem_wr_data;
  assign \mem_rd_data$21  = mem_rd_data;
  assign \ns_entry_addr_out$25  = ns_entry_addr_out;
  assign fault_type_reg = sub_fault_type;
  assign outform_gt_raw_reg = outform_gt_raw;
  assign outform_slot_id_reg = outform_slot_id;
  assign outform_clist_addr_reg = outform_clist_addr;
  
  assign \src_cap.word0_gt  = src_cap[31:0];
  assign \src_cap.word0_gt.slot_id  = src_cap[15:0];
  assign \src_cap.word0_gt.gt_seq  = src_cap[24:16];
  assign \src_cap.word0_gt.gt_type  = src_cap[26:25];
  assign \src_cap.word0_gt.dom  = src_cap[27];
  assign \src_cap.word0_gt.perm  = src_cap[30:28];
  assign \src_cap.word0_gt.b_flag  = src_cap[31];
  assign \src_cap.word1_location  = src_cap[63:32];
  assign \src_cap.word2_w2  = src_cap[95:64];
  assign \result_cap.word0_gt  = result_cap[31:0];
  assign \result_cap.word0_gt.slot_id  = result_cap[15:0];
  assign \result_cap.word0_gt.gt_seq  = result_cap[24:16];
  assign \result_cap.word0_gt.gt_type  = result_cap[26:25];
  assign \result_cap.word0_gt.dom  = result_cap[27];
  assign \result_cap.word0_gt.perm  = result_cap[30:28];
  assign \result_cap.word0_gt.b_flag  = result_cap[31];
  assign \result_cap.word1_location  = result_cap[63:32];
  assign \result_cap.word2_w2  = result_cap[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$8.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$8.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$8.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$8.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$8.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$8.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$8.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$8.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$8.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \$1  = { 1'h0, index_reg, 2'h0 };
  assign \$3 [30] = 1'h0;
  assign { \$3 [32:31], \$3 [29:0] } = { 1'h0, ns_w1_saved[31], ns_w1_saved[29:0] };
endmodule

(* src = "/home/runner/workspace/hardware/ns_gate.py:80" *)
(* generator = "Amaranth" *)
module \top.core.u_shared_mload.u_ns_gate (clk, mem_rd_valid, ns_entry_addr, ns_gate_busy, ns_gate_fault, ns_gate_done, cr15_namespace, ns_gate_start, gt_word0, mem_addr, mem_rd_en, raw_base_reg, raw_w2_reg, ns_abstract_gt, ns_gate_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$69  = 0;
  wire [22:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  reg [31:0] \$15 ;
  reg [31:0] \$16 ;
  reg [31:0] \$17 ;
  reg [31:0] \$18 ;
  reg [4:0] \$19 ;
  wire [32:0] \$2 ;
  reg [31:0] \$20 ;
  reg [2:0] \$21 ;
  wire [31:0] \$3 ;
  wire [32:0] \$4 ;
  wire [32:0] \$5 ;
  wire [32:0] \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$30 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:103" *)
  wire [31:0] computed_integrity;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  reg [31:0] gt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:99" *)
  wire gt_seq_match;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  input [31:0] gt_word0;
  wire [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  output [31:0] mem_addr;
  reg [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:76" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  output [31:0] ns_abstract_gt;
  reg [31:0] ns_abstract_gt = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  output [31:0] ns_entry_addr;
  wire [31:0] ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  output ns_gate_busy;
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  output ns_gate_done;
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  output ns_gate_fault;
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  output [4:0] ns_gate_fault_type;
  reg [4:0] ns_gate_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  input ns_gate_start;
  wire ns_gate_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] ns_gate_state = 3'h0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  output [31:0] raw_base_reg;
  reg [31:0] raw_base_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  reg [31:0] raw_integrity_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  output [31:0] raw_w2_reg;
  reg [31:0] raw_w2_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  wire [31:0] raw_w3_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:106" *)
  wire seal_ok;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  assign \$2  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/ns_gate.py:93" *) \$1 ;
  assign gt_seq_match = gt_latched[24:16] == (* src = "/home/runner/workspace/hardware/ns_gate.py:100" *) raw_w2_reg[29:21];
  assign \$3  = { raw_base_reg[24:0], raw_base_reg[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign seal_ok = computed_integrity == (* src = "/home/runner/workspace/hardware/ns_gate.py:107" *) raw_integrity_reg;
  assign \$4  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:135" *) 3'h4;
  assign \$5  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:148" *) 4'h8;
  assign \$6  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:170" *) 4'hc;
  assign ns_gate_busy = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:184" *) \$7 ;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) ns_gate_state;
  assign \$8  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign ns_gate_fault = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$12  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign ns_gate_done = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:156" *) gt_seq_match;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:159" *) seal_ok;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  always @(posedge clk)
    gt_latched <= \$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:86" *)
  always @(posedge clk)
    raw_base_reg <= \$16 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:87" *)
  always @(posedge clk)
    raw_w2_reg <= \$17 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  always @(posedge clk)
    ns_abstract_gt <= \$18 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  always @(posedge clk)
    ns_gate_fault_type <= \$19 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  always @(posedge clk)
    raw_integrity_reg <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    ns_gate_state <= \$21 ;
  assign \$auto$rtlil.cc:2739:Not$30  = ~ { \$3 [31:30], \$3 [28:25], \$3 [23], \$3 [21], \$3 [19:18], \$3 [16:15], \$3 [13:9], \$3 [7:5], \$3 [3:0] };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    mem_addr = 32'd0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_addr = \$2 [31:0];
      3'h2:
          mem_addr = \$4 [31:0];
      3'h3:
          mem_addr = \$5 [31:0];
      3'h4:
          /* empty */;
      3'h6:
          mem_addr = \$6 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    mem_rd_en = 1'h0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_en = 1'h1;
      3'h2:
          mem_rd_en = 1'h1;
      3'h3:
          mem_rd_en = 1'h1;
      3'h4:
          /* empty */;
      3'h6:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    \$15  = gt_latched;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$15  = gt_word0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    \$16  = raw_base_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$16  = 32'd0;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$16  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    \$17  = raw_w2_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$17  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          if (mem_rd_valid) begin
            \$17  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    \$18  = ns_abstract_gt;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$18  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          if (mem_rd_valid) begin
            \$18  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    \$19  = ns_gate_fault_type;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$19  = 5'h00;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (\$13 ) begin
            \$19  = 5'h09;
          end else if (\$14 ) begin
            \$19  = 5'h0a;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    \$20  = raw_integrity_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$20  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          if (mem_rd_valid) begin
            \$20  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$69 ) begin end
    \$21  = ns_gate_state;
    (* full_case = 32'd1 *)
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$21  = 3'h1;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$21  = 3'h2;
          end
      3'h2:
          if (mem_rd_valid) begin
            \$21  = 3'h3;
          end
      3'h3:
          if (mem_rd_valid) begin
            \$21  = 3'h4;
          end
      3'h4:
          (* full_case = 32'd1 *)
          if (\$13 ) begin
            \$21  = 3'h5;
          end else if (\$14 ) begin
            \$21  = 3'h5;
          end else begin
            \$21  = 3'h6;
          end
      3'h6:
          if (mem_rd_valid) begin
            \$21  = 3'h7;
          end
      3'h7:
          \$21  = 3'h0;
      3'h5:
          \$21  = 3'h0;
    endcase
  end
  assign w0_rot = { raw_base_reg[24:0], raw_base_reg[31:25] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign fault_type_reg = ns_gate_fault_type;
  assign raw_base = raw_base_reg;
  assign raw_w2 = raw_w2_reg;
  assign raw_w3_reg = ns_abstract_gt;
  assign ns_entry_addr_out = \$2 [31:0];
  
  assign ns_entry_addr = \$2 [31:0];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \$1  = { 3'h0, gt_latched[15:0], 4'h0 };
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = raw_w2_reg[29:0];
  assign { computed_integrity[29], computed_integrity[24], computed_integrity[22], computed_integrity[20], computed_integrity[17], computed_integrity[14], computed_integrity[8], computed_integrity[4] } = { \$3 [29], \$3 [24], \$3 [22], \$3 [20], \$3 [17], \$3 [14], \$3 [8], \$3 [4] };
  assign { computed_integrity[31:30], computed_integrity[28:25], computed_integrity[23], computed_integrity[21], computed_integrity[19:18], computed_integrity[16:15], computed_integrity[13:9], computed_integrity[7:5], computed_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$30 ;
endmodule

(* src = "/home/runner/workspace/hardware/switch.py:37" *)
(* generator = "Amaranth" *)
module \top.core.u_switch (clk, mem_rd_valid, switch_start, cr_rd_data, cr_rd_addr, switch_busy, cr15_namespace, switch_fault, fault_type, cr_wr_addr, cr_wr_data, cr_wr_en, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$70  = 0;
  wire [4:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  reg \$19 ;
  wire \$2 ;
  reg [3:0] \$20 ;
  reg [3:0] \$21 ;
  reg [95:0] \$22 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [95:0] \cr15_namespace$21 ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [31:0] \cr15_namespace$21.word0_gt ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire \cr15_namespace$21.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire \cr15_namespace$21.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [8:0] \cr15_namespace$21.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [1:0] \cr15_namespace$21.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [2:0] \cr15_namespace$21.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [15:0] \cr15_namespace$21.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [31:0] \cr15_namespace$21.word1_location ;
  (* src = "/home/runner/workspace/hardware/switch.py:25" *)
  wire [31:0] \cr15_namespace$21.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/switch.py:20" *)
  output [3:0] cr_rd_addr;
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  wire [3:0] \cr_rd_addr$44 ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [95:0] \cr_rd_data$19 ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [31:0] \cr_rd_data$19.word0_gt ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire \cr_rd_data$19.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire \cr_rd_data$19.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [8:0] \cr_rd_data$19.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [1:0] \cr_rd_data$19.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [2:0] \cr_rd_data$19.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [15:0] \cr_rd_data$19.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [31:0] \cr_rd_data$19.word1_location ;
  (* src = "/home/runner/workspace/hardware/switch.py:21" *)
  wire [31:0] \cr_rd_data$19.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/switch.py:12" *)
  wire [2:0] cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  wire [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  wire [3:0] \cr_wr_addr$27 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  wire [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [95:0] \cr_wr_data$29 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$29.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$29.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$29.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data$29.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data$29.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data$29.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data$29.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$29.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$29.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/switch.py:23" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  wire cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  wire \cr_wr_en$31 ;
  (* src = "/home/runner/workspace/hardware/switch.py:44" *)
  wire [3:0] dest_cr;
  (* src = "/home/runner/workspace/hardware/switch.py:67" *)
  wire [31:0] expected_sentinel;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/switch.py:48" *)
  wire fault_latched;
  (* src = "/home/runner/workspace/hardware/switch.py:49" *)
  output [3:0] fault_type;
  reg [3:0] fault_type = 4'h0;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/switch.py:49" *)
  wire [3:0] fault_type_latched;
  (* src = "/home/runner/workspace/hardware/switch.py:14" *)
  wire [15:0] index;
  (* src = "/home/runner/workspace/hardware/switch.py:53" *)
  reg [3:0] local_cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/switch.py:52" *)
  reg local_cr_rd_en;
  (* src = "/home/runner/workspace/hardware/switch.py:27" *)
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  wire [31:0] \mem_addr$33 ;
  (* src = "/home/runner/workspace/hardware/switch.py:29" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/switch.py:29" *)
  wire [31:0] \mem_rd_data$23 ;
  (* src = "/home/runner/workspace/hardware/switch.py:28" *)
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  wire \mem_rd_en$35 ;
  (* src = "/home/runner/workspace/hardware/switch.py:30" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/switch.py:30" *)
  wire \mem_rd_valid$25 ;
  input [17:0] \port$5930$0 ;
  wire [17:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/switch.py:74" *)
  wire sentinel_ok;
  (* src = "/home/runner/workspace/hardware/switch.py:55" *)
  wire src_in_range;
  (* src = "/home/runner/workspace/hardware/switch.py:62" *)
  wire src_is_abstract;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  reg [95:0] src_reg_latched = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire [31:0] \src_reg_latched.word0_gt ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire \src_reg_latched.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire \src_reg_latched.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire [8:0] \src_reg_latched.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire [1:0] \src_reg_latched.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire [2:0] \src_reg_latched.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire [15:0] \src_reg_latched.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire [31:0] \src_reg_latched.word1_location ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  wire [31:0] \src_reg_latched.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:44" *)
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:47" *)
  wire [4:0] sub_fault_type;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  reg sub_start;
  (* src = "/home/runner/workspace/hardware/switch.py:50" *)
  wire \sub_start$10 ;
  (* src = "/home/runner/workspace/hardware/switch.py:15" *)
  output switch_busy;
  wire switch_busy;
  (* src = "/home/runner/workspace/hardware/switch.py:16" *)
  wire switch_complete;
  (* src = "/home/runner/workspace/hardware/switch.py:48" *)
  output switch_fault;
  reg switch_fault = 1'h0;
  (* src = "/home/runner/workspace/hardware/switch.py:11" *)
  input switch_start;
  wire switch_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] switch_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/switch.py:13" *)
  wire [2:0] target;
  (* src = "/home/runner/workspace/hardware/switch.py:78" *)
  wire target_valid;
  (* src = "/home/runner/workspace/hardware/switch.py:34" *)
  wire [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  wire [31:0] \thread_wr_data$41 ;
  (* src = "/home/runner/workspace/hardware/switch.py:32" *)
  wire thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  wire \thread_wr_en$37 ;
  (* src = "/home/runner/workspace/hardware/switch.py:33" *)
  wire [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  wire [3:0] \thread_wr_idx$39 ;
  assign \$1  = 4'h8 + (* src = "/home/runner/workspace/hardware/switch.py:45" *) \port$5930$0 [2:0];
  assign src_in_range = \port$5930$0 [17:15] <= (* src = "/home/runner/workspace/hardware/switch.py:56" *) 3'h7;
  assign src_is_abstract = src_reg_latched[26:25] == (* src = "/home/runner/workspace/hardware/switch.py:63" *) 2'h3;
  assign \$2  = \port$5930$0 [2:0] == (* src = "/home/runner/workspace/hardware/switch.py:69" *) 3'h5;
  assign expected_sentinel = \$2  ? (* src = "/home/runner/workspace/hardware/switch.py:69" *) 32'd4294967294 : 32'd4294967295;
  assign sentinel_ok = src_reg_latched[63:32] == (* src = "/home/runner/workspace/hardware/switch.py:75" *) expected_sentinel;
  assign \$3  = \port$5930$0 [2:0] == (* src = "/home/runner/workspace/hardware/switch.py:80" *) 3'h5;
  assign \$4  = \port$5930$0 [2:0] == (* src = "/home/runner/workspace/hardware/switch.py:80" *) 3'h7;
  assign target_valid = \$3  | (* src = "/home/runner/workspace/hardware/switch.py:80" *) \$4 ;
  assign cr_rd_addr = local_cr_rd_en ? (* src = "/home/runner/workspace/hardware/switch.py:108" *) local_cr_rd_addr : \cr_rd_addr$44 ;
  assign switch_busy = ~ (* src = "/home/runner/workspace/hardware/switch.py:173" *) \$5 ;
  assign switch_complete = \$13  & (* src = "/home/runner/workspace/hardware/switch.py:174" *) sub_done;
  assign \$5  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) switch_state;
  assign \$6  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$7  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$8  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$9  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$10  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$11  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$12  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = switch_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/switch.py:119" *) target_valid;
  assign \$15  = ~ (* src = "/home/runner/workspace/hardware/switch.py:127" *) src_in_range;
  assign \$16  = ~ (* src = "/home/runner/workspace/hardware/switch.py:141" *) src_is_abstract;
  assign \$17  = ~ (* src = "/home/runner/workspace/hardware/switch.py:151" *) sentinel_ok;
  assign \$18  = sub_done | (* src = "/home/runner/workspace/hardware/switch.py:169" *) sub_fault;
  (* src = "/home/runner/workspace/hardware/switch.py:48" *)
  always @(posedge clk)
    switch_fault <= \$19 ;
  (* src = "/home/runner/workspace/hardware/switch.py:49" *)
  always @(posedge clk)
    fault_type <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    switch_state <= \$21 ;
  (* src = "/home/runner/workspace/hardware/switch.py:47" *)
  always @(posedge clk)
    src_reg_latched <= \$22 ;
  (* src = "/home/runner/workspace/hardware/switch.py:42" *)
  \top.core.u_switch.u_mload  u_mload (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$44 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(cr_wr_addr),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .mem_addr(mem_addr),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(mem_rd_en),
    .\mem_rd_valid$23 (mem_rd_valid),
    .\port$5930$0 (\port$5930$0 ),
    .sub_busy(sub_busy),
    .sub_cr_dst(\$1 [3:0]),
    .sub_done(sub_done),
    .sub_fault(sub_fault),
    .sub_fault_type(sub_fault_type),
    .sub_start(sub_start),
    .thread_wr_data(thread_wr_data),
    .thread_wr_en(thread_wr_en),
    .thread_wr_idx(thread_wr_idx)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$70 ) begin end
    local_cr_rd_en = 1'h0;
    casez (switch_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          local_cr_rd_en = 1'h1;
      4'h3:
          local_cr_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$70 ) begin end
    local_cr_rd_addr = 4'h0;
    casez (switch_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          local_cr_rd_addr = { 1'h0, \port$5930$0 [17:15] };
      4'h3:
          local_cr_rd_addr = { 1'h0, \port$5930$0 [17:15] };
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$70 ) begin end
    sub_start = 1'h0;
    casez (switch_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          sub_start = 1'h1;
      4'h7:
          sub_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$70 ) begin end
    \$19  = switch_fault;
    casez (switch_state)
      4'h0:
          \$19  = 1'h0;
      4'h1:
          if (\$14 ) begin
            \$19  = 1'h1;
          end
      4'h2:
          if (\$15 ) begin
            \$19  = 1'h1;
          end
      4'h3:
          /* empty */;
      4'h4:
          if (\$16 ) begin
            \$19  = 1'h1;
          end
      4'h5:
          if (\$17 ) begin
            \$19  = 1'h1;
          end
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          if (sub_fault) begin
            \$19  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$70 ) begin end
    \$20  = fault_type;
    casez (switch_state)
      4'h0:
          \$20  = 4'h0;
      4'h1:
          if (\$14 ) begin
            \$20  = 4'hb;
          end
      4'h2:
          if (\$15 ) begin
            \$20  = 4'hb;
          end
      4'h3:
          /* empty */;
      4'h4:
          if (\$16 ) begin
            \$20  = 4'hb;
          end
      4'h5:
          if (\$17 ) begin
            \$20  = 4'hb;
          end
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          if (sub_fault) begin
            \$20  = sub_fault_type[3:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$70 ) begin end
    \$21  = switch_state;
    casez (switch_state)
      4'h0:
          if (switch_start) begin
            \$21  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (\$14 ) begin
            \$21  = 4'h0;
          end else begin
            \$21  = 4'h2;
          end
      4'h2:
          (* full_case = 32'd1 *)
          if (\$15 ) begin
            \$21  = 4'h0;
          end else begin
            \$21  = 4'h3;
          end
      4'h3:
          \$21  = 4'h4;
      4'h4:
          (* full_case = 32'd1 *)
          if (\$16 ) begin
            \$21  = 4'h0;
          end else begin
            \$21  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$17 ) begin
            \$21  = 4'h0;
          end else begin
            \$21  = 4'h6;
          end
      4'h6:
          \$21  = 4'h7;
      4'h7:
          if (sub_busy) begin
            \$21  = 4'h8;
          end
      4'h8:
          if (\$18 ) begin
            \$21  = 4'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$70 ) begin end
    \$22  = src_reg_latched;
    casez (switch_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          \$22  = cr_rd_data;
    endcase
  end
  assign dest_cr = \$1 [3:0];
  assign target = \port$5930$0 [2:0];
  assign cr_src = \port$5930$0 [17:15];
  assign \sub_start$10  = sub_start;
  assign sub_cr_src = { 1'h0, \port$5930$0 [17:15] };
  assign sub_cr_dst = \$1 [3:0];
  assign sub_index = { 1'h0, \port$5930$0 [14:0] };
  assign index = { 1'h0, \port$5930$0 [14:0] };
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign sub_m_elevated = 1'h1;
  assign \cr_rd_data$19  = cr_rd_data;
  assign \cr15_namespace$21  = cr15_namespace;
  assign \mem_rd_data$23  = mem_rd_data;
  assign \mem_rd_valid$25  = mem_rd_valid;
  assign \cr_wr_addr$27  = cr_wr_addr;
  assign \cr_wr_data$29  = cr_wr_data;
  assign \cr_wr_en$31  = cr_wr_en;
  assign \mem_addr$33  = mem_addr;
  assign \mem_rd_en$35  = mem_rd_en;
  assign \thread_wr_en$37  = thread_wr_en;
  assign \thread_wr_idx$39  = thread_wr_idx;
  assign \thread_wr_data$41  = thread_wr_data;
  assign fault_latched = switch_fault;
  assign fault_type_latched = fault_type;
  
  assign \src_reg_latched.word0_gt  = src_reg_latched[31:0];
  assign \src_reg_latched.word0_gt.slot_id  = src_reg_latched[15:0];
  assign \src_reg_latched.word0_gt.gt_seq  = src_reg_latched[24:16];
  assign \src_reg_latched.word0_gt.gt_type  = src_reg_latched[26:25];
  assign \src_reg_latched.word0_gt.dom  = src_reg_latched[27];
  assign \src_reg_latched.word0_gt.perm  = src_reg_latched[30:28];
  assign \src_reg_latched.word0_gt.b_flag  = src_reg_latched[31];
  assign \src_reg_latched.word1_location  = src_reg_latched[63:32];
  assign \src_reg_latched.word2_w2  = src_reg_latched[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$19.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$19.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$19.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$19.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$19.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$19.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$19.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$19.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$19.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$21.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$21.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$21.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$21.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$21.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$21.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$21.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$21.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$21.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_wr_data$29.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data$29.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data$29.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data$29.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data$29.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data$29.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data$29.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data$29.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data$29.word2_w2  = cr_wr_data[95:64];
endmodule

(* src = "/home/runner/workspace/hardware/mload.py:88" *)
(* generator = "Amaranth" *)
module \top.core.u_switch.u_mload (clk, \mem_rd_valid$23 , cr_rd_data, sub_cr_dst, mem_addr, mem_rd_en, sub_busy, sub_fault, sub_done, cr15_namespace, sub_start, cr_rd_addr, thread_wr_en, thread_wr_idx, thread_wr_data, cr_wr_addr, cr_wr_data, cr_wr_en, sub_fault_type, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$71  = 0;
  wire [18:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [32:0] \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  reg [3:0] \$25 ;
  reg [3:0] \$26 ;
  reg [15:0] \$27 ;
  reg \$28 ;
  reg [31:0] \$29 ;
  wire [32:0] \$3 ;
  reg \$30 ;
  reg [95:0] \$31 ;
  reg [4:0] \$32 ;
  reg [3:0] \$33 ;
  reg [95:0] \$34 ;
  reg [31:0] \$35 ;
  reg [31:0] \$36 ;
  reg [15:0] \$37 ;
  reg [31:0] \$38 ;
  wire [32:0] \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/mload.py:115" *)
  wire bounds_ok;
  (* src = "/home/runner/workspace/hardware/mload.py:119" *)
  wire [31:0] clist_gt_addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [95:0] \cr15_namespace$8 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace$8.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace$8.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace$8.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace$8.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  reg [3:0] cr_dst_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  reg [3:0] cr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  reg [31:0] direct_gt_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  reg direct_mode = 1'h0;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:253" *)
  reg [31:0] gbit_cleared_w1;
  (* src = "/home/runner/workspace/hardware/mload.py:66" *)
  reg gbit_reset_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  reg [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  reg [15:0] index_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/mload.py:135" *)
  reg [31:0] local_mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:136" *)
  reg local_mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:138" *)
  wire [31:0] local_mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:137" *)
  wire local_mem_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  reg m_elevated_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  output [31:0] mem_addr;
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  wire [31:0] \mem_addr$12 ;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  wire [31:0] \mem_rd_data$21 ;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  output mem_rd_en;
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  wire \mem_rd_en$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/mload.py:61" *)
  input \mem_rd_valid$23 ;
  wire \mem_rd_valid$23 ;
  (* src = "/home/runner/workspace/hardware/mload.py:63" *)
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:62" *)
  reg mem_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] mload_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:85" *)
  wire [31:0] ns_abstract_gt;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:71" *)
  wire [31:0] \ns_abstract_gt$56 ;
  (* src = "/home/runner/workspace/hardware/mload.py:65" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] \ns_entry_addr_out$25 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:64" *)
  wire [4:0] ns_gate_fault_type;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  reg ns_gate_start;
  (* src = "/home/runner/workspace/hardware/mload.py:125" *)
  wire ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  reg [31:0] ns_w1_saved = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:79" *)
  reg [31:0] outform_clist_addr = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  wire [31:0] outform_clist_addr_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:81" *)
  wire outform_done_in;
  (* src = "/home/runner/workspace/hardware/mload.py:82" *)
  wire outform_fault_in;
  (* src = "/home/runner/workspace/hardware/mload.py:83" *)
  wire [4:0] outform_fault_type_in;
  (* src = "/home/runner/workspace/hardware/mload.py:77" *)
  reg [31:0] outform_gt_raw = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  wire [31:0] outform_gt_raw_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:78" *)
  reg [15:0] outform_slot_id = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  wire [15:0] outform_slot_id_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:76" *)
  wire outform_start_out;
  input [17:0] \port$5930$0 ;
  wire [17:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  reg [95:0] result_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [8:0] \result_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [1:0] \result_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [2:0] \result_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [15:0] \result_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  reg [95:0] src_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [8:0] \src_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [1:0] \src_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [2:0] \src_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [15:0] \src_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:112" *)
  wire src_is_null;
  (* src = "/home/runner/workspace/hardware/mload.py:44" *)
  output sub_busy;
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  input [3:0] sub_cr_dst;
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  output sub_done;
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  output sub_fault;
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  output [4:0] sub_fault_type;
  reg [4:0] sub_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  input sub_start;
  wire sub_start;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  output [31:0] thread_wr_data;
  reg [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  output thread_wr_en;
  reg thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  output [3:0] thread_wr_idx;
  reg [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  always @(posedge clk)
    m_elevated_reg <= \$30 ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  always @(posedge clk)
    result_cap <= \$31 ;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  always @(posedge clk)
    sub_fault_type <= \$32 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    mload_state <= \$33 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  always @(posedge clk)
    src_cap <= \$34 ;
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  always @(posedge clk)
    outform_clist_addr <= \$35 ;
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  always @(posedge clk)
    outform_gt_raw <= \$36 ;
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  always @(posedge clk)
    outform_slot_id <= \$37 ;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  always @(posedge clk)
    ns_w1_saved <= \$38 ;
  assign src_is_null = ! (* src = "/home/runner/workspace/hardware/mload.py:113" *) src_cap[26:25];
  assign bounds_ok = index_reg < (* src = "/home/runner/workspace/hardware/mload.py:117" *) src_cap[79:64];
  assign \$2  = src_cap[63:32] + (* src = "/home/runner/workspace/hardware/mload.py:120" *) \$1 ;
  assign ns_index_in_bounds = result_cap[15:0] < (* src = "/home/runner/workspace/hardware/mload.py:126" *) cr15_namespace[79:64];
  assign mem_addr = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:144" *) \mem_addr$12  : local_mem_addr;
  assign mem_rd_en = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:147" *) \mem_rd_en$15  : local_mem_rd_en;
  assign mem_rd_valid = ns_gate_busy & (* src = "/home/runner/workspace/hardware/mload.py:152" *) \mem_rd_valid$23 ;
  assign \$4  = ns_entry_addr_out + (* src = "/home/runner/workspace/hardware/mload.py:256" *) 3'h4;
  assign \$5  = cr_dst_reg <= (* src = "/home/runner/workspace/hardware/mload.py:264" *) 3'h7;
  assign sub_busy = ~ (* src = "/home/runner/workspace/hardware/mload.py:302" *) \$6 ;
  assign ns_abstract_gt = m_elevated_reg ? (* src = "/home/runner/workspace/hardware/mload.py:310" *) \ns_abstract_gt$56  : 32'd0;
  assign \$6  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) mload_state;
  assign \$7  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$8  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$9  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign sub_fault = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$10  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$11  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign outform_start_out = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$12  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$13  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$14  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$15  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign sub_done = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$16  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$17  = src_cap[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) src_cap[28];
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$17 ;
  assign \$21  = ~ (* src = "/home/runner/workspace/hardware/mload.py:192" *) bounds_ok;
  assign \$22  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:205" *) 2'h3;
  assign \$23  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:212" *) 2'h2;
  assign \$24  = ~ (* src = "/home/runner/workspace/hardware/mload.py:223" *) ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  always @(posedge clk)
    cr_src_reg <= \$25 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  always @(posedge clk)
    cr_dst_reg <= \$26 ;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  always @(posedge clk)
    index_reg <= \$27 ;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  always @(posedge clk)
    direct_mode <= \$28 ;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  always @(posedge clk)
    direct_gt_reg <= \$29 ;
  (* src = "/home/runner/workspace/hardware/mload.py:90" *)
  \top.core.u_switch.u_mload.u_ns_gate  u_ns_gate (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .gt_word0(gt_word0),
    .mem_addr(\mem_addr$12 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$15 ),
    .mem_rd_valid(mem_rd_valid),
    .ns_abstract_gt(\ns_abstract_gt$56 ),
    .ns_entry_addr(ns_entry_addr_out),
    .ns_gate_busy(ns_gate_busy),
    .ns_gate_done(ns_gate_done),
    .ns_gate_fault(ns_gate_fault),
    .ns_gate_fault_type(ns_gate_fault_type),
    .ns_gate_start(ns_gate_start),
    .raw_base_reg(raw_base),
    .raw_w2_reg(raw_w2)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$31  = result_cap;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$31  = 96'h000000000000000000000000;
          end
      4'h1:
          if (direct_mode) begin
            \$31 [31:0] = direct_gt_reg;
          end
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            \$31 [31:0] = mem_rd_data;
          end
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$31 [63:32] = raw_base;
            \$31 [95:64] = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$32  = sub_fault_type;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$32  = 5'h00;
          end
      4'h1:
          /* empty */;
      4'h3:
          if (src_is_null) begin
            \$32  = 5'h07;
          end else if (\$20 ) begin
            \$32  = 5'h04;
          end
      4'h5:
          if (\$21 ) begin
            \$32  = 5'h08;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
              \$32  = 5'h0b;
            end
          end
      4'h2:
          if (\$24 ) begin
            \$32  = 5'h08;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
            \$32  = ns_gate_fault_type;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$33  = mload_state;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$33  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
            \$33  = 4'h2;
          end else begin
            \$33  = 4'h3;
          end
      4'h3:
          (* full_case = 32'd1 *)
          if (src_is_null) begin
            \$33  = 4'h4;
          end else if (\$20 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$21 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h6;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            (* full_case = 32'd1 *)
            if (\$22 ) begin
              \$33  = 4'h4;
            end else if (\$23 ) begin
              \$33  = 4'h7;
            end else begin
              \$33  = 4'h2;
            end
          end
      4'h2:
          (* full_case = 32'd1 *)
          if (\$24 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h8;
          end
      4'h8:
          \$33  = 4'h9;
      4'h9:
          if (ns_gate_fault) begin
            \$33  = 4'h4;
          end else if (ns_gate_done) begin
            \$33  = 4'ha;
          end
      4'ha:
          \$33  = 4'hb;
      4'hb:
          \$33  = 4'hc;
      4'hc:
          \$33  = 4'h0;
      4'h4:
          \$33  = 4'h0;
      4'h7:
          \$33  = 4'hd;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$34  = src_cap;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            \$34  = cr_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$35  = outform_clist_addr;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$35  = \$2 [31:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$36  = outform_gt_raw;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$36  = mem_rd_data;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$37  = outform_slot_id;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$37  = mem_rd_data[15:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$38  = ns_w1_saved;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$38  = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    cr_rd_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            cr_rd_addr = cr_src_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    local_mem_addr = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_addr = \$2 [31:0];
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          local_mem_addr = \$4 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    local_mem_rd_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    ns_gate_start = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          ns_gate_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    gt_word0 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          gt_word0 = result_cap[31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    gbit_cleared_w1 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_cleared_w1 = \$3 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    mem_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    mem_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_data = gbit_cleared_w1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    gbit_reset_done = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_reset_done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    thread_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    thread_wr_idx = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_idx = cr_dst_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    thread_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_data = result_cap[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    cr_wr_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_addr = cr_dst_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_data = result_cap;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    cr_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$25  = cr_src_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$25  = { 1'h0, \port$5930$0 [17:15] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$26  = cr_dst_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$26  = sub_cr_dst;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$27  = index_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$27  = { 1'h0, \port$5930$0 [14:0] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$28  = direct_mode;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$28  = 1'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$29  = direct_gt_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$29  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$71 ) begin end
    \$30  = m_elevated_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$30  = 1'h1;
          end
    endcase
  end
  assign clist_gt_addr = \$2 [31:0];
  assign \cr15_namespace$8  = cr15_namespace;
  assign local_mem_wr_en = mem_wr_en;
  assign local_mem_wr_data = mem_wr_data;
  assign \mem_rd_data$21  = mem_rd_data;
  assign \ns_entry_addr_out$25  = ns_entry_addr_out;
  assign fault_type_reg = sub_fault_type;
  assign outform_gt_raw_reg = outform_gt_raw;
  assign outform_slot_id_reg = outform_slot_id;
  assign outform_clist_addr_reg = outform_clist_addr;
  
  assign sub_cr_src = { 1'h0, \port$5930$0 [17:15] };
  assign sub_index = { 1'h0, \port$5930$0 [14:0] };
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign sub_m_elevated = 1'h1;
  assign outform_fault_in = 1'h0;
  assign outform_done_in = 1'h0;
  assign outform_fault_type_in = 5'h00;
  assign \src_cap.word0_gt  = src_cap[31:0];
  assign \src_cap.word0_gt.slot_id  = src_cap[15:0];
  assign \src_cap.word0_gt.gt_seq  = src_cap[24:16];
  assign \src_cap.word0_gt.gt_type  = src_cap[26:25];
  assign \src_cap.word0_gt.dom  = src_cap[27];
  assign \src_cap.word0_gt.perm  = src_cap[30:28];
  assign \src_cap.word0_gt.b_flag  = src_cap[31];
  assign \src_cap.word1_location  = src_cap[63:32];
  assign \src_cap.word2_w2  = src_cap[95:64];
  assign \result_cap.word0_gt  = result_cap[31:0];
  assign \result_cap.word0_gt.slot_id  = result_cap[15:0];
  assign \result_cap.word0_gt.gt_seq  = result_cap[24:16];
  assign \result_cap.word0_gt.gt_type  = result_cap[26:25];
  assign \result_cap.word0_gt.dom  = result_cap[27];
  assign \result_cap.word0_gt.perm  = result_cap[30:28];
  assign \result_cap.word0_gt.b_flag  = result_cap[31];
  assign \result_cap.word1_location  = result_cap[63:32];
  assign \result_cap.word2_w2  = result_cap[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$8.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$8.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$8.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$8.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$8.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$8.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$8.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$8.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$8.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \$1  = { 1'h0, index_reg, 2'h0 };
  assign \$3 [30] = 1'h0;
  assign { \$3 [32:31], \$3 [29:0] } = { 1'h0, ns_w1_saved[31], ns_w1_saved[29:0] };
  assign \$19  = 1'h0;
  assign \$20  = 1'h0;
endmodule

(* src = "/home/runner/workspace/hardware/ns_gate.py:80" *)
(* generator = "Amaranth" *)
module \top.core.u_switch.u_mload.u_ns_gate (clk, mem_rd_valid, ns_entry_addr, ns_gate_busy, ns_gate_fault, ns_gate_done, cr15_namespace, ns_gate_start, gt_word0, mem_addr, mem_rd_en, raw_base_reg, raw_w2_reg, ns_abstract_gt, ns_gate_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$72  = 0;
  wire [22:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  reg [31:0] \$15 ;
  reg [31:0] \$16 ;
  reg [31:0] \$17 ;
  reg [31:0] \$18 ;
  reg [4:0] \$19 ;
  wire [32:0] \$2 ;
  reg [31:0] \$20 ;
  reg [2:0] \$21 ;
  wire [31:0] \$3 ;
  wire [32:0] \$4 ;
  wire [32:0] \$5 ;
  wire [32:0] \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$26 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:103" *)
  wire [31:0] computed_integrity;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  reg [31:0] gt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:99" *)
  wire gt_seq_match;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  input [31:0] gt_word0;
  wire [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  output [31:0] mem_addr;
  reg [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:76" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  output [31:0] ns_abstract_gt;
  reg [31:0] ns_abstract_gt = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  output [31:0] ns_entry_addr;
  wire [31:0] ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  output ns_gate_busy;
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  output ns_gate_done;
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  output ns_gate_fault;
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  output [4:0] ns_gate_fault_type;
  reg [4:0] ns_gate_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  input ns_gate_start;
  wire ns_gate_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] ns_gate_state = 3'h0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  output [31:0] raw_base_reg;
  reg [31:0] raw_base_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  reg [31:0] raw_integrity_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  output [31:0] raw_w2_reg;
  reg [31:0] raw_w2_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  wire [31:0] raw_w3_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:106" *)
  wire seal_ok;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  assign \$2  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/ns_gate.py:93" *) \$1 ;
  assign gt_seq_match = gt_latched[24:16] == (* src = "/home/runner/workspace/hardware/ns_gate.py:100" *) raw_w2_reg[29:21];
  assign \$3  = { raw_base_reg[24:0], raw_base_reg[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign seal_ok = computed_integrity == (* src = "/home/runner/workspace/hardware/ns_gate.py:107" *) raw_integrity_reg;
  assign \$4  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:135" *) 3'h4;
  assign \$5  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:148" *) 4'h8;
  assign \$6  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:170" *) 4'hc;
  assign ns_gate_busy = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:184" *) \$7 ;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) ns_gate_state;
  assign \$8  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign ns_gate_fault = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$12  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign ns_gate_done = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:156" *) gt_seq_match;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:159" *) seal_ok;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  always @(posedge clk)
    gt_latched <= \$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:86" *)
  always @(posedge clk)
    raw_base_reg <= \$16 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:87" *)
  always @(posedge clk)
    raw_w2_reg <= \$17 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  always @(posedge clk)
    ns_abstract_gt <= \$18 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  always @(posedge clk)
    ns_gate_fault_type <= \$19 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  always @(posedge clk)
    raw_integrity_reg <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    ns_gate_state <= \$21 ;
  assign \$auto$rtlil.cc:2739:Not$26  = ~ { \$3 [31:30], \$3 [28:25], \$3 [23], \$3 [21], \$3 [19:18], \$3 [16:15], \$3 [13:9], \$3 [7:5], \$3 [3:0] };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    mem_addr = 32'd0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_addr = \$2 [31:0];
      3'h2:
          mem_addr = \$4 [31:0];
      3'h3:
          mem_addr = \$5 [31:0];
      3'h4:
          /* empty */;
      3'h6:
          mem_addr = \$6 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    mem_rd_en = 1'h0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_en = 1'h1;
      3'h2:
          mem_rd_en = 1'h1;
      3'h3:
          mem_rd_en = 1'h1;
      3'h4:
          /* empty */;
      3'h6:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    \$15  = gt_latched;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$15  = gt_word0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    \$16  = raw_base_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$16  = 32'd0;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$16  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    \$17  = raw_w2_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$17  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          if (mem_rd_valid) begin
            \$17  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    \$18  = ns_abstract_gt;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$18  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          if (mem_rd_valid) begin
            \$18  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    \$19  = ns_gate_fault_type;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$19  = 5'h00;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (\$13 ) begin
            \$19  = 5'h09;
          end else if (\$14 ) begin
            \$19  = 5'h0a;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    \$20  = raw_integrity_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$20  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          if (mem_rd_valid) begin
            \$20  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$72 ) begin end
    \$21  = ns_gate_state;
    (* full_case = 32'd1 *)
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$21  = 3'h1;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$21  = 3'h2;
          end
      3'h2:
          if (mem_rd_valid) begin
            \$21  = 3'h3;
          end
      3'h3:
          if (mem_rd_valid) begin
            \$21  = 3'h4;
          end
      3'h4:
          (* full_case = 32'd1 *)
          if (\$13 ) begin
            \$21  = 3'h5;
          end else if (\$14 ) begin
            \$21  = 3'h5;
          end else begin
            \$21  = 3'h6;
          end
      3'h6:
          if (mem_rd_valid) begin
            \$21  = 3'h7;
          end
      3'h7:
          \$21  = 3'h0;
      3'h5:
          \$21  = 3'h0;
    endcase
  end
  assign w0_rot = { raw_base_reg[24:0], raw_base_reg[31:25] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign fault_type_reg = ns_gate_fault_type;
  assign raw_base = raw_base_reg;
  assign raw_w2 = raw_w2_reg;
  assign raw_w3_reg = ns_abstract_gt;
  assign ns_entry_addr_out = \$2 [31:0];
  
  assign ns_entry_addr = \$2 [31:0];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \$1  = { 3'h0, gt_latched[15:0], 4'h0 };
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = raw_w2_reg[29:0];
  assign { computed_integrity[29], computed_integrity[24], computed_integrity[22], computed_integrity[20], computed_integrity[17], computed_integrity[14], computed_integrity[8], computed_integrity[4] } = { \$3 [29], \$3 [24], \$3 [22], \$3 [20], \$3 [17], \$3 [14], \$3 [8], \$3 [4] };
  assign { computed_integrity[31:30], computed_integrity[28:25], computed_integrity[23], computed_integrity[21], computed_integrity[19:18], computed_integrity[16:15], computed_integrity[13:9], computed_integrity[7:5], computed_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$26 ;
endmodule

(* src = "/home/runner/workspace/hardware/tperm.py:41" *)
(* generator = "Amaranth" *)
module \top.core.u_tperm (clk, cr_rd_data, tperm_busy, tperm_complete, cr_rd_addr, cr_wr_addr, cr_wr_data, cr_wr_en, tperm_fault, fault_type, tperm_z_result, preset, \port$5930$15 , tperm_start);
  reg \$auto$verilog_backend.cc:2355:dump_module$73  = 0;
  wire [5:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  reg \$16 ;
  reg [3:0] \$17 ;
  reg [3:0] \$18 ;
  reg [3:0] \$19 ;
  wire [5:0] \$2 ;
  reg [95:0] \$20 ;
  reg \$21 ;
  reg [95:0] \$22 ;
  wire \$3 ;
  wire \$4 ;
  wire [2:0] \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:102" *)
  wire can_only_reduce;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/tperm.py:33" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/tperm.py:34" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:12" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/tperm.py:11" *)
  wire [3:0] cr_target;
  (* src = "/home/runner/workspace/hardware/tperm.py:36" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/tperm.py:37" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:38" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/tperm.py:51" *)
  wire fault_flag;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/tperm.py:52" *)
  wire [3:0] fault_latched;
  (* src = "/home/runner/workspace/hardware/tperm.py:52" *)
  output [3:0] fault_type;
  reg [3:0] fault_type = 4'h0;
  (* src = "/home/runner/workspace/hardware/tperm.py:58" *)
  reg is_exact;
  (* src = "/home/runner/workspace/hardware/tperm.py:59" *)
  reg is_frame;
  (* src = "/home/runner/workspace/hardware/tperm.py:57" *)
  reg is_reserved;
  (* src = "/home/runner/workspace/hardware/tperm.py:56" *)
  reg [5:0] new_perms;
  input [7:0] \port$5930$15 ;
  wire [7:0] \port$5930$15 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:13" *)
  input [3:0] preset;
  wire [3:0] preset;
  (* src = "/home/runner/workspace/hardware/tperm.py:50" *)
  reg [3:0] preset_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  reg [95:0] ref_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire [31:0] \ref_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire \ref_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire \ref_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire [8:0] \ref_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire [1:0] \ref_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire [2:0] \ref_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire [15:0] \ref_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire [31:0] \ref_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  wire [31:0] \ref_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  reg [95:0] result_cap;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire [31:0] \result_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire \result_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire \result_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire [8:0] \result_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire [1:0] \result_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire [2:0] \result_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire [15:0] \result_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire [31:0] \result_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/tperm.py:173" *)
  wire [31:0] \result_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:158" *)
  reg result_dom;
  (* src = "/home/runner/workspace/hardware/tperm.py:157" *)
  reg [5:0] result_logical;
  (* src = "/home/runner/workspace/hardware/tperm.py:159" *)
  reg [2:0] result_perm3;
  (* src = "/home/runner/workspace/hardware/tperm.py:18" *)
  wire stack_has_frame;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  reg [95:0] target_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire [31:0] \target_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire \target_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire \target_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire [8:0] \target_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire [1:0] \target_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire [2:0] \target_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire [15:0] \target_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire [31:0] \target_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  wire [31:0] \target_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:64" *)
  wire [5:0] target_logical;
  (* src = "/home/runner/workspace/hardware/tperm.py:20" *)
  output tperm_busy;
  wire tperm_busy;
  (* src = "/home/runner/workspace/hardware/tperm.py:21" *)
  output tperm_complete;
  wire tperm_complete;
  (* src = "/home/runner/workspace/hardware/tperm.py:51" *)
  output tperm_fault;
  reg tperm_fault = 1'h0;
  (* src = "/home/runner/workspace/hardware/tperm.py:10" *)
  input tperm_start;
  wire tperm_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] tperm_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/tperm.py:53" *)
  output tperm_z_result;
  reg tperm_z_result = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/tperm.py:53" *)
  wire z_result_reg;
  assign target_logical = target_cap[27] ? (* src = "/home/runner/workspace/hardware/tperm.py:66" *) { target_cap[30:28], 3'h0 } : { 3'h0, target_cap[30:28] };
  assign \$1  = new_perms & (* src = "/home/runner/workspace/hardware/tperm.py:103" *) target_logical;
  assign can_only_reduce = \$1  == (* src = "/home/runner/workspace/hardware/tperm.py:103" *) new_perms;
  assign \$2  = new_perms & (* src = "/home/runner/workspace/hardware/tperm.py:160" *) target_logical;
  assign \$3  = result_logical[3] | (* src = "/home/runner/workspace/hardware/tperm.py:163" *) result_logical[4];
  assign \$4  = \$3  | (* src = "/home/runner/workspace/hardware/tperm.py:163" *) result_logical[5];
  assign \$5  = result_dom ? (* src = "/home/runner/workspace/hardware/tperm.py:170" *) result_logical[5:3] : result_logical[2:0];
  assign tperm_busy = ~ (* src = "/home/runner/workspace/hardware/tperm.py:193" *) \$6 ;
  assign \$6  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) tperm_state;
  assign \$7  = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$8  = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$9  = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$10  = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$11  = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$12  = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign tperm_complete = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = tperm_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/tperm.py:125" *) can_only_reduce;
  assign \$15  = target_cap[31:0] != (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/lib/data.py:906" *) ref_cap[31:0];
  (* src = "/home/runner/workspace/hardware/tperm.py:51" *)
  always @(posedge clk)
    tperm_fault <= \$16 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:52" *)
  always @(posedge clk)
    fault_type <= \$17 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:50" *)
  always @(posedge clk)
    preset_reg <= \$18 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    tperm_state <= \$19 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:43" *)
  always @(posedge clk)
    target_cap <= \$20 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:53" *)
  always @(posedge clk)
    tperm_z_result <= \$21 ;
  (* src = "/home/runner/workspace/hardware/tperm.py:47" *)
  always @(posedge clk)
    ref_cap <= \$22 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    (* full_case = 32'd1 *)
    casez (preset_reg)
      4'h0:
          new_perms = 6'h00;
      4'h1:
          new_perms = 6'h01;
      4'h2:
          new_perms = 6'h03;
      4'h3:
          new_perms = 6'h04;
      4'h4:
          new_perms = 6'h05;
      4'h5:
          new_perms = 6'h07;
      4'h6:
          new_perms = 6'h08;
      4'h7:
          new_perms = 6'h10;
      4'h8:
          new_perms = 6'h20;
      4'h9:
          new_perms = 6'h18;
      4'he:
          new_perms = 6'h00;
      4'hd:
          new_perms = 6'h00;
      default:
          new_perms = 6'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    is_exact = 1'h0;
    casez (preset_reg)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'he:
          is_exact = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    is_frame = 1'h0;
    casez (preset_reg)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'he:
          /* empty */;
      4'hd:
          is_frame = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    is_reserved = 1'h0;
    (* full_case = 32'd1 *)
    casez (preset_reg)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h3:
          /* empty */;
      4'h4:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h7:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'he:
          /* empty */;
      4'hd:
          /* empty */;
      default:
          is_reserved = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    cr_rd_addr = 4'h0;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          cr_rd_addr = \port$5930$15 [7:4];
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          cr_rd_addr = \port$5930$15 [3:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    result_logical = 6'h00;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          /* empty */;
      4'h6:
          result_logical = \$2 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    result_dom = 1'h0;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          /* empty */;
      4'h6:
          result_dom = \$4 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    result_perm3 = 3'h0;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          /* empty */;
      4'h6:
          result_perm3 = \$5 ;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    result_cap = 96'h000000000000000000000000;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          /* empty */;
      4'h6:
        begin
          { result_cap[95:31], result_cap[26:0] } = { target_cap[95:31], target_cap[26:0] };
          result_cap[27] = result_dom;
          result_cap[30:28] = result_perm3;
        end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    cr_wr_addr = 4'h0;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          /* empty */;
      4'h6:
          cr_wr_addr = \port$5930$15 [7:4];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          /* empty */;
      4'h6:
          cr_wr_data = result_cap;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    cr_wr_en = 1'h0;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          /* empty */;
      4'h6:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    \$16  = tperm_fault;
    casez (tperm_state)
      4'h0:
          \$16  = 1'h0;
      4'h1:
          /* empty */;
      4'h2:
          if (is_reserved) begin
            \$16  = 1'h1;
          end else if (is_exact) begin
          end else if (is_frame) begin
          end else if (\$14 ) begin
            \$16  = 1'h1;
          end
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          if (\$15 ) begin
            \$16  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    \$17  = fault_type;
    casez (tperm_state)
      4'h0:
          \$17  = 4'h0;
      4'h1:
          /* empty */;
      4'h2:
          if (is_reserved) begin
            \$17  = 4'hc;
          end else if (is_exact) begin
          end else if (is_frame) begin
          end else if (\$14 ) begin
            \$17  = 4'hd;
          end
      4'h5:
          /* empty */;
      4'h4:
          /* empty */;
      4'h8:
          if (\$15 ) begin
            \$17  = 4'he;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    \$18  = preset_reg;
    casez (tperm_state)
      4'h0:
          if (tperm_start) begin
            \$18  = preset;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    \$19  = tperm_state;
    casez (tperm_state)
      4'h0:
          if (tperm_start) begin
            \$19  = 4'h1;
          end
      4'h1:
          \$19  = 4'h2;
      4'h2:
          (* full_case = 32'd1 *)
          if (is_reserved) begin
            \$19  = 4'h3;
          end else if (is_exact) begin
            \$19  = 4'h4;
          end else if (is_frame) begin
            \$19  = 4'h5;
          end else if (\$14 ) begin
            \$19  = 4'h3;
          end else begin
            \$19  = 4'h6;
          end
      4'h5:
          \$19  = 4'h7;
      4'h4:
          \$19  = 4'h8;
      4'h8:
          (* full_case = 32'd1 *)
          if (\$15 ) begin
            \$19  = 4'h3;
          end else begin
            \$19  = 4'h7;
          end
      4'h6:
          \$19  = 4'h7;
      4'h7:
          \$19  = 4'h0;
      4'h3:
          \$19  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    \$20  = target_cap;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          \$20  = cr_rd_data;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    \$21  = tperm_z_result;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          \$21  = 1'h0;
      4'h4:
          /* empty */;
      4'h8:
          (* full_case = 32'd1 *)
          if (\$15 ) begin
          end else begin
            \$21  = 1'h1;
          end
      4'h6:
          \$21  = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$73 ) begin end
    \$22  = ref_cap;
    casez (tperm_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h2:
          /* empty */;
      4'h5:
          /* empty */;
      4'h4:
          \$22  = cr_rd_data;
    endcase
  end
  assign cr_target = \port$5930$15 [7:4];
  assign cr_src = \port$5930$15 [3:0];
  assign fault_flag = tperm_fault;
  assign fault_latched = fault_type;
  assign z_result_reg = tperm_z_result;
  
  assign stack_has_frame = 1'h0;
  assign \target_cap.word0_gt  = target_cap[31:0];
  assign \target_cap.word0_gt.slot_id  = target_cap[15:0];
  assign \target_cap.word0_gt.gt_seq  = target_cap[24:16];
  assign \target_cap.word0_gt.gt_type  = target_cap[26:25];
  assign \target_cap.word0_gt.dom  = target_cap[27];
  assign \target_cap.word0_gt.perm  = target_cap[30:28];
  assign \target_cap.word0_gt.b_flag  = target_cap[31];
  assign \target_cap.word1_location  = target_cap[63:32];
  assign \target_cap.word2_w2  = target_cap[95:64];
  assign \result_cap.word0_gt  = result_cap[31:0];
  assign \result_cap.word0_gt.slot_id  = result_cap[15:0];
  assign \result_cap.word0_gt.gt_seq  = result_cap[24:16];
  assign \result_cap.word0_gt.gt_type  = result_cap[26:25];
  assign \result_cap.word0_gt.dom  = result_cap[27];
  assign \result_cap.word0_gt.perm  = result_cap[30:28];
  assign \result_cap.word0_gt.b_flag  = result_cap[31];
  assign \result_cap.word1_location  = result_cap[63:32];
  assign \result_cap.word2_w2  = result_cap[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \ref_cap.word0_gt  = ref_cap[31:0];
  assign \ref_cap.word0_gt.slot_id  = ref_cap[15:0];
  assign \ref_cap.word0_gt.gt_seq  = ref_cap[24:16];
  assign \ref_cap.word0_gt.gt_type  = ref_cap[26:25];
  assign \ref_cap.word0_gt.dom  = ref_cap[27];
  assign \ref_cap.word0_gt.perm  = ref_cap[30:28];
  assign \ref_cap.word0_gt.b_flag  = ref_cap[31];
  assign \ref_cap.word1_location  = ref_cap[63:32];
  assign \ref_cap.word2_w2  = ref_cap[95:64];
endmodule

(* src = "/home/runner/workspace/hardware/fused_unit.py:390" *)
(* generator = "Amaranth" *)
module \top.core.u_xloadlambda (clk, mem_rd_valid, start, cr_rd_data, cr_rd_addr, busy, lazy_resolve_irq, pet_name_rd_data, cr15_namespace, nia_set, nia_value, fault, fault_type, lazy_resolve_slot, cr_wr_addr, cr_wr_data, cr_wr_en, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$74  = 0;
  wire \$1 ;
  reg \$10 ;
  reg [3:0] \$11 ;
  reg \$12 ;
  reg \$13 ;
  reg \$14 ;
  reg [15:0] \$15 ;
  reg [2:0] \$16 ;
  reg [95:0] \$17 ;
  wire \$2 ;
  wire \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:353" *)
  output busy;
  wire busy;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:354" *)
  wire complete;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [95:0] \cr15_namespace$16 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [31:0] \cr15_namespace$16.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire \cr15_namespace$16.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire \cr15_namespace$16.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [8:0] \cr15_namespace$16.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [1:0] \cr15_namespace$16.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [2:0] \cr15_namespace$16.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [15:0] \cr15_namespace$16.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [31:0] \cr15_namespace$16.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:363" *)
  wire [31:0] \cr15_namespace$16.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:351" *)
  wire [3:0] cr_dst;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:358" *)
  output [3:0] cr_rd_addr;
  wire [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  wire [3:0] \cr_rd_addr$39 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [95:0] \cr_rd_data$14 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [31:0] \cr_rd_data$14.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire \cr_rd_data$14.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire \cr_rd_data$14.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [8:0] \cr_rd_data$14.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [1:0] \cr_rd_data$14.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [2:0] \cr_rd_data$14.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [15:0] \cr_rd_data$14.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [31:0] \cr_rd_data$14.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:359" *)
  wire [31:0] \cr_rd_data$14.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:350" *)
  wire [3:0] cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  wire [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  wire [3:0] \cr_wr_addr$22 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  wire [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [95:0] \cr_wr_data$24 ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$24.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$24.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data$24.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data$24.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data$24.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data$24.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data$24.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$24.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data$24.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:361" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  wire cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  wire \cr_wr_en$26 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:396" *)
  output fault;
  reg fault = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:396" *)
  wire fault_latched;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:397" *)
  output [3:0] fault_type;
  reg [3:0] fault_type = 4'h0;
  (* init = 4'h0 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:397" *)
  wire [3:0] fault_type_latched;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:352" *)
  wire [15:0] index;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:401" *)
  wire [15:0] index_latched;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:409" *)
  wire is_null;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:380" *)
  output lazy_resolve_irq;
  wire lazy_resolve_irq;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:386" *)
  output [15:0] lazy_resolve_slot;
  reg [15:0] lazy_resolve_slot = 16'h0000;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  reg [95:0] loaded_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire [31:0] \loaded_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire \loaded_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire \loaded_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire [8:0] \loaded_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire [1:0] \loaded_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire [2:0] \loaded_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire [15:0] \loaded_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire [31:0] \loaded_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  wire [31:0] \loaded_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:404" *)
  reg [3:0] local_cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:403" *)
  reg local_cr_rd_en;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:365" *)
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  wire [31:0] \mem_addr$28 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:367" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:367" *)
  wire [31:0] \mem_rd_data$18 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:366" *)
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  wire \mem_rd_en$30 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:368" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:368" *)
  wire \mem_rd_valid$20 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:374" *)
  output nia_set;
  reg nia_set;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:375" *)
  output [31:0] nia_value;
  reg [31:0] nia_value;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:386" *)
  wire [15:0] pet_name_rd_addr;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:387" *)
  input pet_name_rd_data;
  wire pet_name_rd_data;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:349" *)
  input start;
  wire start;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:399" *)
  reg sub_done_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:400" *)
  reg sub_fault_latched = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:47" *)
  wire [4:0] sub_fault_type;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  reg sub_start = 1'h0;
  (* init = 1'h0 *)
  (* src = "/home/runner/workspace/hardware/fused_unit.py:398" *)
  wire sub_start_reg;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:372" *)
  wire [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  wire [31:0] \thread_wr_data$36 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:370" *)
  wire thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  wire \thread_wr_en$32 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:371" *)
  wire [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  wire [3:0] \thread_wr_idx$34 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] xloadlambda_state = 3'h0;
  assign is_null = ! (* src = "/home/runner/workspace/hardware/fused_unit.py:410" *) loaded_cap[26:25];
  assign sub_m_elevated = \port$5930$0 [18:15] == (* src = "/home/runner/workspace/hardware/fused_unit.py:418" *) 3'h6;
  assign cr_rd_addr = local_cr_rd_en ? (* src = "/home/runner/workspace/hardware/fused_unit.py:438" *) local_cr_rd_addr : \cr_rd_addr$39 ;
  assign busy = ~ (* src = "/home/runner/workspace/hardware/fused_unit.py:513" *) \$1 ;
  assign \$1  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) xloadlambda_state;
  assign \$2  = xloadlambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$3  = xloadlambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$4  = xloadlambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$5  = xloadlambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign lazy_resolve_irq = xloadlambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$6  = xloadlambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign complete = xloadlambda_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$7  = ~ (* src = "/home/runner/workspace/hardware/perm_check.py:27" *) loaded_cap[27];
  assign \$8  = \$7  & (* src = "/home/runner/workspace/hardware/perm_check.py:27" *) loaded_cap[30];
  assign \$9  = ~ (* src = "/home/runner/workspace/hardware/fused_unit.py:484" *) \$8 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:396" *)
  always @(posedge clk)
    fault <= \$10 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:397" *)
  always @(posedge clk)
    fault_type <= \$11 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:399" *)
  always @(posedge clk)
    sub_done_latched <= \$12 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:400" *)
  always @(posedge clk)
    sub_fault_latched <= \$13 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:398" *)
  always @(posedge clk)
    sub_start <= \$14 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:401" *)
  always @(posedge clk)
    lazy_resolve_slot <= \$15 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    xloadlambda_state <= \$16 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:395" *)
  always @(posedge clk)
    loaded_cap <= \$17 ;
  (* src = "/home/runner/workspace/hardware/fused_unit.py:393" *)
  \top.core.u_xloadlambda.u_mload  u_mload (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .cr_rd_addr(\cr_rd_addr$39 ),
    .cr_rd_data(cr_rd_data),
    .cr_wr_addr(cr_wr_addr),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .mem_addr(mem_addr),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(mem_rd_en),
    .\mem_rd_valid$23 (mem_rd_valid),
    .\port$5930$0 (\port$5930$0 ),
    .sub_done(sub_done),
    .sub_fault(sub_fault),
    .sub_fault_type(sub_fault_type),
    .sub_m_elevated(sub_m_elevated),
    .sub_start(sub_start),
    .thread_wr_data(thread_wr_data),
    .thread_wr_en(thread_wr_en),
    .thread_wr_idx(thread_wr_idx)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    local_cr_rd_en = 1'h0;
    casez (xloadlambda_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          local_cr_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    local_cr_rd_addr = 4'h0;
    casez (xloadlambda_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          local_cr_rd_addr = \port$5930$0 [22:19];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    nia_set = 1'h0;
    casez (xloadlambda_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          nia_set = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    nia_value = 32'd0;
    casez (xloadlambda_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          nia_value = loaded_cap[63:32];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$10  = fault;
    casez (xloadlambda_state)
      3'h0:
          \$10  = 1'h0;
      3'h1:
          if (sub_fault) begin
            \$10  = 1'h1;
          end
      3'h3:
          /* empty */;
      3'h4:
          if (is_null) begin
            (* full_case = 32'd1 *)
            if (pet_name_rd_data) begin
            end else begin
              \$10  = 1'h1;
            end
          end else if (\$9 ) begin
            \$10  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$11  = fault_type;
    casez (xloadlambda_state)
      3'h0:
          \$11  = 4'h0;
      3'h1:
          if (sub_fault) begin
            \$11  = sub_fault_type[3:0];
          end
      3'h3:
          /* empty */;
      3'h4:
          if (is_null) begin
            (* full_case = 32'd1 *)
            if (pet_name_rd_data) begin
            end else begin
              \$11  = 4'h7;
            end
          end else if (\$9 ) begin
            \$11  = 4'h3;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$12  = sub_done_latched;
    casez (xloadlambda_state)
      3'h0:
          \$12  = 1'h0;
      3'h1:
          if (sub_done) begin
            \$12  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$13  = sub_fault_latched;
    casez (xloadlambda_state)
      3'h0:
          \$13  = 1'h0;
      3'h1:
          if (sub_fault) begin
            \$13  = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$14  = sub_start;
    casez (xloadlambda_state)
      3'h0:
          if (start) begin
            \$14  = 1'h1;
          end
      3'h1:
          \$14  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$15  = lazy_resolve_slot;
    casez (xloadlambda_state)
      3'h0:
          if (start) begin
            \$15  = { 1'h0, \port$5930$0 [14:0] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$16  = xloadlambda_state;
    (* full_case = 32'd1 *)
    casez (xloadlambda_state)
      3'h0:
          if (start) begin
            \$16  = 3'h1;
          end
      3'h1:
          if (sub_fault_latched) begin
            \$16  = 3'h2;
          end else if (sub_done_latched) begin
            \$16  = 3'h3;
          end
      3'h3:
          \$16  = 3'h4;
      3'h4:
          (* full_case = 32'd1 *)
          if (is_null) begin
            (* full_case = 32'd1 *)
            if (pet_name_rd_data) begin
              \$16  = 3'h5;
            end else begin
              \$16  = 3'h2;
            end
          end else if (\$9 ) begin
            \$16  = 3'h2;
          end else begin
            \$16  = 3'h6;
          end
      3'h6:
          \$16  = 3'h7;
      3'h7:
          \$16  = 3'h0;
      3'h2:
          \$16  = 3'h0;
      3'h5:
          \$16  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$74 ) begin end
    \$17  = loaded_cap;
    casez (xloadlambda_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h3:
          \$17  = cr_rd_data;
    endcase
  end
  assign sub_start_reg = sub_start;
  assign sub_cr_src = \port$5930$0 [18:15];
  assign cr_src = \port$5930$0 [18:15];
  assign sub_cr_dst = \port$5930$0 [22:19];
  assign cr_dst = \port$5930$0 [22:19];
  assign sub_index = { 1'h0, \port$5930$0 [14:0] };
  assign index = { 1'h0, \port$5930$0 [14:0] };
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign \cr_rd_data$14  = cr_rd_data;
  assign \cr15_namespace$16  = cr15_namespace;
  assign \mem_rd_data$18  = mem_rd_data;
  assign \mem_rd_valid$20  = mem_rd_valid;
  assign \cr_wr_addr$22  = cr_wr_addr;
  assign \cr_wr_data$24  = cr_wr_data;
  assign \cr_wr_en$26  = cr_wr_en;
  assign \mem_addr$28  = mem_addr;
  assign \mem_rd_en$30  = mem_rd_en;
  assign \thread_wr_en$32  = thread_wr_en;
  assign \thread_wr_idx$34  = thread_wr_idx;
  assign \thread_wr_data$36  = thread_wr_data;
  assign fault_latched = fault;
  assign fault_type_latched = fault_type;
  assign index_latched = lazy_resolve_slot;
  assign pet_name_rd_addr = lazy_resolve_slot;
  
  assign \loaded_cap.word0_gt  = loaded_cap[31:0];
  assign \loaded_cap.word0_gt.slot_id  = loaded_cap[15:0];
  assign \loaded_cap.word0_gt.gt_seq  = loaded_cap[24:16];
  assign \loaded_cap.word0_gt.gt_type  = loaded_cap[26:25];
  assign \loaded_cap.word0_gt.dom  = loaded_cap[27];
  assign \loaded_cap.word0_gt.perm  = loaded_cap[30:28];
  assign \loaded_cap.word0_gt.b_flag  = loaded_cap[31];
  assign \loaded_cap.word1_location  = loaded_cap[63:32];
  assign \loaded_cap.word2_w2  = loaded_cap[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \cr_rd_data$14.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data$14.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data$14.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data$14.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data$14.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data$14.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data$14.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data$14.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data$14.word2_w2  = cr_rd_data[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$16.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$16.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$16.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$16.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$16.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$16.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$16.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$16.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$16.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_wr_data$24.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data$24.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data$24.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data$24.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data$24.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data$24.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data$24.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data$24.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data$24.word2_w2  = cr_wr_data[95:64];
endmodule

(* src = "/home/runner/workspace/hardware/mload.py:88" *)
(* generator = "Amaranth" *)
module \top.core.u_xloadlambda.u_mload (clk, \mem_rd_valid$23 , cr_rd_data, sub_m_elevated, mem_addr, mem_rd_en, sub_fault, sub_done, cr15_namespace, sub_start, cr_rd_addr, thread_wr_en, thread_wr_idx, thread_wr_data, cr_wr_addr, cr_wr_data, cr_wr_en, sub_fault_type, \port$5930$0 , mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$75  = 0;
  wire [18:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire \$17 ;
  wire \$18 ;
  wire \$19 ;
  wire [32:0] \$2 ;
  wire \$20 ;
  wire \$21 ;
  wire \$22 ;
  wire \$23 ;
  wire \$24 ;
  reg [3:0] \$25 ;
  reg [3:0] \$26 ;
  reg [15:0] \$27 ;
  reg \$28 ;
  reg [31:0] \$29 ;
  wire [32:0] \$3 ;
  reg \$30 ;
  reg [95:0] \$31 ;
  reg [4:0] \$32 ;
  reg [3:0] \$33 ;
  reg [95:0] \$34 ;
  reg [31:0] \$35 ;
  reg [31:0] \$36 ;
  reg [15:0] \$37 ;
  reg [31:0] \$38 ;
  wire [32:0] \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/mload.py:115" *)
  wire bounds_ok;
  (* src = "/home/runner/workspace/hardware/mload.py:119" *)
  wire [31:0] clist_gt_addr;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [95:0] \cr15_namespace$8 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace$8.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace$8.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace$8.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace$8.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace$8.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace$8.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:56" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  reg [3:0] cr_dst_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:49" *)
  output [3:0] cr_rd_addr;
  reg [3:0] cr_rd_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  input [95:0] cr_rd_data;
  wire [95:0] cr_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire \cr_rd_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [8:0] \cr_rd_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [1:0] \cr_rd_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [2:0] \cr_rd_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [15:0] \cr_rd_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:50" *)
  wire [31:0] \cr_rd_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  reg [3:0] cr_src_reg = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:52" *)
  output [3:0] cr_wr_addr;
  reg [3:0] cr_wr_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  output [95:0] cr_wr_data;
  reg [95:0] cr_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire \cr_wr_data.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [8:0] \cr_wr_data.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [1:0] \cr_wr_data.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [2:0] \cr_wr_data.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [15:0] \cr_wr_data.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:53" *)
  wire [31:0] \cr_wr_data.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:54" *)
  output cr_wr_en;
  reg cr_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  reg [31:0] direct_gt_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  reg direct_mode = 1'h0;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:253" *)
  reg [31:0] gbit_cleared_w1;
  (* src = "/home/runner/workspace/hardware/mload.py:66" *)
  reg gbit_reset_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  reg [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  reg [15:0] index_reg = 16'h0000;
  (* src = "/home/runner/workspace/hardware/mload.py:135" *)
  reg [31:0] local_mem_addr;
  (* src = "/home/runner/workspace/hardware/mload.py:136" *)
  reg local_mem_rd_en;
  (* src = "/home/runner/workspace/hardware/mload.py:138" *)
  wire [31:0] local_mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:137" *)
  wire local_mem_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  reg m_elevated_reg = 1'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:58" *)
  output [31:0] mem_addr;
  wire [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  wire [31:0] \mem_addr$12 ;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/mload.py:60" *)
  wire [31:0] \mem_rd_data$21 ;
  (* src = "/home/runner/workspace/hardware/mload.py:59" *)
  output mem_rd_en;
  wire mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  wire \mem_rd_en$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/mload.py:61" *)
  input \mem_rd_valid$23 ;
  wire \mem_rd_valid$23 ;
  (* src = "/home/runner/workspace/hardware/mload.py:63" *)
  reg [31:0] mem_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:62" *)
  reg mem_wr_en;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [3:0] mload_state = 4'h0;
  (* src = "/home/runner/workspace/hardware/mload.py:85" *)
  wire [31:0] ns_abstract_gt;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:71" *)
  wire [31:0] \ns_abstract_gt$56 ;
  (* src = "/home/runner/workspace/hardware/mload.py:65" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] \ns_entry_addr_out$25 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:64" *)
  wire [4:0] ns_gate_fault_type;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  reg ns_gate_start;
  (* src = "/home/runner/workspace/hardware/mload.py:125" *)
  wire ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  reg [31:0] ns_w1_saved = 32'd0;
  (* src = "/home/runner/workspace/hardware/mload.py:79" *)
  reg [31:0] outform_clist_addr = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  wire [31:0] outform_clist_addr_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:81" *)
  wire outform_done_in;
  (* src = "/home/runner/workspace/hardware/mload.py:82" *)
  wire outform_fault_in;
  (* src = "/home/runner/workspace/hardware/mload.py:83" *)
  wire [4:0] outform_fault_type_in;
  (* src = "/home/runner/workspace/hardware/mload.py:77" *)
  reg [31:0] outform_gt_raw = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  wire [31:0] outform_gt_raw_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:78" *)
  reg [15:0] outform_slot_id = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  wire [15:0] outform_slot_id_reg;
  (* src = "/home/runner/workspace/hardware/mload.py:76" *)
  wire outform_start_out;
  input [22:0] \port$5930$0 ;
  wire [22:0] \port$5930$0 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  reg [95:0] result_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire \result_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [8:0] \result_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [1:0] \result_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [2:0] \result_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [15:0] \result_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  wire [31:0] \result_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  reg [95:0] src_cap = 96'h000000000000000000000000;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word0_gt ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire \src_cap.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [8:0] \src_cap.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [1:0] \src_cap.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [2:0] \src_cap.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [15:0] \src_cap.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word1_location ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  wire [31:0] \src_cap.word2_w2 ;
  (* src = "/home/runner/workspace/hardware/mload.py:112" *)
  wire src_is_null;
  (* src = "/home/runner/workspace/hardware/mload.py:44" *)
  wire sub_busy;
  (* src = "/home/runner/workspace/hardware/mload.py:39" *)
  wire [3:0] sub_cr_dst;
  (* src = "/home/runner/workspace/hardware/mload.py:38" *)
  wire [3:0] sub_cr_src;
  (* src = "/home/runner/workspace/hardware/mload.py:41" *)
  wire sub_direct;
  (* src = "/home/runner/workspace/hardware/mload.py:42" *)
  wire [31:0] sub_direct_gt;
  (* src = "/home/runner/workspace/hardware/mload.py:45" *)
  output sub_done;
  wire sub_done;
  (* src = "/home/runner/workspace/hardware/mload.py:46" *)
  output sub_fault;
  wire sub_fault;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  output [4:0] sub_fault_type;
  reg [4:0] sub_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/mload.py:40" *)
  wire [15:0] sub_index;
  (* src = "/home/runner/workspace/hardware/mload.py:43" *)
  input sub_m_elevated;
  wire sub_m_elevated;
  (* src = "/home/runner/workspace/hardware/mload.py:37" *)
  input sub_start;
  wire sub_start;
  (* src = "/home/runner/workspace/hardware/mload.py:70" *)
  output [31:0] thread_wr_data;
  reg [31:0] thread_wr_data;
  (* src = "/home/runner/workspace/hardware/mload.py:68" *)
  output thread_wr_en;
  reg thread_wr_en;
  (* src = "/home/runner/workspace/hardware/mload.py:69" *)
  output [3:0] thread_wr_idx;
  reg [3:0] thread_wr_idx;
  (* src = "/home/runner/workspace/hardware/mload.py:99" *)
  always @(posedge clk)
    m_elevated_reg <= \$30 ;
  (* src = "/home/runner/workspace/hardware/mload.py:101" *)
  always @(posedge clk)
    result_cap <= \$31 ;
  (* src = "/home/runner/workspace/hardware/mload.py:102" *)
  always @(posedge clk)
    sub_fault_type <= \$32 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    mload_state <= \$33 ;
  (* src = "/home/runner/workspace/hardware/mload.py:100" *)
  always @(posedge clk)
    src_cap <= \$34 ;
  (* src = "/home/runner/workspace/hardware/mload.py:131" *)
  always @(posedge clk)
    outform_clist_addr <= \$35 ;
  (* src = "/home/runner/workspace/hardware/mload.py:132" *)
  always @(posedge clk)
    outform_gt_raw <= \$36 ;
  (* src = "/home/runner/workspace/hardware/mload.py:133" *)
  always @(posedge clk)
    outform_slot_id <= \$37 ;
  (* src = "/home/runner/workspace/hardware/mload.py:128" *)
  always @(posedge clk)
    ns_w1_saved <= \$38 ;
  assign src_is_null = ! (* src = "/home/runner/workspace/hardware/mload.py:113" *) src_cap[26:25];
  assign bounds_ok = index_reg < (* src = "/home/runner/workspace/hardware/mload.py:117" *) src_cap[79:64];
  assign \$2  = src_cap[63:32] + (* src = "/home/runner/workspace/hardware/mload.py:120" *) \$1 ;
  assign ns_index_in_bounds = result_cap[15:0] < (* src = "/home/runner/workspace/hardware/mload.py:126" *) cr15_namespace[79:64];
  assign mem_addr = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:144" *) \mem_addr$12  : local_mem_addr;
  assign mem_rd_en = ns_gate_busy ? (* src = "/home/runner/workspace/hardware/mload.py:147" *) \mem_rd_en$15  : local_mem_rd_en;
  assign mem_rd_valid = ns_gate_busy & (* src = "/home/runner/workspace/hardware/mload.py:152" *) \mem_rd_valid$23 ;
  assign \$4  = ns_entry_addr_out + (* src = "/home/runner/workspace/hardware/mload.py:256" *) 3'h4;
  assign \$5  = cr_dst_reg <= (* src = "/home/runner/workspace/hardware/mload.py:264" *) 3'h7;
  assign sub_busy = ~ (* src = "/home/runner/workspace/hardware/mload.py:302" *) \$6 ;
  assign ns_abstract_gt = m_elevated_reg ? (* src = "/home/runner/workspace/hardware/mload.py:310" *) \ns_abstract_gt$56  : 32'd0;
  assign \$6  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) mload_state;
  assign \$7  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$8  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$9  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign sub_fault = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$10  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$11  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign outform_start_out = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$12  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h8;
  assign \$13  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'h9;
  assign \$14  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'ha;
  assign \$15  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hb;
  assign sub_done = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hc;
  assign \$16  = mload_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 4'hd;
  assign \$17  = src_cap[27] & (* src = "/home/runner/workspace/hardware/perm_check.py:29" *) src_cap[28];
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$17 ;
  assign \$19  = ~ (* src = "/home/runner/workspace/hardware/mload.py:185" *) sub_m_elevated;
  assign \$20  = \$18  & (* src = "/home/runner/workspace/hardware/mload.py:185" *) \$19 ;
  assign \$21  = ~ (* src = "/home/runner/workspace/hardware/mload.py:192" *) bounds_ok;
  assign \$22  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:205" *) 2'h3;
  assign \$23  = mem_rd_data[26:25] == (* src = "/home/runner/workspace/hardware/mload.py:212" *) 2'h2;
  assign \$24  = ~ (* src = "/home/runner/workspace/hardware/mload.py:223" *) ns_index_in_bounds;
  (* src = "/home/runner/workspace/hardware/mload.py:94" *)
  always @(posedge clk)
    cr_src_reg <= \$25 ;
  (* src = "/home/runner/workspace/hardware/mload.py:95" *)
  always @(posedge clk)
    cr_dst_reg <= \$26 ;
  (* src = "/home/runner/workspace/hardware/mload.py:96" *)
  always @(posedge clk)
    index_reg <= \$27 ;
  (* src = "/home/runner/workspace/hardware/mload.py:97" *)
  always @(posedge clk)
    direct_mode <= \$28 ;
  (* src = "/home/runner/workspace/hardware/mload.py:98" *)
  always @(posedge clk)
    direct_gt_reg <= \$29 ;
  (* src = "/home/runner/workspace/hardware/mload.py:90" *)
  \top.core.u_xloadlambda.u_mload.u_ns_gate  u_ns_gate (
    .clk(clk),
    .cr15_namespace(cr15_namespace),
    .gt_word0(gt_word0),
    .mem_addr(\mem_addr$12 ),
    .mem_rd_data(mem_rd_data),
    .mem_rd_en(\mem_rd_en$15 ),
    .mem_rd_valid(mem_rd_valid),
    .ns_abstract_gt(\ns_abstract_gt$56 ),
    .ns_entry_addr(ns_entry_addr_out),
    .ns_gate_busy(ns_gate_busy),
    .ns_gate_done(ns_gate_done),
    .ns_gate_fault(ns_gate_fault),
    .ns_gate_fault_type(ns_gate_fault_type),
    .ns_gate_start(ns_gate_start),
    .raw_base_reg(raw_base),
    .raw_w2_reg(raw_w2)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$31  = result_cap;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$31  = 96'h000000000000000000000000;
          end
      4'h1:
          if (direct_mode) begin
            \$31 [31:0] = direct_gt_reg;
          end
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            \$31 [31:0] = mem_rd_data;
          end
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$31 [63:32] = raw_base;
            \$31 [95:64] = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$32  = sub_fault_type;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$32  = 5'h00;
          end
      4'h1:
          /* empty */;
      4'h3:
          if (src_is_null) begin
            \$32  = 5'h07;
          end else if (\$20 ) begin
            \$32  = 5'h04;
          end
      4'h5:
          if (\$21 ) begin
            \$32  = 5'h08;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
              \$32  = 5'h0b;
            end
          end
      4'h2:
          if (\$24 ) begin
            \$32  = 5'h08;
          end
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
            \$32  = ns_gate_fault_type;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$33  = mload_state;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$33  = 4'h1;
          end
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
            \$33  = 4'h2;
          end else begin
            \$33  = 4'h3;
          end
      4'h3:
          (* full_case = 32'd1 *)
          if (src_is_null) begin
            \$33  = 4'h4;
          end else if (\$20 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h5;
          end
      4'h5:
          (* full_case = 32'd1 *)
          if (\$21 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h6;
          end
      4'h6:
          if (\mem_rd_valid$23 ) begin
            (* full_case = 32'd1 *)
            if (\$22 ) begin
              \$33  = 4'h4;
            end else if (\$23 ) begin
              \$33  = 4'h7;
            end else begin
              \$33  = 4'h2;
            end
          end
      4'h2:
          (* full_case = 32'd1 *)
          if (\$24 ) begin
            \$33  = 4'h4;
          end else begin
            \$33  = 4'h8;
          end
      4'h8:
          \$33  = 4'h9;
      4'h9:
          if (ns_gate_fault) begin
            \$33  = 4'h4;
          end else if (ns_gate_done) begin
            \$33  = 4'ha;
          end
      4'ha:
          \$33  = 4'hb;
      4'hb:
          \$33  = 4'hc;
      4'hc:
          \$33  = 4'h0;
      4'h4:
          \$33  = 4'h0;
      4'h7:
          \$33  = 4'hd;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$34  = src_cap;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            \$34  = cr_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$35  = outform_clist_addr;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$35  = \$2 [31:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$36  = outform_gt_raw;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$36  = mem_rd_data;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$37  = outform_slot_id;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          if (\mem_rd_valid$23 ) begin
            if (\$22 ) begin
            end else if (\$23 ) begin
              \$37  = mem_rd_data[15:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$38  = ns_w1_saved;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          if (ns_gate_fault) begin
          end else if (ns_gate_done) begin
            \$38  = raw_w2;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    cr_rd_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          (* full_case = 32'd1 *)
          if (direct_mode) begin
          end else begin
            cr_rd_addr = cr_src_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    local_mem_addr = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_addr = \$2 [31:0];
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          local_mem_addr = \$4 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    local_mem_rd_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          local_mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    ns_gate_start = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          ns_gate_start = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    gt_word0 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          gt_word0 = result_cap[31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    gbit_cleared_w1 = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_cleared_w1 = \$3 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    mem_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    mem_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          mem_wr_data = gbit_cleared_w1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    gbit_reset_done = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          gbit_reset_done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    thread_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_en = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    thread_wr_idx = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_idx = cr_dst_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    thread_wr_data = 32'd0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          if (\$5 ) begin
            thread_wr_data = result_cap[31:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    cr_wr_addr = 4'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_addr = cr_dst_reg;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    cr_wr_data = 96'h000000000000000000000000;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_data = result_cap;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    cr_wr_en = 1'h0;
    casez (mload_state)
      4'h0:
          /* empty */;
      4'h1:
          /* empty */;
      4'h3:
          /* empty */;
      4'h5:
          /* empty */;
      4'h6:
          /* empty */;
      4'h2:
          /* empty */;
      4'h8:
          /* empty */;
      4'h9:
          /* empty */;
      4'ha:
          /* empty */;
      4'hb:
          /* empty */;
      4'hc:
          cr_wr_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$25  = cr_src_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$25  = \port$5930$0 [18:15];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$26  = cr_dst_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$26  = \port$5930$0 [22:19];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$27  = index_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$27  = { 1'h0, \port$5930$0 [14:0] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$28  = direct_mode;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$28  = 1'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$29  = direct_gt_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$29  = 32'd0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$75 ) begin end
    \$30  = m_elevated_reg;
    casez (mload_state)
      4'h0:
          if (sub_start) begin
            \$30  = sub_m_elevated;
          end
    endcase
  end
  assign clist_gt_addr = \$2 [31:0];
  assign \cr15_namespace$8  = cr15_namespace;
  assign local_mem_wr_en = mem_wr_en;
  assign local_mem_wr_data = mem_wr_data;
  assign \mem_rd_data$21  = mem_rd_data;
  assign \ns_entry_addr_out$25  = ns_entry_addr_out;
  assign fault_type_reg = sub_fault_type;
  assign outform_gt_raw_reg = outform_gt_raw;
  assign outform_slot_id_reg = outform_slot_id;
  assign outform_clist_addr_reg = outform_clist_addr;
  
  assign sub_cr_src = \port$5930$0 [18:15];
  assign sub_cr_dst = \port$5930$0 [22:19];
  assign sub_index = { 1'h0, \port$5930$0 [14:0] };
  assign sub_direct = 1'h0;
  assign sub_direct_gt = 32'd0;
  assign outform_fault_in = 1'h0;
  assign outform_done_in = 1'h0;
  assign outform_fault_type_in = 5'h00;
  assign \src_cap.word0_gt  = src_cap[31:0];
  assign \src_cap.word0_gt.slot_id  = src_cap[15:0];
  assign \src_cap.word0_gt.gt_seq  = src_cap[24:16];
  assign \src_cap.word0_gt.gt_type  = src_cap[26:25];
  assign \src_cap.word0_gt.dom  = src_cap[27];
  assign \src_cap.word0_gt.perm  = src_cap[30:28];
  assign \src_cap.word0_gt.b_flag  = src_cap[31];
  assign \src_cap.word1_location  = src_cap[63:32];
  assign \src_cap.word2_w2  = src_cap[95:64];
  assign \result_cap.word0_gt  = result_cap[31:0];
  assign \result_cap.word0_gt.slot_id  = result_cap[15:0];
  assign \result_cap.word0_gt.gt_seq  = result_cap[24:16];
  assign \result_cap.word0_gt.gt_type  = result_cap[26:25];
  assign \result_cap.word0_gt.dom  = result_cap[27];
  assign \result_cap.word0_gt.perm  = result_cap[30:28];
  assign \result_cap.word0_gt.b_flag  = result_cap[31];
  assign \result_cap.word1_location  = result_cap[63:32];
  assign \result_cap.word2_w2  = result_cap[95:64];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \cr15_namespace$8.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace$8.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace$8.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace$8.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace$8.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace$8.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace$8.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace$8.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace$8.word2_w2  = cr15_namespace[95:64];
  assign \cr_wr_data.word0_gt  = cr_wr_data[31:0];
  assign \cr_wr_data.word0_gt.slot_id  = cr_wr_data[15:0];
  assign \cr_wr_data.word0_gt.gt_seq  = cr_wr_data[24:16];
  assign \cr_wr_data.word0_gt.gt_type  = cr_wr_data[26:25];
  assign \cr_wr_data.word0_gt.dom  = cr_wr_data[27];
  assign \cr_wr_data.word0_gt.perm  = cr_wr_data[30:28];
  assign \cr_wr_data.word0_gt.b_flag  = cr_wr_data[31];
  assign \cr_wr_data.word1_location  = cr_wr_data[63:32];
  assign \cr_wr_data.word2_w2  = cr_wr_data[95:64];
  assign \cr_rd_data.word0_gt  = cr_rd_data[31:0];
  assign \cr_rd_data.word0_gt.slot_id  = cr_rd_data[15:0];
  assign \cr_rd_data.word0_gt.gt_seq  = cr_rd_data[24:16];
  assign \cr_rd_data.word0_gt.gt_type  = cr_rd_data[26:25];
  assign \cr_rd_data.word0_gt.dom  = cr_rd_data[27];
  assign \cr_rd_data.word0_gt.perm  = cr_rd_data[30:28];
  assign \cr_rd_data.word0_gt.b_flag  = cr_rd_data[31];
  assign \cr_rd_data.word1_location  = cr_rd_data[63:32];
  assign \cr_rd_data.word2_w2  = cr_rd_data[95:64];
  assign \$1  = { 1'h0, index_reg, 2'h0 };
  assign \$3 [30] = 1'h0;
  assign { \$3 [32:31], \$3 [29:0] } = { 1'h0, ns_w1_saved[31], ns_w1_saved[29:0] };
endmodule

(* src = "/home/runner/workspace/hardware/ns_gate.py:80" *)
(* generator = "Amaranth" *)
module \top.core.u_xloadlambda.u_mload.u_ns_gate (clk, mem_rd_valid, ns_entry_addr, ns_gate_busy, ns_gate_fault, ns_gate_done, cr15_namespace, ns_gate_start, gt_word0, mem_addr, mem_rd_en, raw_base_reg, raw_w2_reg, ns_abstract_gt, ns_gate_fault_type, mem_rd_data);
  reg \$auto$verilog_backend.cc:2355:dump_module$76  = 0;
  wire [22:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  reg [31:0] \$15 ;
  reg [31:0] \$16 ;
  reg [31:0] \$17 ;
  reg [31:0] \$18 ;
  reg [4:0] \$19 ;
  wire [32:0] \$2 ;
  reg [31:0] \$20 ;
  reg [2:0] \$21 ;
  wire [31:0] \$3 ;
  wire [32:0] \$4 ;
  wire [32:0] \$5 ;
  wire [32:0] \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  wire [23:0] \$auto$rtlil.cc:2739:Not$22 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:103" *)
  wire [31:0] computed_integrity;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  input [95:0] cr15_namespace;
  wire [95:0] cr15_namespace;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word0_gt ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.b_flag ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire \cr15_namespace.word0_gt.dom ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [8:0] \cr15_namespace.word0_gt.gt_seq ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [1:0] \cr15_namespace.word0_gt.gt_type ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [2:0] \cr15_namespace.word0_gt.perm ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [15:0] \cr15_namespace.word0_gt.slot_id ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word1_location ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:67" *)
  wire [31:0] \cr15_namespace.word2_w2 ;
  (* init = 5'h00 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  wire [4:0] fault_type_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  reg [31:0] gt_latched = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:99" *)
  wire gt_seq_match;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:66" *)
  input [31:0] gt_word0;
  wire [31:0] gt_word0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:74" *)
  output [31:0] mem_addr;
  reg [31:0] mem_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:76" *)
  input [31:0] mem_rd_data;
  wire [31:0] mem_rd_data;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:75" *)
  output mem_rd_en;
  reg mem_rd_en;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:77" *)
  input mem_rd_valid;
  wire mem_rd_valid;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  output [31:0] ns_abstract_gt;
  reg [31:0] ns_abstract_gt = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  output [31:0] ns_entry_addr;
  wire [31:0] ns_entry_addr;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:72" *)
  wire [31:0] ns_entry_addr_out;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:61" *)
  output ns_gate_busy;
  wire ns_gate_busy;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:62" *)
  output ns_gate_done;
  wire ns_gate_done;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:63" *)
  output ns_gate_fault;
  wire ns_gate_fault;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  output [4:0] ns_gate_fault_type;
  reg [4:0] ns_gate_fault_type = 5'h00;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:60" *)
  input ns_gate_start;
  wire ns_gate_start;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] ns_gate_state = 3'h0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  wire [31:0] raw_base;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:69" *)
  output [31:0] raw_base_reg;
  reg [31:0] raw_base_reg = 32'd0;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  reg [31:0] raw_integrity_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  wire [31:0] raw_w2;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:70" *)
  output [31:0] raw_w2_reg;
  reg [31:0] raw_w2_reg = 32'd0;
  (* init = 32'd0 *)
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  wire [31:0] raw_w3_reg;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:106" *)
  wire seal_ok;
  (* src = "/home/runner/workspace/hardware/integrity32.py:60" *)
  wire [31:0] w0_rot;
  (* src = "/home/runner/workspace/hardware/integrity32.py:59" *)
  wire [31:0] w1_masked;
  (* src = "/home/runner/workspace/hardware/integrity32.py:61" *)
  wire [31:0] w1_rot;
  assign \$2  = cr15_namespace[63:32] + (* src = "/home/runner/workspace/hardware/ns_gate.py:93" *) \$1 ;
  assign gt_seq_match = gt_latched[24:16] == (* src = "/home/runner/workspace/hardware/ns_gate.py:100" *) raw_w2_reg[29:21];
  assign \$3  = { raw_base_reg[24:0], raw_base_reg[31:25] } ^ (* src = "/home/runner/workspace/hardware/integrity32.py:68" *) { w1_masked[18:0], w1_masked[31:19] };
  assign seal_ok = computed_integrity == (* src = "/home/runner/workspace/hardware/ns_gate.py:107" *) raw_integrity_reg;
  assign \$4  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:135" *) 3'h4;
  assign \$5  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:148" *) 4'h8;
  assign \$6  = \$2 [31:0] + (* src = "/home/runner/workspace/hardware/ns_gate.py:170" *) 4'hc;
  assign ns_gate_busy = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:184" *) \$7 ;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) ns_gate_state;
  assign \$8  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign ns_gate_fault = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$12  = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign ns_gate_done = ns_gate_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h7;
  assign \$13  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:156" *) gt_seq_match;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/ns_gate.py:159" *) seal_ok;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:82" *)
  always @(posedge clk)
    gt_latched <= \$15 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:86" *)
  always @(posedge clk)
    raw_base_reg <= \$16 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:87" *)
  always @(posedge clk)
    raw_w2_reg <= \$17 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:88" *)
  always @(posedge clk)
    ns_abstract_gt <= \$18 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:84" *)
  always @(posedge clk)
    ns_gate_fault_type <= \$19 ;
  (* src = "/home/runner/workspace/hardware/ns_gate.py:102" *)
  always @(posedge clk)
    raw_integrity_reg <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    ns_gate_state <= \$21 ;
  assign \$auto$rtlil.cc:2739:Not$22  = ~ { \$3 [31:30], \$3 [28:25], \$3 [23], \$3 [21], \$3 [19:18], \$3 [16:15], \$3 [13:9], \$3 [7:5], \$3 [3:0] };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    mem_addr = 32'd0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_addr = \$2 [31:0];
      3'h2:
          mem_addr = \$4 [31:0];
      3'h3:
          mem_addr = \$5 [31:0];
      3'h4:
          /* empty */;
      3'h6:
          mem_addr = \$6 [31:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    mem_rd_en = 1'h0;
    casez (ns_gate_state)
      3'h0:
          /* empty */;
      3'h1:
          mem_rd_en = 1'h1;
      3'h2:
          mem_rd_en = 1'h1;
      3'h3:
          mem_rd_en = 1'h1;
      3'h4:
          /* empty */;
      3'h6:
          mem_rd_en = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    \$15  = gt_latched;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$15  = gt_word0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    \$16  = raw_base_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$16  = 32'd0;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$16  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    \$17  = raw_w2_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$17  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          if (mem_rd_valid) begin
            \$17  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    \$18  = ns_abstract_gt;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$18  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          /* empty */;
      3'h6:
          if (mem_rd_valid) begin
            \$18  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    \$19  = ns_gate_fault_type;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$19  = 5'h00;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          if (\$13 ) begin
            \$19  = 5'h09;
          end else if (\$14 ) begin
            \$19  = 5'h0a;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    \$20  = raw_integrity_reg;
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$20  = 32'd0;
          end
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          if (mem_rd_valid) begin
            \$20  = mem_rd_data;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$76 ) begin end
    \$21  = ns_gate_state;
    (* full_case = 32'd1 *)
    casez (ns_gate_state)
      3'h0:
          if (ns_gate_start) begin
            \$21  = 3'h1;
          end
      3'h1:
          if (mem_rd_valid) begin
            \$21  = 3'h2;
          end
      3'h2:
          if (mem_rd_valid) begin
            \$21  = 3'h3;
          end
      3'h3:
          if (mem_rd_valid) begin
            \$21  = 3'h4;
          end
      3'h4:
          (* full_case = 32'd1 *)
          if (\$13 ) begin
            \$21  = 3'h5;
          end else if (\$14 ) begin
            \$21  = 3'h5;
          end else begin
            \$21  = 3'h6;
          end
      3'h6:
          if (mem_rd_valid) begin
            \$21  = 3'h7;
          end
      3'h7:
          \$21  = 3'h0;
      3'h5:
          \$21  = 3'h0;
    endcase
  end
  assign w0_rot = { raw_base_reg[24:0], raw_base_reg[31:25] };
  assign w1_rot = { w1_masked[18:0], w1_masked[31:19] };
  assign fault_type_reg = ns_gate_fault_type;
  assign raw_base = raw_base_reg;
  assign raw_w2 = raw_w2_reg;
  assign raw_w3_reg = ns_abstract_gt;
  assign ns_entry_addr_out = \$2 [31:0];
  
  assign ns_entry_addr = \$2 [31:0];
  assign \cr15_namespace.word0_gt  = cr15_namespace[31:0];
  assign \cr15_namespace.word0_gt.slot_id  = cr15_namespace[15:0];
  assign \cr15_namespace.word0_gt.gt_seq  = cr15_namespace[24:16];
  assign \cr15_namespace.word0_gt.gt_type  = cr15_namespace[26:25];
  assign \cr15_namespace.word0_gt.dom  = cr15_namespace[27];
  assign \cr15_namespace.word0_gt.perm  = cr15_namespace[30:28];
  assign \cr15_namespace.word0_gt.b_flag  = cr15_namespace[31];
  assign \cr15_namespace.word1_location  = cr15_namespace[63:32];
  assign \cr15_namespace.word2_w2  = cr15_namespace[95:64];
  assign \$1  = { 3'h0, gt_latched[15:0], 4'h0 };
  assign w1_masked[31:30] = 2'h0;
  assign w1_masked[29:0] = raw_w2_reg[29:0];
  assign { computed_integrity[29], computed_integrity[24], computed_integrity[22], computed_integrity[20], computed_integrity[17], computed_integrity[14], computed_integrity[8], computed_integrity[4] } = { \$3 [29], \$3 [24], \$3 [22], \$3 [20], \$3 [17], \$3 [14], \$3 [8], \$3 [4] };
  assign { computed_integrity[31:30], computed_integrity[28:25], computed_integrity[23], computed_integrity[21], computed_integrity[19:18], computed_integrity[16:15], computed_integrity[13:9], computed_integrity[7:5], computed_integrity[3:0] } = \$auto$rtlil.cc:2739:Not$22 ;
endmodule

(* src = "/home/runner/workspace/hardware/uart_crc16.py:24" *)
(* generator = "Amaranth" *)
module \top.crc_mod (clk, data_in, valid, crc, reset);
  reg \$auto$verilog_backend.cc:2355:dump_module$77  = 0;
  wire \$1 ;
  wire [15:0] \$10 ;
  wire \$11 ;
  wire [15:0] \$12 ;
  wire \$13 ;
  wire [15:0] \$14 ;
  wire \$15 ;
  wire [15:0] \$16 ;
  reg [15:0] \$17 ;
  wire [15:0] \$2 ;
  wire \$3 ;
  wire [15:0] \$4 ;
  wire \$5 ;
  wire [15:0] \$6 ;
  wire \$7 ;
  wire [15:0] \$8 ;
  wire \$9 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$10 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$12 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$14 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$16 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$2 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$4 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$6 ;
  wire [2:0] \$auto$rtlil.cc:2739:Not$8 ;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:21" *)
  output [15:0] crc;
  reg [15:0] crc = 16'hffff;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:26" *)
  wire [15:0] crc_next;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s0;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s1;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s2;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s3;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s4;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s5;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s6;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:33" *)
  wire [15:0] crc_s7;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:20" *)
  input [7:0] data_in;
  wire [7:0] data_in;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:18" *)
  input reset;
  wire reset;
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:19" *)
  input valid;
  wire valid;
  assign \$1  = data_in[7] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc[15];
  assign crc_s0 = \$1  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$2  : { crc[14:0], 1'h0 };
  assign \$3  = data_in[6] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc_s0[15];
  assign crc_s1 = \$3  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$4  : { crc_s0[14:0], 1'h0 };
  assign \$5  = data_in[5] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc_s1[15];
  assign crc_s2 = \$5  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$6  : { crc_s1[14:0], 1'h0 };
  assign \$7  = data_in[4] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc_s2[15];
  assign crc_s3 = \$7  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$8  : { crc_s2[14:0], 1'h0 };
  assign \$9  = data_in[3] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc_s3[15];
  assign crc_s4 = \$9  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$10  : { crc_s3[14:0], 1'h0 };
  assign \$11  = data_in[2] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc_s4[15];
  assign crc_s5 = \$11  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$12  : { crc_s4[14:0], 1'h0 };
  assign \$13  = data_in[1] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc_s5[15];
  assign crc_s6 = \$13  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$14  : { crc_s5[14:0], 1'h0 };
  assign \$15  = data_in[0] ^ (* src = "/home/runner/workspace/hardware/uart_crc16.py:31" *) crc_s6[15];
  assign crc_s7 = \$15  ? (* src = "/home/runner/workspace/hardware/uart_crc16.py:34" *) \$16  : { crc_s6[14:0], 1'h0 };
  (* src = "/home/runner/workspace/hardware/uart_crc16.py:21" *)
  always @(posedge clk)
    crc <= \$17 ;
  assign \$auto$rtlil.cc:2739:Not$2  = ~ { crc[11], crc[4], 1'h0 };
  assign \$auto$rtlil.cc:2739:Not$12  = ~ { crc_s4[11], crc_s4[4], 1'h0 };
  assign \$auto$rtlil.cc:2739:Not$14  = ~ { crc_s5[11], crc_s5[4], 1'h0 };
  assign \$auto$rtlil.cc:2739:Not$16  = ~ { crc_s6[11], crc_s6[4], 1'h0 };
  assign \$auto$rtlil.cc:2739:Not$4  = ~ { crc_s0[11], crc_s0[4], 1'h0 };
  assign \$auto$rtlil.cc:2739:Not$6  = ~ { crc_s1[11], crc_s1[4], 1'h0 };
  assign \$auto$rtlil.cc:2739:Not$8  = ~ { crc_s2[11], crc_s2[4], 1'h0 };
  assign \$auto$rtlil.cc:2739:Not$10  = ~ { crc_s3[11], crc_s3[4], 1'h0 };
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$77 ) begin end
    \$17  = crc;
    if (reset) begin
      \$17  = 16'hffff;
    end else if (valid) begin
      \$17  = crc_s7;
    end
  end
  assign crc_next = crc_s7;
  
  assign { \$2 [15:13], \$2 [11:6], \$2 [4:1] } = { crc[14:12], crc[10:5], crc[3:0] };
  assign { \$2 [12], \$2 [5], \$2 [0] } = \$auto$rtlil.cc:2739:Not$2 ;
  assign { \$4 [15:13], \$4 [11:6], \$4 [4:1] } = { crc_s0[14:12], crc_s0[10:5], crc_s0[3:0] };
  assign { \$4 [12], \$4 [5], \$4 [0] } = \$auto$rtlil.cc:2739:Not$4 ;
  assign { \$6 [15:13], \$6 [11:6], \$6 [4:1] } = { crc_s1[14:12], crc_s1[10:5], crc_s1[3:0] };
  assign { \$6 [12], \$6 [5], \$6 [0] } = \$auto$rtlil.cc:2739:Not$6 ;
  assign { \$8 [15:13], \$8 [11:6], \$8 [4:1] } = { crc_s2[14:12], crc_s2[10:5], crc_s2[3:0] };
  assign { \$8 [12], \$8 [5], \$8 [0] } = \$auto$rtlil.cc:2739:Not$8 ;
  assign { \$10 [15:13], \$10 [11:6], \$10 [4:1] } = { crc_s3[14:12], crc_s3[10:5], crc_s3[3:0] };
  assign { \$10 [12], \$10 [5], \$10 [0] } = \$auto$rtlil.cc:2739:Not$10 ;
  assign { \$12 [15:13], \$12 [11:6], \$12 [4:1] } = { crc_s4[14:12], crc_s4[10:5], crc_s4[3:0] };
  assign { \$12 [12], \$12 [5], \$12 [0] } = \$auto$rtlil.cc:2739:Not$12 ;
  assign { \$14 [15:13], \$14 [11:6], \$14 [4:1] } = { crc_s5[14:12], crc_s5[10:5], crc_s5[3:0] };
  assign { \$14 [12], \$14 [5], \$14 [0] } = \$auto$rtlil.cc:2739:Not$14 ;
  assign { \$16 [15:13], \$16 [11:6], \$16 [4:1] } = { crc_s6[14:12], crc_s6[10:5], crc_s6[3:0] };
  assign { \$16 [12], \$16 [5], \$16 [0] } = \$auto$rtlil.cc:2739:Not$16 ;
endmodule

(* src = "/home/runner/workspace/hardware/uart_tx.py:97" *)
(* generator = "Amaranth" *)
module \top.debug (clk, byte_data, \data$15 , send, busy, tx, send_byte);
  reg \$auto$verilog_backend.cc:2355:dump_module$78  = 0;
  wire [6:0] \$1 ;
  wire \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire [4:0] \$16 ;
  wire \$17 ;
  wire \$18 ;
  reg [31:0] \$19 ;
  wire [31:0] \$2 ;
  reg [3:0] \$20 ;
  reg [2:0] \$21 ;
  reg [7:0] \$22 ;
  wire [31:0] \$3 ;
  wire \$4 ;
  wire \$5 ;
  wire \$6 ;
  wire \$7 ;
  wire \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:93" *)
  output busy;
  reg busy;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:21" *)
  wire \busy$8 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:92" *)
  input [7:0] byte_data;
  wire [7:0] byte_data;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:107" *)
  reg [7:0] byte_reg = 8'h00;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:19" *)
  reg [7:0] data;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:89" *)
  input [31:0] \data$15 ;
  wire [31:0] \data$15 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:105" *)
  reg [31:0] data_reg = 32'd0;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] debug_printer_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:22" *)
  wire done;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:110" *)
  reg [7:0] hex_byte;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:106" *)
  reg [3:0] nibble_idx = 4'h0;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:109" *)
  wire [3:0] nibble_val;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:90" *)
  input send;
  wire send;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:91" *)
  input send_byte;
  wire send_byte;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:20" *)
  reg start;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:23" *)
  output tx;
  wire tx;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:23" *)
  wire \tx$1 ;
  assign \$2  = data_reg >> (* src = "/home/runner/workspace/hardware/uart_tx.py:111" *) \$1 ;
  assign \$4  = ~ (* src = "/home/runner/workspace/hardware/uart_tx.py:129" *) \busy$8 ;
  assign \$5  = ~ (* src = "/home/runner/workspace/hardware/uart_tx.py:147" *) \busy$8 ;
  assign \$6  = ~ (* src = "/home/runner/workspace/hardware/uart_tx.py:161" *) \busy$8 ;
  assign \$7  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) debug_printer_state;
  assign \$8  = debug_printer_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$9  = debug_printer_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$10  = debug_printer_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$11  = debug_printer_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$12  = debug_printer_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  assign \$13  = debug_printer_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h6;
  assign \$14  = ~ (* src = "/home/runner/workspace/hardware/uart_tx.py:129" *) \busy$8 ;
  assign \$15  = ! (* src = "/home/runner/workspace/hardware/uart_tx.py:139" *) nibble_idx;
  assign \$16  = nibble_idx - (* src = "/home/runner/workspace/hardware/uart_tx.py:142" *) 1'h1;
  assign \$17  = ~ (* src = "/home/runner/workspace/hardware/uart_tx.py:147" *) \busy$8 ;
  assign \$18  = ~ (* src = "/home/runner/workspace/hardware/uart_tx.py:161" *) \busy$8 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:105" *)
  always @(posedge clk)
    data_reg <= \$19 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:106" *)
  always @(posedge clk)
    nibble_idx <= \$20 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    debug_printer_state <= \$21 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:107" *)
  always @(posedge clk)
    byte_reg <= \$22 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:100" *)
  \top.debug.uart  uart (
    .clk(clk),
    .busy(\busy$8 ),
    .data(data),
    .done(done),
    .start(start),
    .tx(tx)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    (* full_case = 32'd1 *)
    casez (\$3 [3:0])
      4'h0:
          hex_byte = 8'h30;
      4'h1:
          hex_byte = 8'h31;
      4'h2:
          hex_byte = 8'h32;
      4'h3:
          hex_byte = 8'h33;
      4'h4:
          hex_byte = 8'h34;
      4'h5:
          hex_byte = 8'h35;
      4'h6:
          hex_byte = 8'h36;
      4'h7:
          hex_byte = 8'h37;
      4'h8:
          hex_byte = 8'h38;
      4'h9:
          hex_byte = 8'h39;
      4'ha:
          hex_byte = 8'h41;
      4'hb:
          hex_byte = 8'h42;
      4'hc:
          hex_byte = 8'h43;
      4'hd:
          hex_byte = 8'h44;
      4'he:
          hex_byte = 8'h45;
      4'hf:
          hex_byte = 8'h46;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    busy = 1'h0;
    casez (debug_printer_state)
      3'h0:
          busy = 1'h0;
      3'h1:
          busy = 1'h1;
      3'h3:
          busy = 1'h1;
      3'h4:
          busy = 1'h1;
      3'h5:
          busy = 1'h1;
      3'h2:
          busy = 1'h1;
      3'h6:
          busy = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    data = 8'h00;
    casez (debug_printer_state)
      3'h0:
          /* empty */;
      3'h1:
          if (\$4 ) begin
            data = hex_byte;
          end
      3'h3:
          /* empty */;
      3'h4:
          if (\$5 ) begin
            data = 8'h0a;
          end
      3'h5:
          /* empty */;
      3'h2:
          if (\$6 ) begin
            data = byte_reg;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    start = 1'h0;
    casez (debug_printer_state)
      3'h0:
          /* empty */;
      3'h1:
          if (\$4 ) begin
            start = 1'h1;
          end
      3'h3:
          /* empty */;
      3'h4:
          if (\$5 ) begin
            start = 1'h1;
          end
      3'h5:
          /* empty */;
      3'h2:
          if (\$6 ) begin
            start = 1'h1;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    \$19  = data_reg;
    casez (debug_printer_state)
      3'h0:
          if (send) begin
            \$19  = \data$15 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    \$20  = nibble_idx;
    casez (debug_printer_state)
      3'h0:
          if (send) begin
            \$20  = 4'h7;
          end
      3'h1:
          /* empty */;
      3'h3:
          if (done) begin
            (* full_case = 32'd1 *)
            if (\$15 ) begin
            end else begin
              \$20  = \$16 [3:0];
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    \$21  = debug_printer_state;
    casez (debug_printer_state)
      3'h0:
          if (send) begin
            \$21  = 3'h1;
          end else if (send_byte) begin
            \$21  = 3'h2;
          end
      3'h1:
          if (\$14 ) begin
            \$21  = 3'h3;
          end
      3'h3:
          if (done) begin
            (* full_case = 32'd1 *)
            if (\$15 ) begin
              \$21  = 3'h4;
            end else begin
              \$21  = 3'h1;
            end
          end
      3'h4:
          if (\$17 ) begin
            \$21  = 3'h5;
          end
      3'h5:
          if (done) begin
            \$21  = 3'h0;
          end
      3'h2:
          if (\$18 ) begin
            \$21  = 3'h6;
          end
      3'h6:
          if (done) begin
            \$21  = 3'h0;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$78 ) begin end
    \$22  = byte_reg;
    casez (debug_printer_state)
      3'h0:
          if (send) begin
          end else if (send_byte) begin
            \$22  = byte_data;
          end
    endcase
  end
  assign \tx$1  = tx;
  assign nibble_val = \$3 [3:0];
  
  assign \$1  = { 1'h0, nibble_idx, 2'h0 };
  assign \$3 [31:4] = 28'h0000000;
  assign \$3 [3:0] = \$2 [3:0];
endmodule

(* src = "/home/runner/workspace/hardware/uart_tx.py:26" *)
(* generator = "Amaranth" *)
module \top.debug.uart (clk, start, tx, busy, done, data);
  reg \$auto$verilog_backend.cc:2355:dump_module$79  = 0;
  wire \$1 ;
  reg [8:0] \$10 ;
  reg [3:0] \$11 ;
  reg [1:0] \$12 ;
  wire \$2 ;
  wire \$3 ;
  wire \$4 ;
  wire [9:0] \$5 ;
  wire [4:0] \$6 ;
  wire \$7 ;
  wire [9:0] \$8 ;
  reg [9:0] \$9 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:31" *)
  reg [3:0] bit_pos = 4'h0;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:21" *)
  output busy;
  reg busy;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:30" *)
  reg [8:0] counter = 9'h000;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:19" *)
  input [7:0] data;
  wire [7:0] data;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:22" *)
  output done;
  reg done;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:32" *)
  reg [9:0] shift_reg = 10'h000;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:20" *)
  input start;
  wire start;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:23" *)
  output tx;
  reg tx;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [1:0] uart_tx_state = 2'h0;
  assign \$1  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) uart_tx_state;
  assign \$2  = uart_tx_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$3  = uart_tx_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$4  = counter == (* src = "/home/runner/workspace/hardware/uart_tx.py:55" *) 9'h1b1;
  assign \$6  = bit_pos + (* src = "/home/runner/workspace/hardware/uart_tx.py:59" *) 1'h1;
  assign \$7  = bit_pos == (* src = "/home/runner/workspace/hardware/uart_tx.py:61" *) 4'h9;
  assign \$8  = counter + (* src = "/home/runner/workspace/hardware/uart_tx.py:64" *) 1'h1;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:32" *)
  always @(posedge clk)
    shift_reg <= \$9 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:30" *)
  always @(posedge clk)
    counter <= \$10 ;
  (* src = "/home/runner/workspace/hardware/uart_tx.py:31" *)
  always @(posedge clk)
    bit_pos <= \$11 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    uart_tx_state <= \$12 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$79 ) begin end
    tx = 1'h1;
    casez (uart_tx_state)
      2'h0:
          tx = 1'h1;
      2'h1:
          tx = shift_reg[0];
      2'h2:
          tx = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$79 ) begin end
    busy = 1'h0;
    casez (uart_tx_state)
      2'h0:
          busy = 1'h0;
      2'h1:
          busy = 1'h1;
      2'h2:
          busy = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$79 ) begin end
    done = 1'h0;
    casez (uart_tx_state)
      2'h0:
          done = 1'h0;
      2'h1:
          done = 1'h0;
      2'h2:
          done = 1'h1;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$79 ) begin end
    \$9  = shift_reg;
    casez (uart_tx_state)
      2'h0:
          if (start) begin
            \$9  = { 1'h1, data, 1'h0 };
          end
      2'h1:
          if (\$4 ) begin
            \$9  = \$5 ;
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$79 ) begin end
    \$10  = counter;
    casez (uart_tx_state)
      2'h0:
          if (start) begin
            \$10  = 9'h000;
          end
      2'h1:
          (* full_case = 32'd1 *)
          if (\$4 ) begin
            \$10  = 9'h000;
          end else begin
            \$10  = \$8 [8:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$79 ) begin end
    \$11  = bit_pos;
    casez (uart_tx_state)
      2'h0:
          if (start) begin
            \$11  = 4'h0;
          end
      2'h1:
          if (\$4 ) begin
            \$11  = \$6 [3:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$79 ) begin end
    \$12  = uart_tx_state;
    casez (uart_tx_state)
      2'h0:
          if (start) begin
            \$12  = 2'h1;
          end
      2'h1:
          if (\$4 ) begin
            if (\$7 ) begin
              \$12  = 2'h2;
            end
          end
      2'h2:
          \$12  = 2'h0;
    endcase
  end
  
  assign \$5  = { 1'h0, shift_reg[9:1] };
endmodule

(* src = "/home/runner/workspace/hardware/uart_rx.py:25" *)
(* generator = "Amaranth" *)
module \top.uart_rx_mod (clk, data, valid, rx);
  reg \$auto$verilog_backend.cc:2355:dump_module$80  = 0;
  wire \$1 ;
  wire [9:0] \$10 ;
  wire \$11 ;
  wire \$12 ;
  wire \$13 ;
  wire \$14 ;
  wire \$15 ;
  wire \$16 ;
  wire [1:0] \$17 ;
  reg [8:0] \$18 ;
  reg [2:0] \$19 ;
  wire \$2 ;
  reg [3:0] \$20 ;
  reg [7:0] \$21 ;
  reg [7:0] \$22 ;
  wire \$3 ;
  wire [9:0] \$4 ;
  wire \$5 ;
  wire [4:0] \$6 ;
  wire \$7 ;
  wire [9:0] \$8 ;
  wire \$9 ;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:31" *)
  reg [3:0] bit_pos = 4'h0;
  (* src = "/home/runner/workspace/hardware/ti60_f225.py:58" *)
  input clk;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:30" *)
  reg [8:0] counter = 9'h000;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:20" *)
  output [7:0] data;
  reg [7:0] data = 8'h00;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:22" *)
  reg error;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:19" *)
  input rx;
  wire rx;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:34" *)
  reg [1:0] rx_sync = 2'h3;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:32" *)
  reg [7:0] shift_reg = 8'h00;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  reg [2:0] uart_rx_state = 3'h0;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:21" *)
  output valid;
  reg valid;
  assign \$1  = ~ (* src = "/home/runner/workspace/hardware/uart_rx.py:44" *) rx_sync[1];
  assign \$2  = counter == (* src = "/home/runner/workspace/hardware/uart_rx.py:50" *) 8'hd8;
  assign \$3  = ~ (* src = "/home/runner/workspace/hardware/uart_rx.py:51" *) rx_sync[1];
  assign \$4  = counter + (* src = "/home/runner/workspace/hardware/uart_rx.py:57" *) 1'h1;
  assign \$5  = counter == (* src = "/home/runner/workspace/hardware/uart_rx.py:61" *) 9'h1b1;
  assign \$6  = bit_pos + (* src = "/home/runner/workspace/hardware/uart_rx.py:65" *) 1'h1;
  assign \$7  = bit_pos == (* src = "/home/runner/workspace/hardware/uart_rx.py:67" *) 3'h7;
  assign \$8  = counter + (* src = "/home/runner/workspace/hardware/uart_rx.py:70" *) 1'h1;
  assign \$9  = counter == (* src = "/home/runner/workspace/hardware/uart_rx.py:74" *) 9'h1b1;
  assign \$10  = counter + (* src = "/home/runner/workspace/hardware/uart_rx.py:81" *) 1'h1;
  assign \$11  = ! (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) uart_rx_state;
  assign \$12  = uart_rx_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 1'h1;
  assign \$13  = uart_rx_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h2;
  assign \$14  = uart_rx_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 2'h3;
  assign \$15  = uart_rx_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h4;
  assign \$16  = uart_rx_state == (* src = "/home/runner/workspace/.pythonlibs/lib/python3.11/site-packages/amaranth/hdl/_dsl.py:486" *) 3'h5;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:34" *)
  always @(posedge clk)
    rx_sync <= \$17 ;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:30" *)
  always @(posedge clk)
    counter <= \$18 ;
  (* src = "/nix/store/h097imm3w6dpx10qynrd2sz9fks2wbq8-python3-3.12.11/lib/python3.12/contextlib.py:144" *)
  always @(posedge clk)
    uart_rx_state <= \$19 ;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:31" *)
  always @(posedge clk)
    bit_pos <= \$20 ;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:32" *)
  always @(posedge clk)
    shift_reg <= \$21 ;
  (* src = "/home/runner/workspace/hardware/uart_rx.py:20" *)
  always @(posedge clk)
    data <= \$22 ;
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$80 ) begin end
    \$18  = counter;
    casez (uart_rx_state)
      3'h0:
          if (\$1 ) begin
            \$18  = 9'h000;
          end
      3'h1:
          (* full_case = 32'd1 *)
          if (\$2 ) begin
            if (\$3 ) begin
              \$18  = 9'h000;
            end
          end else begin
            \$18  = \$4 [8:0];
          end
      3'h2:
          (* full_case = 32'd1 *)
          if (\$5 ) begin
            \$18  = 9'h000;
          end else begin
            \$18  = \$8 [8:0];
          end
      3'h3:
          (* full_case = 32'd1 *)
          if (\$9 ) begin
          end else begin
            \$18  = \$10 [8:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$80 ) begin end
    \$19  = uart_rx_state;
    casez (uart_rx_state)
      3'h0:
          if (\$1 ) begin
            \$19  = 3'h1;
          end
      3'h1:
          if (\$2 ) begin
            (* full_case = 32'd1 *)
            if (\$3 ) begin
              \$19  = 3'h2;
            end else begin
              \$19  = 3'h0;
            end
          end
      3'h2:
          if (\$5 ) begin
            if (\$7 ) begin
              \$19  = 3'h3;
            end
          end
      3'h3:
          if (\$9 ) begin
            (* full_case = 32'd1 *)
            if (rx_sync[1]) begin
              \$19  = 3'h4;
            end else begin
              \$19  = 3'h5;
            end
          end
      3'h4:
          \$19  = 3'h0;
      3'h5:
          \$19  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$80 ) begin end
    \$20  = bit_pos;
    casez (uart_rx_state)
      3'h0:
          /* empty */;
      3'h1:
          if (\$2 ) begin
            if (\$3 ) begin
              \$20  = 4'h0;
            end
          end
      3'h2:
          if (\$5 ) begin
            \$20  = \$6 [3:0];
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$80 ) begin end
    \$21  = shift_reg;
    casez (uart_rx_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          if (\$5 ) begin
            \$21  = { rx_sync[1], shift_reg[7:1] };
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$80 ) begin end
    \$22  = data;
    casez (uart_rx_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          if (\$9 ) begin
            if (rx_sync[1]) begin
              \$22  = shift_reg;
            end
          end
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$80 ) begin end
    valid = 1'h0;
    casez (uart_rx_state)
      3'h0:
          valid = 1'h0;
      3'h1:
          valid = 1'h0;
      3'h2:
          valid = 1'h0;
      3'h3:
          valid = 1'h0;
      3'h4:
          valid = 1'h1;
      3'h5:
          valid = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2355:dump_module$80 ) begin end
    error = 1'h0;
    casez (uart_rx_state)
      3'h0:
          error = 1'h0;
      3'h1:
          error = 1'h0;
      3'h2:
          error = 1'h0;
      3'h3:
          error = 1'h0;
      3'h4:
          error = 1'h0;
      3'h5:
          error = 1'h1;
    endcase
  end
  
  assign \$17 [1] = rx_sync[0];
  assign \$17 [0] = rx;
endmodule
