Isolated in-memory ChurchSimulator in this separate page. Does not change the main IDE, saved Namespace, boot configuration, editor draft, or saved LUMPs. Canonical boot and fixture driver preparation run during Load; these are not tests in the lightning-bolt CapabilityTest. CHANGE driver words are encoded by the fixture, not accepted through the assembler.
Choose a test and load it. Saved Alice/Mallory binaries are fetched read-only.
The ascending-layout scenario compiles the current Alice source and Mallory source. It does not patch their instructions. Other scenarios select exact historical Alice/Mallory files, not the latest editor revisions. Their legacy literal LOAD indexes are adapted to current encodings in disposable RAM copies, then minted as separate fixture identities. Saved binaries and live IDE state are never changed. Thread drivers resume explicit continuations above retained poison roots.
The tuple tests use the existing 58-word Thread heap record, not the designer’s illustrative 18-word layout. Alice and Mallory run in separate Threads. Alice uses her CR5 heap; Mallory’s test driver has no grant to Alice’s heap. The allocator reserves fixture storage; real DWRITE/DREAD instructions exercise Alice’s access. Mallory’s baseline DREAD through empty CR4 faults NULL_CAP. With valid own CR5, indexed DREAD/DWRITE attempts targeting Alice’s tuple and immediate attempts one word past Mallory’s authorized Thread range fault RANGE without retiring. The existing instruction gate checks the owning Thread’s Namespace range, not a tuple ACL or the narrower heap layout. A positive DREAD at the same tuple-relative offset reads Mallory’s own record, not Alice’s. Denied attempts check exact first-fault evidence, unchanged data registers, and every Alice tuple word. No tuple ACL or new security mechanism is introduced. The tuple regression uses explicitly pinned baseline Alice/Mallory fixtures, not the latest editor revisions. This is a bounded simulator regression, not a proof for every attack, FPGA validation, or a Dijkstra messaging test.
Choose a tuple test to collect evidence.
The ascending-layout test compiles the current Alice/Mallory source, without historical instruction patches. It is an isolated fixture, not the selected NewLayout image, admission path or FPGA proof. Boot.Thread is NS[2]; Thread.2 and Thread.3 are NS[11] and NS[12]. A preboot fixture binds the declared own-RW rows, provisions CR0 driver continuations and places each actor’s E capability in that actor’s own CR1. Alice's data is checked at Mallory's fault; survival through fault restart is not yet verified. Reset loaded test reloads the initial image and does not preserve the stash.
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